Institutionen för systemteknik - DiVA portalliu.diva-portal.org/smash/get/diva2:660503/FULLTEXT01.pdf · Institutionen för systemteknik Department of Electrical Engineering

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

Connected Me - Proof of Concept

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan vid Linköpings universitet

av

Dilip Kumar [email protected]

LiTH-ISY-EX--11/4504--SE

Linköping 2011

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

Connected Me - Proof of Concept

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av


LiTH-ISY-EX--11/4504--SE

Handledare: J Jacob Wiknerisy, Linköpings universitet

Jan HederenEricsson AB

Examinator: Oscar Gustafssonisy, Linköpings universitet

Linköping, 22 August, 2011

Avdelning, InstitutionDivision, Department

Division of Automatic ControlDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2011-08-22

SpråkLanguage

� Svenska/Swedish� Engelska/English

�

�

RapporttypReport category

� Licentiatavhandling� Examensarbete� C-uppsats� D-uppsats� Övrig rapport�

�

URL för elektronisk versionhttp://www.control.isy.liu.se

http://www.ep.liu.se

ISBN—

ISRNLiTH-ISY-EX--11/4504--SE

Serietitel och serienummerTitle of series, numbering

ISSN—

TitelTitle Connected Me - Proof of Concept

FörfattareAuthor


SammanfattningAbstract

Connected Me is a Human Body Communication (HBC) system, which is used fortransferring data through human body. The working principle is based on theorycalled Body Coupled Communication (BCC), which uses electrostatic couplingfor transferring data between device and human body. Capacitance between bodyand electrode acts as an electrical interface between devices. BCC has become aprominent research area in the field of Personal Area Network (PAN), introducedby Zimmerman in 1995. Until now there have been significant amount of paperspublished on human body models and Analog Front End (AFE), but only fewreports are available in digital baseband processing.

The proposed Human Body Communication (HBC) system consists ofdigital baseband and AFE. Digital baseband is used for transferring data packets.AFE is designed for reconstructing signal shape after signal degradation causedby the human body. This thesis implements high speed serial digital commu-nication system for a human body channel. Available modulation schemes andcharacteristics of the Physical layer (PHY) with respect to human body channelare analyzed before implementing the system. The outcome of this thesis is aFPGA demonstrator that shows the possibility of communication through thehuman body.

NyckelordKeywords Connected Me, Physical Layer of HBC, Human Body Communication System,

Manchester Encoder

Abstract

Connected Me is a Human Body Communication (HBC) system, which is used fortransferring data through human body. The working principle is based on theorycalled Body Coupled Communication (BCC), which uses electrostatic coupling fortransferring data between device and human body. Capacitance between bodyand electrode acts as an electrical interface between devices. BCC has become aprominent research area in the field of Personal Area Network (PAN), introducedby Zimmerman in 1995. Until now there have been significant amount of paperspublished on human body models and Analog Front End (AFE), but only fewreports are available in digital baseband processing.

The proposed HBC system consists of digital baseband and AFE. Digital base-band is used for transferring data packets. AFE is designed for reconstructingsignal shape after signal degradation caused by the human body. This thesisimplements high speed serial digital communication system for a human bodychannel. Available modulation schemes and characteristics of the Physical layer(PHY) with respect to human body channel are analyzed before implementingthe system. The outcome of this thesis is a FPGA demonstrator that shows thepossibility of communication through the human body.

v

Acknowledgments

I would like to thank Mr. Jan Hederen and Ericsson AB for this exciting thesisopportunity and their full support during the project. I would like to acknowledgemy supervisor Dr. J Jacob Wikner for his guidance and brilliant ideas. I wouldlike to take this opportunity to thank my examiner Dr. Oscar Gustafsson.

I would like to thank my fellow project teammates, Kiran Uliveppa Kariyan-navar and Bibin Babu for their unconditional cooperation and support. Finally, Iam grateful to my friends Padma and Dinesh for spending their summer workingat Fo-lab.

Above all, I am obliged to thank my Mom and Dad for their unconditional loveand affection from India.

vii

Contents

1 Introduction 51.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2 Project plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.4 Expected results of the thesis . . . . . . . . . . . . . . . . . . . . . 81.5 Outline of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Literature survey 92.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Low frequency operation . . . . . . . . . . . . . . . . . . . . 102.1.2 Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Selection of modulation scheme . . . . . . . . . . . . . . . . . . . . 112.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Digital baseband 133.1 Software model of digital baseband . . . . . . . . . . . . . . . . . . 13

3.1.1 Development of digital baseband . . . . . . . . . . . . . . . 133.1.2 Evaluation of the software model . . . . . . . . . . . . . . . 17

3.2 Hardware model of digital baseband . . . . . . . . . . . . . . . . . 173.2.1 Transmitter Physical layer . . . . . . . . . . . . . . . . . . . 183.2.2 Receiver Physical layer . . . . . . . . . . . . . . . . . . . . . 20

4 Application layer 254.1 PS/2 Keyboard application layer . . . . . . . . . . . . . . . . . . . 264.2 Audio streaming application layer . . . . . . . . . . . . . . . . . . . 274.3 File transfer application layer . . . . . . . . . . . . . . . . . . . . . 284.4 Bit Error Rate tester . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.4.1 Test pattern generator . . . . . . . . . . . . . . . . . . . . . 294.4.2 Bit Error Rate calculator . . . . . . . . . . . . . . . . . . . 29

5 Results and discussion 335.1 Datarate vs. Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . 335.2 Clock oversampling ratio vs. BER . . . . . . . . . . . . . . . . . . 345.3 Datarate vs. Power consumption of transmitter . . . . . . . . . . . 35

ix

x Contents

5.4 Datarate vs. Power consumption of receiver . . . . . . . . . . . . . 37

6 Future work and conclusion 396.1 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Bibliography 43

A Transmitter Baseband (VHDL) 45

B Receiver Baseband (VHDL) 52

C File Transfer Application Layer: Transmitter (VHDL) 61

D File Transfer Application Layer: Receiver (VHDL) 67

E Audio Streaming Application Layer: Transmitter (VHDL) 71

F Audio Streaming Application Layer: Receiver (VHDL) 78

List of Tables1.1 Sub-projects of Connected Me. . . . . . . . . . . . . . . . . . . . . 7

3.1 Requirement specification for software model . . . . . . . . . . . . 14

4.1 Length field and application layers . . . . . . . . . . . . . . . . . . 25

5.1 Transmitter PHY layer: Power consumption by block type . . . . . 355.2 Receiver PHY layer: Power consumption by block type . . . . . . . 36

2 Contents

List of Figures1.1 Body Area Network (BAN) using electrostatic coupling. . . . . . . 61.2 System overview of Connected Me for BCC. . . . . . . . . . . . . . 7

2.1 Zimmerman’s lumped element model of BCC. . . . . . . . . . . . . 9

3.1 Body coupled communication frame structure used in software model. 153.2 Simulink model illustrating data processing to a frame at transmitter. 153.3 Simulink model of receiving data at receiver. . . . . . . . . . . . . 163.4 Manchester decoder samples input to decode data. . . . . . . . . . 163.5 The test setup for the software model to measure BER. . . . . . . 173.6 Body coupled communication final frame structure used in hardware. 183.7 Physical layer of the transmitter. . . . . . . . . . . . . . . . . . . . 193.8 Manchester decoder: transmission clock is recovered by over-sampling

preamble to find the bit transition. . . . . . . . . . . . . . . . . . . 203.9 Physical layer of the receiver. . . . . . . . . . . . . . . . . . . . . . 23

4.1 Overview of transmitter application layer interface to the PHY. . . 264.2 Overview of receiver application layer interface to the PHY. . . . . 274.3 A 19-bit LFSR used in pseudo-random test pattern generation. . . 294.4 Test pattern generator that transmits a pseudo-random data to the

test system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.5 BER error detector and calculator. . . . . . . . . . . . . . . . . . . 31

5.1 Datarate vs. BER for clock oversampling ratio of 20. . . . . . . . . 345.2 Datarate vs. Electrode area vs. Clock oversampling ratio vs. BER. 355.3 Datarate vs. Dynamic power consumption for transmitter PHY. . 365.4 Datarate vs. Dynamic power consumption for receiver PHY. . . . 37

6.1 Connected Me development team at the Ericsson booth at ECCTD2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2 Hans Vestberg, CEO of Ericsson demonstrating Connected Me atCES 2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

List of Acronyms

AFE = Analog Front End.BAN = Body Area Network.BER = Bit Error Rate.CRC = Cyclic Redundancy Check.EMF = Electromagnetic Field.EOF = End-of-packet.FEC = Forward Error Correction.HBC = Human Body Communication.LFSR = Linear Feedback Shift Register.MAC = Media Access Control.PAN = Personal Area Network.PER = Packet Error Rate.PHY = Physical Layer.PISO = Parallel Input Serial Output.SNR = Signal to Noise Ratio.SOF = Start-of-Packet.WBAN = Wireless Body Area Network.

3

Chapter 1

Introduction

1.1 BackgroundA computer network is a collection of nodes interconnected by channels for ex-changing of digital information and sharing computational resources. It is classi-fied based on its geographical scope into one of the following networks, PersonalArea Network (PAN), Local Area Network (LAN), Metropolitan Area Network(MAN) or Wide Area Network (WAN).

A PAN can expand upto 10 meters which is typically used for communica-tion among devices near to one person. Some of the nodes used in PAN can becomputing devices as laptops and mobile phones, transponders as microphones,earphones and bio medical sensors. These nodes are typically connected by phys-ical cables and radio waves (wireless). Where as, Body Area Network (BAN) isused to describe the application of wearable computing devices in wireless PANfor communications on, in and near the human body [10].

Near-field signaling is used in BANs, where the distances between the nodesare up to 2 meters. In order to cover a smaller distance, capacitive BCC can beused instead of Electromagnetic Field (EMF) for signal transmissions [12]. Thefigure (Figure 1.1) shows a BAN using electrostatic capacitive coupling for sendingdata. The benefits of BCC are low frequency operation, less power consumptionand less signal interception; As the signal is not radiated beyond the human body,eavesdropping is avoided.

1.2 Project planThe aim of the main project "Connected Me" is to build a hardware prototype inthree sub-projects. Three sub-projects were structured as shown in table 1.1 forinvestigating possibility of using human body as a channel for communication.

This thesis is written for sub-project 1. Sub-project 1 is to implement a higherdata-rate digital communication system for a human body channel. Sub-project2 is to do detailed analysis of prerequisites with respect to baseband and Analog

5

6 Introduction

Figure 1.1. Body Area Network (BAN) using electrostatic coupling.

Front End (AFE) modeling, the AFE model is used in the demo model for proof ofconcept. Sub-project 3 deals with building a hardware prototype for HBC systemand evaluating the human body model and baseband.

1.3 System description 7

Table 1.1. Sub-projects of Connected Me.

No. Title (Thesis Registration Number)1 Connected Me - Proof of concepts (LiTH-ISY-EX–11/4504–SE)2 Connecting the human body - models, connections, competition

(LiTH-ISY-EX–11/4505–SE)3 Connected Me : Hardware for high speed BCC (LiTH-ISY-EX–

11/4503–SE)

1.3 System descriptionFigure 1.2 shows system level functional block diagram of the developed "Con-nected Me" system. It implements Manchester encoder simplex communicationsystem which operates at 12 Mbps data rate. A simplex communication systemsends data traffic in only one direction from transmitter to receiver. A transmitterdevice sends data through body to receiver device. Electrodes are used to coupledata from transmitter to body and receive data to receiver.

Figure 1.2. System overview of Connected Me for BCC.

Connected Me is developed with off-shelf analog discrete components and field-programmable gate array (FPGA). FPGA implements digital baseband processinglogics; transmitter (TX) and receiver (RX) AFEs are implemented with commer-cially available discrete components. AFE TX is a line driver circuitry connectedto Manchester encoder output from FPGA. The output of AFE TX is a singleended 4.5 V peak-peak signal. AFE RX reconstructs signal shape of the received

8 Introduction

signal from body; it also implements a multi-stage amplifier and a Schmitt triggercircuitry.

1.4 Expected results of the thesisThe Scope of the thesis is to develop a high data rate digital communication systemand obtain maximum data rate on the human body link by using the recommendedmodulation scheme from literature survey. A Physical Layer (PHY) should bedeveloped for transferring data packets in bits through the human body, also anerror detection mechanism is to be integrated in the baseband for reliable datatransfer. A Bit Error Rate (BER) analyzer will be needed for evaluation andimprovement of system. The outcome of this thesis will be a FPGA demonstratorthat shows the possibility of communication over the human body.

1.5 Outline of the thesisThis section outlines contents of the thesis under each chapter. In chapter 2,literature survey findings are discussed. The prerequisites of digital basebandwith respect to the human body channel are presented. It is explained the reasonwhy Manchester encoder is chosen as the modulation scheme for baseband. Inchapter 3, the PHY layer for digital baseband of HBC system is developed. PHYis developed in two stages. As the first stage in development, a Matlab’s simulinkmodel of baseband is developed. This is integrated with the AFE model from sub-project 2 in the matlab environment to study the human body channel. In secondstage, the digital baseband model from software development is designed in RTLto create a hardware prototype for further analysis in sub-project 3. In chapter 4,three application layers with different uses are developed for FPGA demonstrator.And lastly, BER calculator is developed for performance evaluation of system inchapter 4 before the results of this work and future work are discussed in chapter5.

Chapter 2

Literature survey

According to Zimmerman, a human body is a node which may be modeled as alumped element model as shown in figure 2.1. Electrical signals are electrostaticallycoupled to the human body through electrodes at transmitter and receiver [12].Electrostatic coupling is defined as the transfer of electric energy by means of thecapacitance between two surfaces.

Figure 2.1. Zimmerman’s lumped element model of BCC.

9

10 Literature survey

A potential difference establishes an electric filed which transfer charges fromone surface to another surface. Thus, data can be transferred through the bodyby modulating this potential difference at the transmitter between a electrode andbody. The Receiver demodulates data by detecting a potential difference at thereceiver electrode. Electrodes which are used to couple electrical signal are madeof conductive material.

2.1 Motivation

One of the key advantages of the BCC is its simplified communication protocol.Any two devices are easily paired by touching them and signals are capacitivelycoupled into the body. The clothes that he/she wearing act as a dielectric, devicescan be in pocket as direct skin contact with electrodes is not needed. A few otherbenefits of BCC are as follows.

2.1.1 Low frequency operation

A BAN usually spans around 1 to 2 meters. The network nodes are placed asclose as half a meter away. A radio transmission requires a carrier frequencyof at least 600 MHz for radiating through an antenna of half a meter length.Thus, the carrier frequency needs up-conversion before the transmission to reducethe antenna size as in for e.g. Bluetooth (a near-field technology for BAN). Asopposed to this, the near-field electrostatic coupling signal transmission does notup-convert the baseband frequency to reduce the size of the electrode for matchingthe wavelength of the carrier frequency. Here, the size of the electrode is increasedfor maximum conductivity, even then the size of the electrode is very smallerthan the wavelength of the carrier frequency. For example, to transmit a 10 MHzfrequency radio signal, radio transmission without any up-conversion needs anantenna (half-dipole) of about 15 meters length (improved antenna design canreduce the antenna size only to some extent). Where as the electrostatic couplingcan achieve it with a good electrode of just 0.05 meters (300 times smaller). Theelectrostatic coupling is at least a far better choice for the nodes operating at alower radio frequency, where the wavelength is larger than the distance betweenany communicating nodes as in BAN [12].

2.1.2 Interference

The electrodes that are used for electrostatic coupling are inefficient EMF trans-mitter/receiver at the operating carrier frequency to cause any significant inter-ception. The electric field strength in the near-field signaling falls off steeply withan increase in distance, hence a little interference from a distant transmitter inneighbor BAN [12]. The time division or frequency division multi-channel accesswill avoid interference from the devices with in the same network.

2.2 Selection of modulation scheme 11

2.1.3 PowerThe EMF transmission propagates beyond the vicinity of a human body onlyto connect two nodes on the body, this is a loss of energy. According to [8],it was found that air propagation channel has a larger path loss than the bodychannel for lower radio frequencies; on the contrary, transmission power of near-filed electrostatic signaling for body channel can be reduced quite significantly tomatch the performance of air propagation channel. Also AFE and baseband donot need to not work at GHz, since the electrostatic coupling transmits the signaldirectly without any up-conversion. This saves a lot of power in dynamic powerconsumption as in P = 1

2 × C × V 2 × F .

2.2 Selection of modulation schemeA modulation scheme can be either narrowband transmission or wideband trans-mission based on the frequency response of the communicating channel to themodulating output signal. It is narrowband if the frequency response of the chan-nel is flat, otherwise it is wideband for non flat response. The Signal to NoiseRatio (SNR) of the received signal determines the bit-error rate of the system. Innarrowband transmission, the SNR can be improved by increasing the transmitpower, whereas in wideband transmission increasing the bandwidth of the signalimproves the SNR performance because the received signal is less susceptible tonoise and other interference, which typically affects only a narrow region of thetotal signal. Thus, trading power for bandwidth will result in a low power com-munication system but leads to spectrum inefficiency.

In [7] data was modulated using various digital modulation schemes beforesending it through the human body to measure the performance of the modula-tion to noise distortion. The Modulation schemes with more constellation pointsare distorted more and difficult to recover than the modulation schemes withfewer constellation points. This limits the length of the communicating channelto use. The Error Vector Magnitude (EVM) requirement for BCC is more forcomplex modulation schemes than IEEE standard requirements set for air-borneradio transmission.

Manchester coding is most commonly used line encoder for its simple hardwareimplementation. It is used in wideband signaling, which guarantees regular bittransition irrespective of the message at the expense of doubling the data rate.The regular bit transitions help in easier clock recovery, and removes the DCcomponent which leads to low susceptible to noise.

2.3 ConclusionUntil now there have been many reports published on AFEs for electrostatic cou-pling HBC system. Some of them were fabricated in a chip and tested for fewscenarios on the human body by transferring small sized data. IEEE had launcheda working group for Wireless Body Area Network (WBAN) in late 2007, which

12 Literature survey

is known as 802.15.6, this group is defining the the PHY and Media Access Con-trol (MAC) layers for HBC system along with other developments for narrowbandand ultra wideband communication layers in WBAN. There are two proposals ofpacket frame structure for HBC system were made in [5], one for fixed data rateand the other for variable data rate communication systems. But, their details arenot given.

The output of this thesis is a hardware prototype, with a digital baseband andPHY layer for the human body channel. The digital baseband of this thesis andthe AFE model developed by sub-project 2 are integrated in sub-project 3. Thesub-project 3 studies the HBC and dependencies of environmental factors in themodel. Measurement results are analyzed to improve the AFE model and tunethe demodulation scheme in the receiver’s baseband for low bit error rate in orderto increase the data transfer rate.

Chapter 3

Digital baseband

3.1 Software model of digital basebandThe software model of the digital baseband is a functionality model with inherentcontrol signals for verifying the working principle of a HBC system. The aim ofthe software model is to integrate the digital baseband in the software loop testing.The software loop consists of the digital baseband transmitter and receiver, theAFEs and the human body equivalent RC model. The loop testing helps in tuningthe AFE and the baseband parameters. Furthermore, the loop test addresses non-ideal effects like interference and noise before finalizing the design for the hardwareimplementation of digital baseband.

3.1.1 Development of digital basebandThe design of digital baseband for the transmitter and the receiver satisfies therequirements as defined in Table 3.1. The baseband implements a PHY for a sim-ple packet based HBC system. The digital baseband adopts IEEE 802.3 Ethernetstandard as the transmission protocol. IEEE 802.3 standard defines Manchesterencoder as the digital baseband modulation scheme. Hence, it is easier to imple-ment IEEE Ethernet based packet frame format in the baseband where Manchesterencoder is used.

The baseband implements a fixed data rate simplex transmission system. Du-plex systems need multiple channel access mechanism with collision detectors thatare outside the ambit of this subproject.

Transmitter

The Pseudo-random binary data bit generator is the data source for the softwaremodel of the digital baseband. The continuous input stream of raw binary databits divides into many equal sized small segments called packets. The basebandimplements the PHY for transmitting data packets into the transmission mediumin a form of electrical signal. The data packets are flanked by header and trail-

13

14 Digital baseband

Table 3.1. Requirement specification for software model

Specification1 Packet based communication system2 Manchester encoder and decoder3 Simplex system4 Fixed data rate5 Error detection capability

Transmitter1 IEEE 802.3 Ethernet frame format2 Fixed packet size3 Random data input4 CRC-32

Receiver1 Clock recovery2 Packet detector3 Packet Error Rate (PER) counter4 Bit Error Rate (BER) calculator

ers into complete packets. A preamble is appended for clock synchronization andpacket detection in the receiver. The packet frame format of the software modelof the baseband does not have length and address fields similarly to IEEE Ether-net standard because the characteristics of the human body as the transmissionmedium is unknown. Instead user sets the packet size and transmission data ratebefore each simulation. A 32 bit Cyclic Redundancy Check (CRC) check value isadded in the end of packet and sent through a serial data output line. The outputbits are Manchester encoded before it transmits into the channel. Manchester en-coder defines binary data bit ’1’ as a rise transition (0 to 1) and binary data bit’0’ as a fall transition (1 to 0).A complete packet consists of

• A Start of Packet (SOP) of 7 octets of 10101010.

• A delimiter of 1 octet of 10101011.

• Fixed size data.

• CRC-32 (IEEE 802.3) Forward Error Correction (FEC) code in the trailer.

The SOP helps in detecting the presence of packet. The delimiter to determinethe bit location where the user data (payload) start. CRC-32 adds 32-bit checkvalue at the end of each packet to detect the transmission error in the receivedpacket. An n-bits check value is the remainder from a long division by n-th degreepolynomial on the block of data to be protected. The IEEE CRC-32 polynomial

3.1 Software model of digital baseband 15

Figure 3.1. Body coupled communication frame structure used in software model.

7−bytes

CRC−32

(IEEE 802.3)

Payload

(Fixed number of bytes)

Preamble of

7−Octets of

10101010 10101011

1−Octet of

Delimiter of

4−byteNo. of bytes is set prior to simulation1−byte

Figure 3.2. Simulink model illustrating data processing to a frame at transmitter.

of

x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

is the divider used to calculate a 32-bit check value.

Receiver

The receiver has four major functions namely,

i. Clock synchronization

ii. Packet detection

iii. Error detection

iv. Baseband digital data processing

The receiver baseband implements a fixed data rate system. Fixed data ratesystem avoids locking to frequencies other than the desired frequency. Clock re-covery uses clock over-sampling technique on the encoded input to recover thebaseband clock. It uses a clock of 10 times higher than baseband’s clock frequencyfor finding a transition edge in the preamble. It counts the number of oversam-pling clock pulses between the transition edges. When the number of pulses isequivalent to the baseband’s clock period between transition edges, a synchronousclock pulse is generated whose time period is set to the baseband’s clock period.

A synchronous pulse which acts as the Manchester decoder’s sampling instantis as shown in the Figure 3.4. The clock recovery is ON only during the preamble

16 Digital baseband

Figure 3.3. Simulink model of receiving data at receiver.

period of the incoming data packet. It is disabled after a packet (SOP) is detected.Ideally, only two times oversampling clock can be used in clock recovery, but tohave tolerance for a wider pulse duty-cycle of about 75% on the input signal andfor increased precision in the recovered clock, a high clock over-sampling ratio isdesired.

The decoder samples at the second half cycle of a bit period

data ’1’ data ’0’ data ’1’ data ’1’

Figure 3.4. Manchester decoder samples input to decode data.

Packet detection is to detect the preamble for the presence of packet in thechannel. The delimiter determines the binary bit position the payload starts ina packet. The receiver first tries to match the preamble for at least 16 bits ofalternate ’1’ and ’0’ to detect the presence of packet in the input stream. After apreamble is successfully detected, a delimiter of bit pattern ’11’ is searched in aspace of 48 bits. If the bit pattern ’11’ is not detected, an error flag is raised andthe entire procedure is restarted for preamble detection.

In this software model there is no baseband digital data processing done, ratherthe data recovered from the received packet is only used to calculate BER. TheCRC-32 check value is used to detect the transmission error. The long division isperformed on both the received data and CRC-32 check value, if the remainder iszero the received packet is error free.

3.2 Hardware model of digital baseband 17

3.1.2 Evaluation of the software modelPerformance of the software baseband model is evaluated after connecting thehuman body equivalent (RC) electrical model and AFE with the baseband. Nonideal finite rise and fall time of the signals, and signal interference are introduced inthe system. The test set-up is shown in the Figure 3.5. PER and BER calculatorprovide the performance metrics. PER is defined as the number of CRC OKreceived data packets to the total number of packets sent by the transmitter. PERcalculator lists the number of packets that are lost because of missed delimiter,preamble lost, and the number of incorrect packets for CRC error. BER is the totalnumber of incorrectly received bits to the total number of bits transmitted. TheBER is calculated as illustrated in the Figure 3.5 where received bits are mappedto transmitted bits. A number of bit positions that does not match is counted.This count of number of incorrect bits and the total number of bits accounted forit will give the BER.

Modulation Output

Physical layer

Transmitter Electrical Model

Human BodyPhysical Layer

(PHY)

Receiver

(PHY)

Finite Rise/Fall Time SNR

0

1

1

1

1

0

0

1

0

0

1

1

0

0

0

0

0

1

1

1

1

0

Error

Pseudo−random

Binary Input

Synchronized

Received Binary Data

BER Offline

Calculator

Decoded Data

Figure 3.5. The test setup for the software model to measure BER.

3.2 Hardware model of digital basebandSoftware model is the first step in developing a digital baseband for HBC system.Software model has implicit control signals for synchronization between functional

18 Digital baseband

blocks. That is, there is no need of deriving control signals explicitly for the soft-ware model, where as hardware model is a register transfer level (RTL) model andcontrol signals are derived for synchronizing the sub-blocks in the system. Thesoftware model needs improvement considering practical scenarios before imple-menting the software model in hardware.

The following changes are done in the packet frame structure: 16-bits lengthfield to accommodate up to 216 bytes in a packet including header and the trailerfields; 4-bits each for source and destination address fields for implementing aBAN of 16 devices; 16-bit CRC for FEC based on the maximum data block toprotect. Thus protecting a packet of 216 − 1 bits from errors going undetected [6].CRC-16/CCITT generating polynomial is used to compute the 16-bit check valuefor forward error detection.

Figure 3.6. Body coupled communication final frame structure used in hardware.

PayloadSource Destination

Address

(4−bits)(4−bits)

Address

(16−bits)

1−Octet of

10101011

DelimiterPreamble of

10101010

7−Octets of

(Variable size) 16−bits

CRC−16

CCIT

Length

Software model has no application data processing, it generates random data.Hardware model implements three application layers for different user applicationsfor digital data processing before sending data packets to the PHY layer.

The PHY layer for the human body channel was implemented with Altera’sDSP Builder for Simulink, and the Application layers were implemented in VHDL.The Cyclone-II DE2-70 Development FPGA Board from Altera was chosen forverification of the project.

3.2.1 Transmitter Physical layerThe PHY provides electrical procedural interface for logical data packets from thetop layers. It defines clock synchronization, packet detection, and error detectioncapability for successful communication between the nodes in a network. The PHYalso defines logical interface to the top layer. The top layer has to transmit userdata packet to the PHY layer byte by byte in parallel with synchronized Start-of-Packet (SOF) and End-of-packet (EOF) control signals to indicate the first andlast byte of a data packet. Totally, two control lines and 8-bit data bus are used tosetup the connection between the top layer and the PHY. A transmission of newpacket from application layer to PHY is initiated when the control signal fromPHY goes low.

The effective payload data rate achieved by the PHY is lesser than the transmis-sion rate, because length field is calculated in PHY after storing the data receivedfrom application layer. Payload data rate can be improved when the length fieldis directly received from application layer.

The PHY of the transmitter has four stages: assembling packets, multiplexingpreamble and assembled packet, Parallel Input Serial Output (PISO) that con-


EOPData

(8−bit)

(Big−endian)

Assembler

Length field

Address field

Payload

MUX

Preamble

PISO CRC−16

Interface to Application LayerREADY acknowledgement to successful transmission

of the received packet

Encoder

ManchesterTX OUT

SOP

Figure 3.7. Physical layer of the transmitter.

verts byte to bits and transmitting Manchester encoded bits into the transmissionmedium. A complete packet is formed from the stored data in the memory in theassembler. The length field value (16-bit) and address fields values (8-bit) are inthe lowest address memory locations. The data received from the application layer(variable size) are in the higher address memory locations. Big-endian storage for-mat is followed as in, the most significant byte of a data word is stored first andleast significant data byte is stored in the next address memory location. Once theassembling is done READY control signal is set to HIGH. Now, the transmissionto the channel is started by first reading out the preamble from the look up table(LUT), followed by the data packet in the memory, and finally reading out thecalculated CRC check field through PISO.

When the last byte of data packet is read, the remainder from the long divisionfor CRC is transmitted in the end of the packet. The 16-bit check field for FECis being calculated while the transmission of data is taking place. READY signalis de-asserted once the CRC 16-bit check value is transmitted. A PISO is used inbyte to bit conversion for serial data transmission.

A state machine is implemented in PHY to build a packet frame from thepayload data received from application layer. Application layer upon sensing lowstate of the READY signal from PHY and if there is any payload available totransfer, will send the payload data, SOP and EOP signals to PHY. While PHYis receiving payload data from application layer the length counter is incrementedby ’1’ for every byte it receives. After an EOP is received the final length countervalue is stored in their corresponding memory locations in the packet frame. Apacket is transferred serially with binary data bits are Manchester encoded withthe clock. Manchester encoder is an ex-or logical gate with the data and clock asits input.

20 Digital baseband

3.2.2 Receiver Physical layer

Receiver PHY is implemented in a finite-state machine. It’s initial state is pream-ble detection. While in preamble detection clock synchronizer recovers the base-band clock from the Manchester encoded input data. Packet detection is com-pleted when at least two successive octets of 10101010 in a preamble of 62-bitsof alternate 1’s and 0’s are successfully decoded by the receiver. After a packetis detected, clock synchronizer is disabled and a delimiter of binary data ’11’ issearched in incoming packet to determine the bit position where the header be-gins. Header is decoded for 16-bit length field which determines how many bytesto receive from the channel before the state machine will go to preamble detectionof next incoming packet.

Synchronous Clock Generator to hit the sweet spot

Period CheckPeriod CheckPeriod Check

Duty cycle check

sweet spot

Period check=(2 × n) ± 1,(2 × n)

Duty cycle ckeck=n,n+1

Known edge is delayed and triggered the

Figure 3.8. Manchester decoder: transmission clock is recovered by over-samplingpreamble to find the bit transition.

BAN is used to connect devices in a range of applications like for exampledelivering small data virtual business card (VCS), and in applications with largerpayload for file transfer and streaming content. Hence a packet of fixed payloadsize for all data services is inefficient and power consuming. So, a 16-bit length fieldis added in the packet header to make the communication system more compatibleand efficient to use in different applications. In this way, the power consumptionfrom the bandwidth loss from appending zeros to fill the packet is avoided. Thislength field says how many bytes in total are packed in a packet. A packet willhave a minimum of 6 bytes excluding preamble and delimiter, header of 3-byte,payload of at least 1 byte and CRC FEC code of 2-byte.

A packet received by receiver is Manchester decoded by recovered clock andstored in bytes in an incremental byte-addressable memory. Memory should belarge enough to store a maximum size packet that is in use. Memory is addressedby a 16-bit counter, which is used to count the number of bytes in received data.PHY sets the READY signal for 8 clock cycles to mark a new packet is received.Then an application layer reads the decoded data from memory.


Clock synchronizer

Binary data output is Manchester encoded with transmitter clock in transmitterto protect data from the channel noise and for easier clock recovery in the receiver.Clock synchronizer in receiver recovers the baseband clock from the encoded binarystreaming input of the receiver. Manchester encoder is defined as a rising transition‘0´ to ‘1´ for binary data ‘1´ and a falling transition ‘1´ to ‘0´ for binary data‘0´. Hence, to decode the data correctly in receiver, a decoder should sample thebinary streaming input at the second half cycle of a bit period.

Baseband clock is recovered by over-sampling preamble to find the bit tran-sition edge, it is used as reference point by clock generator circuit to generatebaseband clock. The clock generator will generate one pulse for every n over-sampling clock pulses at an internal of one baseband clock, ’n’ is defined as inequation 3.1.

There are two properties met by clock recovery circuit before it generates recov-ered clock to verify that the generated clock has same clock phase to the encodedinput. Thus, it avoids locking to noise or any form of interference picked by thechannel. At First, since the Manchester encoded output signal of a preamble of bits10101010 has half the transmitter clock frequency, so a number of over-samplingclock pulses between one positive transition edge to the next positive transitionedge of the encoded input should be equal to (2 × n) ± 1 during preamble beforeit is declared as packet detected. This condition is called period check. Secondly,the first complete positive negative half cycles having a pulse duty cycle of 45%to 55% will trigger the clock generator. These two conditions are to ensure thatclock synchronizer is locking to the correct phase of the encoded input.

n = Over-sampling clock frequency at the receiverBaseband clock frequency at the transmitter (3.1)

To tolerate a duty cycle up to 75%, sampling point of Manchester decoder isselected to be in the fourth quarter of a bit period as shown in figure 3.8. Hence, byhaving these requirements for recovering the baseband clock, Manchester decoderwill have optimal sampling points against phase changes in received signal.

It was found that for higher data rate the Manchester encoded signal in anarrow bandwidth human body channel (i.e phase and frequency response are non-flat with frequencies) will incur phase jitters. This has duty cycle effect in AFEoutput. The subproject 2 discusses more on wide-band signaling effect in narrowband channel. Hence by having the clock synchronizer that chooses sampling pointfor Manchester decoder based on its bit error rate will have low BER againstchannel changes. This algorithm will determine the number of master clock cyclesto delay the sampling point.

CRC receiver - Error detection circuitry

The CRC detector is built from shift registers and logical gates to implementCRC-16/CCITT polynomial long division. The registers are cleared before CRCcalculation starts. After the last bit is received, it’s shifted into the least significantbit of the shift register. An additional 16 bit 0’s are shifted in before reading

22 Digital baseband

the long division remainder in the shift register for declaring packet error. Theremainder must be zero to declare a packet free of transmission error.


Ad

dre

ss

Clo

ck

Sy

nch

ron

izer

Pre

amb

le

Det

ecto

r

Dec

oder

Man

ches

ter

Del

imit

er

(SO

P)

Det

ecto

rE

xtr

acto

r

Len

gth

fie

ld

CR

C−

16

Det

ecto

r

SIP

O

Pay

load

dat

a

Mem

ory

for

Mem

ory

Ad

dre

ssG

ener

ator

En

able

RX

IN

Clo

ck

Clo

ck

Dat

a (8

−b

it)

Dis

able

Add

ress

Len

gth

fie

ld

Dec

od

ed D

ata

Interface to Application layer

RE

AD

Y

Err

or

Dat

a

Rea

d

Figure 3.9. Physical layer of the receiver.

Chapter 4

Application layer

Application layer processes user data to sizable packets. It transfers packets tothe PHY layer. Its main function is to process user data that is generated from anapplication into a small data packets which can be transmitted over PHY. Basedon the nature of application in use, a packet can be in few bytes to many hundredsbytes of processed data. Similarly, the Application layer in receiver opens thepackets and process them back into desired format for the application.

To exploit wider bandwidth supported by human body channel and becauseof its use in BAN network, there are three application layers targeting differentapplications and BER tester developed in this chapter. A multiplexer is used tointerface all application layers to the transmitter PHY layer. Application layer isselected to drive packets to PHY layer. Where as in the receiver, based on the16-bit length field (see Table 4.1) a packet is sent to the right application layer.

Table 4.1. Length field and application layers

Length Field (Payload (Totallength - 1) +Header (3 byte) + CRC (2 byte))

Application Layer

5 PS/2 Keyboard Application layer1028 / 260 / 68 / 36 Audio Application layer1030 File Transfer Application layer8196 BER Testing mode

The application layers that were developed in this project are as follows,

i. PS/2 Keyboard Application Layer

ii. Audio Streaming Application Layer

iii. File Transfer Application Layer

iv. BER Tester

25

26 Application layer

READY

layer

layer

Keyboard

PS/2

Audio

Application

File Transfer

Application

Application

layer

Test

BER

Generator

Transmitter

Layer

Physical

LCD

TX OUT

SOP

EOP

DATA

8−bit

SOP

SOP

SOP

SOP

EOP

EOP

EOP

EOP

DATA

DATA

DATA

DATA

MUX

ASCII

Scan code

ASCII

FIL

E T

RA

NS

FE

R

Mode

AU

DIO

Mode

BE

R M

od

e

BER Mode

FILE TRANSFERMode

AUDIO Mode

Figure 4.1. Overview of transmitter application layer interface to the PHY.

4.1 PS/2 Keyboard application layerA scan code corresponding to the key pressed in a keyboard which is connected intransmitter is sent over the human body channel to receiver. The pressed alphabetis displayed in a LCD in receiver. A PS/2 keyboard transmits make/break codeinto a serial data stream by a clock and data serial lines. For each pressed key,PS2 generates a make code consisting of a start bit, a 8-bit encoded code, an oddparity bit and a stop bit; it is followed by a break code consisting of a 8 bit specialcode (FO’h) when the key is released. The transmitter reads the make and breakscan codes of the key pressed through the PS/2 interface, and decodes to a 8-bitpacked to PHY layer with SOP and EOP control signals.

Where as at receiver, the scan code that is extracted from the received packetis converted to an ASCII value. It is forwarded to a LCD controller to display thealpha-numeric character in LCD.

4.2 Audio streaming application layer 27

Display

Receiver

Physical

Layer

Application

Keyboard

Application

Layer

Audio

Layer

File Transfer

Application

Layer

Demux

Length ( 16−bit )

Payload Data

Ready

Read Memory

Address

RX IN

CRC Error

Payload Data

Ready

Read Memory

Address

Payload Data

Ready

Read Memory

Address

Payload Data

Ready

Read Memory

Address

BER Calculator

0.000e−00 7 − Segment Display

StreamBitRecovered

ClockSOP

SpeakerTo

Display

LCD

To

To

VGA

Figure 4.2. Overview of receiver application layer interface to the PHY.

4.2 Audio streaming application layer

This application layer uses the audio codec available in DE2-70 Altera developmentboard. The codec is configured to output digital samples of the audio line input,ADC in the codec is operated at 48 kHz sample mode with the samples quantizedto 8-bit each for left and right audio channels. The digital output samples fromleft and right audio channels are encoded in a single serial data line. These bit-samples are collected in bytes and buffered for 32, 64, 256 or 1024 bytes based onselected packet size. when buffer memory is once filled for packet size, it startstransmitting to PHY layer in 8-bit data lines along with SOP and EOP controlsignals. The Packet size of a buffer is selected based on the BER of the channel.

As samples flows in continuously from the codec two buffer memories are usedto store samples, one to store the present incoming samples while the other memoryis streaming out stored samples to PHY layer for transmission. An acknowledg-ment signal is sent by PHY layer to confirm a successful transmission of packet inorder to request for a new packet from the application layer.

Audio application layer at the receiver configures the codec to reproduce theanalog stereo audio line output from received digital samples . Depending on theselected size of the received packet, it takes one to several packets to fill a buffermemory of 1024 bytes before it can be serially transferred to the codec. Similar totransmitter two buffers are used in receiver for simultaneous buffering from PHYand transferring to codec.


4.3 File transfer application layer

File transfer application layer transfers a stored file over the human body channelto receiver. Since a large file cannot be transferred in one large packet, the file isdivided into many small packets and then transferred packet by packet to receiver.The length of each packet is set to 1026 bytes with 2-byte for the packet numberand 1024 bytes for user data. The packet number in each transferred packet isto help in assembling the packets to reconstruct the file in receiver. The file thatto be transferred is stored in a local memory. Memory locations are addressedconsecutively to access data for forming packets. There is a counter for countingthe total number of bytes that are sent from the file and one more counter to count1024 bytes data in each packet. After each packet is transferred to PHY layer, theApplication layer waits for an acknowledgment to send the next packet of 1024bytes data.

Receiver application layer has a memory to store the packets received, packetsare organized according to its packet number to reconstruct the file. The packetsare stored in memory locations that are accessed by the address bus formed bypacket number as MSB and byte number as LSB of address bus.

This application layer was tested by sending an image file to a receiver node.An image that is stored in a memory is transferred in a number of packets to thereceiver. The received image is displayed in a VGA screen that is connected toreceiver. Since, each packet maps to a group of pixels in the image the systemperformance is visually seen on the screen. A lost or corrupted packet is easilyseen visually.

4.4 Bit Error Rate tester

In order to test the performance of the communication systems, a BER testeris built in the system. The BER is one such parameter which can measure theperformance of the system in numbers. BER is defined as the total number ofreceived data bits that are received incorrectly to the total number of bits trans-mitted. The BER is affected by the quality of the communicating channel due tothe attenuation of the signal in the channel, presence of interference, noise anddistortion; also affected by clock synchronization problems that may happen inthe receiver, the quality of modulation schemes. Therefore, BER tester can beused as an evaluation tool or even as an online adaptation tool to have a betterclock synchronization for improved performance (see 3.2.2).

BER is calculated by transmitting a pseudo-random stress pattern of 1’s and0’s to the receiver. These generated bit patterns go through the same processas the regular user data like modulation, packing preamble, header and trailerfor helping in the packet detection in the receiver. Whereas, in the receiver thesame stress pattern is generated to compare it with the received data to count thenumber of incorrectly received error bits, finding the BER of the system. Usually,the number of bits used to find the BER will be in hundreds thousands of bits.

4.4 Bit Error Rate tester 29

4.4.1 Test pattern generatorA simple and efficient test pattern generator is implemented using a Linear Feed-back Shift Register (LFSR), counters and comparators. The LFSR is a seriallyconnected flipflops (shift register) with the first flipflop’s input connecting to theoutput of linear function of the previous shift register content. A primitive polyno-mial is selected based on the required periodicity of the stress pattern. The prim-itive polynomial determines the bits of the shift register that should be tappedto implement the linear feedback function for the LFSR. The rightmost flipflop ofthe shift register is the output node that gives the deterministic random patternoutput.

The Test pattern generator implements the 19-bit LFSR (Figure 4.3) for theprimitive polynomial of degree 19, x19 + x18 + x17 + x14 + 1 , which can generate apseudo-random bits of period 219 −1 bits before repeating the same pattern again.The initial seed of the shift register is initialized to 0F0F0hex.

Output

X14 X17 X18 X191

Figure 4.3. A 19-bit LFSR used in pseudo-random test pattern generation.

The test pattern generation is started by switching on the testing (BER) mode,which starts sending logical packets of random binary bits to the PHY for thetransmission. After each packet is sent the test generator awaits acknowledgmentfrom the PHY before sending the next packet. Each packet consists of 65536pseudorandom binary bits (8192 bytes).

4.4.2 Bit Error Rate calculatorThe BER calculator is implemented in the receiver and interfaced to the PHY.The BER calculator is enabled for the length field in the received packet to be thevalue of a BER packet size (see Table 4.1). The BER calculator also implementsa LFSR for the same primitive polynomial that is used in the test generator forbinary bit comparison. The PHY sends a SOP signal to initialize the LFSR seed


(8−bit)

Data

Reset

Enable

BER mode Ready_inverted

==8191<8192

Rising

EdgeLFSR

Counter SOP

EOP

==0

SIPO

Figure 4.4. Test pattern generator that transmits a pseudo-random data to the testsystem.

value; the calculator has started counting the number of received bits that donot match with the locally generated LFSR output. Computing BER for everysingle packet received is too fast to display and gives unrealistic output. Therefore,the BER is calculated on every 64 packets, that is 4,194,304 bits (65536 bits perpacket), received. Since, the total number of bits compared for BER calculation is222 a power of ‘2’ the decimal point (dp) in the binary representation of the totalnumber of error bits is left shifted (binary division) by ‘22’ bits to get the BERvalue. The PHY layer in the receiver derives SOP, recovered baseband clock anddecoded data for BER calculator to calculate the BER of the system.

4.4 Bit Error Rate tester 31

+

Counter

Payload

PacketCounter 7−segment

BCD to

BCD

Binary to

Register23−bit

Error BitsCounter

<65536

Reset

En

able

Res

et

Enab

leEn

able

En

able

Bit Stream

SOP

==65535

!=

Res

et

==63

Cle

ar

+LFSR Leftshift dp

’22’ bits

Figure 4.5. BER error detector and calculator.

Chapter 5

Results and discussion

In this chapter the measurement results are given for the performance of digitalbaseband for the human body channel. In the test setup, transmitter and receiverare placed at 120 cm apart and they are electrostatically coupled to the humanbody channel through electrodes. The results from the measurements should beuseful as a benchmark for any future evaluation of an improvised system.

All these measurement and estimated metrics were obtained from the exper-iments carried out on Altera’s DE2-70 FPGA development board. This boardoperates at a 50 MHz crystal clock with a 90-nm process Cyclone II FPGA de-signed on 1.2 V SRAM process. This board also has a PLL, which is used togenerate clock for digital baseband for different data rates. The PLL uses a ra-tional divider to generate clock at various frequencies, it can generate a clock aslow as 9 MHz. For frequencies below 9 MHz, sequential circuit frequency divideris used to derive lower frequencies, which had poor performance for data rates 6Mbps and below due to the presence of clock jitter. There were adjustments inthe sample point of reciever decoder to improve the BER performance.

The BER Tester, Section 4.4, that is implemented in the digital baseband isused to measure he variation of many variables that exist in the system, suchas area of the electrodes, output power of transmitter, oversampling clock ratiofor clock phase synchronization in receiver, data rate, transmission frequency, etc.Power consumption is estimated using PowerPlay power analysis tool in QuartusII EDA. The tool uses toggle rate of nodes found in design to estimate power con-sumption. The design is gate synthesized with a process technology library, whichtranslates the design in terms of primitive logical gates from the provided tech-nology library. This gate model is simulated to collect signal activities (toggling)of all nodes in the design. A 20 pF capacitor is taken for transmitter output toestimate power consumption.

5.1 Datarate vs. Bit Error RateThe human body communication system has low BER because of strong electro-static coupling through larger electrode area and low attenuation provided by the

33

34 Results and discussion

human channel. BER is measured for various data rate between 2.5 Mbps to 12.5Mbps to understand quality of the channel. The test setup uses electrodes of 60cm2 in dimension, and a clock oversampling ratio of 20 for all data rates. BERwas measured for data rates, 2.5, 6, 10 and 12.5 Mbps (Figure 5.1). BER is lowfor slower data rates and seems to increase for faster data rates because of sig-nal interference in that radio spectrum from applications like RFID and amateurradio.

1 2.5 6 10 12.50

2.0E−7

4.0E−7

6.0E−7

1.0E−6

Datarate ( Mbps )

BE

R

Datarate vs. BER

Figure 5.1. Datarate vs. BER for clock oversampling ratio of 20.

5.2 Clock oversampling ratio vs. BERThe clock oversampling ratio determines the performance of Manchester decoderfor optimal data reception in receiver. Thus by reducing clock oversampling ra-tio, the clock phase recovery leads to more decoding error by setting less precisesampling point of the decoder. The effect is even more for faster data rate as bitperiod is small. This effect is triggered by reducing the strength of electrostaticcoupling of transmitter by reducing electrode size from 60 cm2 to 8 cm2. BERis the metric used to evaluate the performance of change in clock oversamplingratio. For strong electrostatic coupling, low clock oversampling ratio is enough tohave a low BER as strong signal is not affected by the channel. Where as in weakelectrostatic coupling conditions, there is a need of higher clock sampling ratio tocompensate pulse duty cycle changes incurred in channel and AFE from signal

5.3 Datarate vs. Power consumption of transmitter 35

attenuation and slow phase recovery. The Figure 5.2 illustrates the presence oftrade-off between the area of electrode, clock oversampling ratio and data rate.

4 6 8 10 12 1410

−7

10−6

10−5

10−4

10−3

10−2

Datarate ( Mbps )

BE

R

Datarate vs. Electrode area vs. Oversampling ratio vs. BER

Oversampling=10, Area of Electrode=8 cm2Oversampling=20, Area of Electrode=8 cm2Oversampling=10, Area of Electrode=60 cm2Oversampling=20, Area of Electrode=60 cm2

Figure 5.2. Datarate vs. Electrode area vs. Clock oversampling ratio vs. BER.

5.3 Datarate vs. Power consumption of transmit-ter

Table 5.1. Transmitter PHY layer: Power consumption by block type

Data rate I/0 (mw) UserMemory(mw)

CombinationalCircuit (mw)

SequentialCircuit (mw)

2.5 Mbps 0.36 0.28 0.03 0.036 Mbps 0.81 0.69 0.06 0.0710 Mbps 1.37 1.14 0.10 0.1212 Mbps 1.68 1.36 0.12 0.14

The gate model is simulated by a test bench to calculate signal activity (tog-gling) for all nodes in the design. The test bench will generate the test inputsignals, SOP, EOP control signals and the data for the PHY. The test bench hasa counter whose output is given as input data to the PHY. The test bench imple-ments a data packet of 1024 bytes. It waits for an acknowledgment from the PHYbefore it can send another data packet.

36 Results and discussion

0 2 4 6 8 10 12 130

0.5

1

1.5

2

2.5

3

3.5

Datarate ( Mbps )

Dyn

amic

Pow

er (

mw

)Transmitter PHY layer : Datarate vs. Dynamic Power Consumption

Figure 5.3. Datarate vs. Dynamic power consumption for transmitter PHY.

A dynamic power consumption is directly proportional to the transmission rate(Figure 5.3), more than half of this consumption is from the 20 pF capacitor con-sidered at the transmitter output. A frequency voltage scaling can be implementedin the PHY to reduce the data rate based on the application layer’s requirement.

Table 5.2. Receiver PHY layer: Power consumption by block type

Data rate I/0 (mw) UserMemory(mw)

CombinationalCircuit (mw)

SequentialCircuit (mw)

2.5 Mbps 0.16 0.04 0.22 0.266 Mbps 0.39 0.10 0.52 0.6210 Mbps 0.64 0.17 0.86 1.0312 Mbps 0.75 0.21 1.03 1.23

5.4 Datarate vs. Power consumption of receiver 37

5.4 Datarate vs. Power consumption of receiver

2 4 6 8 10 120

0.5

1

1.5

2

2.5

3

3.5

Datarate ( Mbps )

Dyn

amic

Pow

er (

mw

)

Receiver PHY layer : Datarate vs. Dynamic Power Consumption

Figure 5.4. Datarate vs. Dynamic power consumption for receiver PHY.

The test bench is setup to directly connect the simulated output from thetransmitter PHY layer to the receiver PHY layer for providing input to calculatepower consumption of the receiver PHY layer. Its dynamic power consumptionis directly proportional to the transmission rate because a higher clock samplingfrequency is used for faster transmission rate(Figure 5.4). The power consumptionis divided between I/O, data memory, combination and sequential circuit.

Chapter 6

Future work and conclusion

6.1 Future workThis section recommends a number of future works that will improve the stabilityand performance of the system.

• The PHY has been built on Simulink using Altera DSP builder tool boxfor fast prototyping. One can rebuild the system in VHDL, which enablesporting the design from FPGA to ASIC library. This may also be a step toimprovement in the resource usage and improvement in performance as well.

• Manchester encoder was chosen as the baseband modulation scheme for hard-ware simplicity and easier clock synchronization. One may test the PHY withdifferent pulse modulation/line encoder schemes to find a best alternative interms of symbol rate and power consumption.

• Although duplex transmission system seems tricky in single channel wide-band signaling, half duplex transmission can be implemented by designingMAC layer. One can think of Carrier sense multiple access with collisiondetection (CSMA/CD) access method as in Ethernet standards IEEE 802.3.

• Forward error correction algorithm can replace CRC for applications, wheredata integrity is important; or Automatic repeat request (ARQ) error controltechnique can request the sender for retransmission, if the CRC error checkis failed.

• HBC system is suitable for BAN network. There are many kinds of com-municating devices connected to the BAN network and each one of themhas different needs. Depending on the nature of the data to transmit, thetransmission data rate should be made variable to conserve power.

• An algorithm can be implemented for Online tuning of AFE’s gain andbandwidth based on the calculated BER.

39

40 Future work and conclusion

• The clock synchronization is active only during preamble period of a packetand the next synchronization will be during the next incoming packet. Ex-istence of clock drifts between the transmitter and the receiver clock willreduce the optimal packet length. So there is a need of protocol in the re-ceiver PHY to transmit service message to the transmitter PHY node torequest for a step down in length of the payload.

The final outcome of this thesis is a prototype of the working principle demon-strating proof of concept. In order for making a product, some of the aforemen-tioned future work needs to be completed for more stability to reach the market.

6.2 ConclusionIn this thesis work, digital baseband for HBC system is designed and implemented.The baseband is designed to work along with the AFE circuit to send data throughthe human body channel. Manchester encoder was selected for the baseband mod-ulation scheme for hardware simplicity and easier clock recovery. CRC field isadded in the packet trailer for FEC in the receiver. There are four applicationlayers developed in this thesis for different application use and bandwidth require-ments. PS/2 keyboard application layer is developed for transferring small packetscontaining encoded key strokes. This is developed as an example of applicationswhich requires small bandwidth. Where as the audio application layer is developedfor streaming application that has wide bandwidth requirement.

The file transfer application layer is developed for transferring large file, itdivides the file by multiple small sized packets. The file transfer was tested bytransferring images. An image of 307200 pixels and each pixel is encoded in 16bits has a total file size of 600 kB data to transfer. This image file is divided by anumber of packets with each packet corresponds to a block of pixels in the image.The received image is displayed in a VGA screen. Since, each packet correspondsto a block of pixels in the VGA screen, a lost or corrupted packet is visually seenin the displayed image.

A BER tester is implemented in hardware to measure the performance of thecommunication system. The effects of different baseband parameters such as datarate and clock oversampling ratio were measured with BER tester. The powerconsumption was estimated for the transmitter and receiver PHY layers from thesimulation results. This thesis is concluded with the successful hardware imple-mentation of all the designs in a FPGA and tested on a human body channel withAFE.

Connected Me prototype was demonstrated on a number of major technicalexhibitions under the banner of Ericsson including European Conference on CircuitTheory and Design (ECCTD 2011, Linkoping), Consumer Electronics Show (CES2012, Las Vegas), Mobile World Congress (MWC 2012, Barcelona) and at CTIA2013 in Las Vegas.

6.2 Conclusion 41

Figure 6.1. Connected Me development team at the Ericsson booth at ECCTD 2011.

Figure 6.2. Hans Vestberg, CEO of Ericsson demonstrating Connected Me at CES2012.

Bibliography

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[2] A. Fort, C. Desset, P. Wambacq, and L.V. Biesen. Indoor body-area channelmodel for narrowband communications. Microwaves, Antennas Propagation,IET, 1(6):1197–1203, 2007.

[3] Jin Huang, Lei Wang, Dahui Zhang, and Yuanting Zhang. A low-frequencylow-noise transceiver for human body channel communication. In BiomedicalCircuits and Systems Conference, 2009. BioCAS 2009. IEEE, pages 37–40,2009.

[4] T.W. Kang, J.H. Hwang, C.H. Hyoung, I. G. Lim, H.I. Park, and S.W. Kang.Performance evaluation of human body communication system for ieee 802.15on the effect of human body channel. In Consumer Electronics (ISCE), 2011IEEE 15th International Symposium on, pages 232–235, 2011.

[5] K.S. Kwak, S Ullah, and N. Ullah. An Overview of IEEE 802.15.6 Standard.Applied Sciences in Biomedical and Communication Technologies (ISABEL),2010 3rd International Symposium on, November 2010.

[6] W.W. Peterson and D.T. Brown. Cyclic codes for error detection. Proceedingsof the IRE, 1961.

[7] J.A. Ruiz and S. Shimamoto. Experimental evaluation of body channel re-sponse and digital modulation schemes for intra-body communications. IEEEInternational Conference on Communications, 2006.

[8] J.A. Ruiz, J. Xu, and S. Shimamoto. Propagation characteristics of intra-bodycommunications for body area networks. IEEE Consumer Communicationsand Networking Conference, 2006.

[9] T. C W Schenk, N.S. Mazloum, L. Tan, and P. Rutten. Experimental char-acterization of the body-coupled communications channel. In Wireless Com-munication Systems. 2008. ISWCS ’08. IEEE International Symposium on,pages 234–239, 2008.

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[11] Seong-Jun Song, Namjun Cho, Sunyoung Kim, J. Yoo, and Hoi-Jun Yoo.A 2mb/s wideband pulse transceiver with direct-coupled interface for humanbody communications. In Solid-State Circuits Conference, 2006. ISSCC 2006.Digest of Technical Papers. IEEE International, pages 2278–2287, 2006.

[12] T.G. Zimmerman. Personal area networks: Near-field intrabody communica-tion. IBM Systems Journal, 35:609–617, 1996.

Appendix A

Transmitter Baseband(VHDL)

l ibrary IEEE ;use IEEE . std_logic_1164 . a l l ;use IEEE .NUMERIC_STD. a l l ;−− This f i l e d e c l a r e s e n t i t y of t r a n s m i t t e r and component i n s t a n t i a t i o n s−− of implementation of a p p l i c a t i o n l a y e r s and Physica l (PHY) l a y e r of the−− t r a n s m i t t e r . LCD c o n t r o l l e r and ASCII converter from PS2 keyboard−− scan codes components are i n s t a n t i a t e d . A c o n f i g u r a b l e−− Phase−locked loop (PLL) component generated from Altera Quartus I I−− l i b r a r y i s conf igured f o r generat ing a 12 MHz c l o c k . An XOR gate i s−− connected b e f o r e the t r a n s m i t t e r output with data and c l o c k as the−− inputs f o r Manchester encoded data . The code i s s y n t h e s i z a b l e f o r−− Altera DE2−70 Development board .

entity TX_top i sport (

−− I /O pins , Bit−error rate pat tern l e n g t h s e l e c t o rber_size_2048 : IN s td_log i c ;ber_size_4096 : IN s td_log i c ;ber_size_8192 : IN s td_log i c ;−− I /O pins to communicate with ROM which has image data

s toreddata_f lash : IN s td_log ic_vector (15 DOWNTO 0) ;f l a sh_addres s : OUT s td_log ic_vector ( 21 DOWNTO 0 ) ;byte_low_flash : OUT s td_log i c ;

−−highchip_en_flash : OUT s td_log i c ;

−−lowch ip_reset : OUT s td_log i c ;out_en_flash : OUT s td_log i c ;

−−here lowwr_en_flash : OUT s td_log i c ;

−−here high

−− I /O pins f o r Image t r a s n f e r modeimage_mode : IN s td_log i c ;−−j u s t l i k e audio and ber

modeimage_change : IN s td_log i c ;−− a l o c a l counter w i l l t rack

which image to send

Length_256 : IN s td_log i c ;Length_64 : IN s td_log i c ;Length_32 : IN s td_log i c ;

45

46 Transmitter Baseband (VHDL)

−− I /O pins f o r LCD package in the boardpower_lcd : out s td_log i c ;rs_lcd : out s td_log i c ;rd_wrlow_lcd : out s td_log i c ;enable_lcd : out s td_log i c ;data_lcd : inout s td_log ic_vector (7 downto 0) :=(

others=>’Z ’ ) ;Clock : in s td_log i c ;a c l r : in s td_log i c ;

−− I /O pins from PS2 keyboard c o n t r o l l e rkey_clk : in s td_log i c ;key_data : in s td_log i c ;ber_start : in s td_log i c ;−− sendaudio_mode : IN s td_log i c ; −−mode s e l e c t i o nber_mode : IN s td_log i c ; −−mode s e l e c t i o n−− I /O pins from Audio CODECADCDAT : IN s td_log i c ;ADCLRC : IN s td_log i c ;BLCK : IN s td_log i c ;XTI : OUT s td_log i c ;s c l : OUT s td_log i c ;sda : INOUT s td_log i c ;−− Output from PLL used f o r c l o c k d i v i s i o n , s e t to ’1 ’

when phase lockedl ocked : OUT s td_log i c ;

−− Status s i g n a l , Packet l e n g t hl ength : OUT s td_log ic_vector (15 downto 0) ;

−− Manchester encoder ouput f o r data and i n v e r t e d datatx_out : OUT s td_log i c ;tx_outinv : OUT s td_log i c

) ;end TX_top ;

Architecture a1 of TX_top i s

−− Component i n s t a n t i a t i o n of keyboard a p p l i c a t i o n l a y e rCOMPONENT kb_app l i ca t i on layer i s

port (Clock : in s td_log i c ;a c l r : in s td_log i c ;data : out s td_log ic_vector (8−1 downto 0) ;eop : out s td_log i c ;key_clk : in s td_log i c ;key_data : in s td_log i c ;sop : out s td_log i c

) ;end COMPONENT;

−− Component i n s t a n t i a t i o n of Bit−error rate a p p l i c a t i o n l a y e rCOMPONENT be r_app l i c a t i on l aye r i s

port (Clock : in s td_log i c ;a c l r : in s td_log i c ;ber_s ize : in s td_log ic_vector (16−1 downto 0) ;ber_start : in s td_log i c ;data : out s td_log ic_vector (8−1 downto 0) ;eop : out s td_log i c ;sop : out s td_log i c

) ;end COMPONENT;

−− Component i n s t a n t i a t i o n of audio t r a n s f e r a p p l i c a t i o n l a y e rCOMPONENT audio_appl_tx i s

PORT(audio_mode : IN s td_log i c ;Length_256 : IN s td_log i c ;Length_64 : IN s td_log i c ;Length_32 : IN s td_log i c ;

47

tx_clk : IN s td_log i c ;−−2.5mhzdata_out : OUT s td_log ic_vector (7 downto 0) ;ack_physical : IN s td_log i c ;sop_out : OUT s td_log i c ;eop_out : OUT s td_log i c ;ADCDAT : IN s td_log i c ;ADCLRC : IN s td_log i c ;BLCK : IN s td_log i c ;r e s e tn : IN s td_log i c ;sys_clk : IN s td_log i c ;−−50 mhz f o r audio i n t e r f a c eXTI : OUT s td_log i c ;s c l : OUT s td_log i c ;sda : INOUT s td_log i c

) ;

−− Declarat ions

END COMPONENT;

−− Component i n s t a n t i a t i o n of LCD c o n t r o l l e rcomponent lcd_control ler_TX i s

port ( c l k : in s td_log i c ;power : out s td_log i c := ’1 ’ ;a c l r : in s td_log i c ;r s : out s td_log i c ;rd_wrlow : out s td_log i c ;enable : out s td_log i c ;data : inout s td_log ic_vector (7 downto 0) :=(others=>’Z ’ ) ;data_rx : in s td_log ic_vector (7 downto 0) ;ready : in s td_log i c

) ;END component ;

−− Component i n s t a n t i a t i o n of PS2 scan code to ASCII convertercomponent kb_conversion i s

port ( c l k : in s td_log i c ;rd : in s td_log i c ;scan_code : in s td_log ic_vector (7 downto 0) ;a s c i : out s td_log ic_vector (7 downto 0) ;output_en : out s td_log i c

) ;END component ;

−− Component i n s t a n t i a t i o n of image t r a n s f e r a p p l i c a t i o n l a y e rcomponent image_txPORT(−−f l a s h i n t e r f a c e

data_f lash : IN s td_log ic_vector (15 DOWNTO 0) ;f l a sh_addres s : OUT s td_log ic_vector ( 21 DOWNTO 0 ) ;byte_low_flash : OUT s td_log i c ; −−highchip_en_flash : OUT s td_log i c ; −−lowch ip_reset : OUT s td_log i c ;out_en_flash : OUT s td_log i c ; −−here

lowwr_en_flash : OUT s td_log i c ; −−here

high

−− Board i n t e r f a c eimage_mode : IN s td_log i c ;−−j u s t l i k e audio and ber modeimage_change : IN s td_log i c ;−− a l o c a l counter w i l l t rack which

image to send−− p h y s i c a l l a y e r i n t e r f a c e

tx_clk : IN s td_log i c ;−−2.5mhzdata_out : OUT s td_log ic_vector (7 downto 0) ;ack_physical : IN s td_log i c ;sop_out : OUT s td_log i c ;


eop_out : OUT s td_log i c ;r e s e tn : IN s td_log i c

) ;END component ;

−− Component i n s t a n t i a t i o n of PLLcomponent pll_12MHz

PORT(

a r e s e t : IN STD_LOGIC := ’ 0 ’ ;i n c l k 0 : IN STD_LOGIC := ’ 0 ’ ;c0 : OUT STD_LOGIC ;locked : OUT STD_LOGIC

) ;end component ;

−− Component i n s t a n t i a t i o n of TX PHY l a y e rCOMPONENT tx_phys i ca l l aye r i s

port (Clock : in s td_log i c ;a c l r : in s td_log i c ;l ength : out s td_log ic_vector (16−1 downto 0) ;ready : out s td_log i c ;test_out : out s td_log ic_vector (8−1 downto 0) ;tx_out : out s td_log i c ;tx_physical layer_tx_clk_pin : in s td_log i c ;tx_physical layer_tx_data : in s td_log ic_vector (8−1 downto

0) ;tx_physical layer_tx_eop : in s td_log i c ;tx_physical layer_tx_sop : in s td_log i c

) ;end COMPONENT;

signal ber_s ize : s td_log ic_vector (16−1 downto 0) ;

−−t e s t i n g c l o c k generat ion

signal clock_12 : s td_log i c ;

signal ack_physical : s td_log i c ;signal data_appl : s td_log ic_vector (7 downto 0) ;signal keyboard_data : s td_log ic_vector (7 downto 0) ;signal sop : s td_log i c ;signal eop : s td_log i c ;signal asic_out : s td_log ic_vector (7 downto 0) ;

signal key_sop : s td_log i c ;signal key_eop : s td_log i c ;signal key_data_appl : s td_log ic_vector (7 downto 0) ;

signal ber_sop : s td_log i c ;signal ber_eop : s td_log i c ;signal ber_data_appl : s td_log ic_vector (7 downto 0) ;

signal audio_sop : s td_log i c ;signal audio_eop : s td_log i c ;signal audio_data_appl : s td_log ic_vector (7 downto 0) ;

signal image_sop : s td_log i c ;signal image_eop : s td_log i c ;signal image_data_appl : s td_log ic_vector (7 downto 0) ;

−− f o r tx_clk1

signal lcd_ready : s td_log i c ;signal output_en : s td_log i c ;

signal tx_out_int : s td_log i c ;

49

signal ber_start_int : s td_log i c ;

begin

ber_size<= std_log ic_vector ( to_unsigned (4096 ,16) ) when ber_size_4096= ’1 ’else

s td_log ic_vector ( to_unsigned (2048 ,16) ) when ber_size_2048= ’1 ’else

s td_log ic_vector ( to_unsigned (8192 ,16) ) when ber_size_8192= ’1 ’else

s td_log ic_vector ( to_unsigned (16384 ,16) ) ;

−− Manchester outputtx_out<=tx_out_int ;tx_outinv<= not ( tx_out_int ) ;

l 1 : kb_app l i ca t i on layerport map (

Clock => clock_12 ,a c l r =>ac l r ,data => key_data_appl ,eop => key_eop ,key_clk => key_clk ,key_data => key_data ,sop =>key_sop

) ;

l 2 : b e r_app l i c a t i on l aye rport map (

Clock => clock_12 ,a c l r =>ac l r ,ber_s ize=>ber_size ,ber_start => ber_start_int ,data => ber_data_appl ,eop => ber_eop ,sop => ber_sop

) ;

asc i i_conv : kb_conversionport map

( c l k => clock_12 ,rd => lcd_ready ,scan_code => keyboard_data ,a s c i => asic_out ,output_en => output_en

) ;

l cd : lcd_control ler_TX

port map ( c l k => clock_12 ,power=> power_lcd ,a c l r => ac l r ,r s => rs_lcd ,rd_wrlow =>rd_wrlow_lcd ,enable =>enable_lcd ,data => data_lcd ,data_rx => asic_out ,ready=> output_en

) ;

l 5 : audio_appl_txPORT MAP(

audio_mode=>audio_mode ,Length_256=> Length_256 ,Length_64=>Length_64 ,Length_32=>Length_32 ,


tx_clk => clock_12 ,data_out => audio_data_appl ,ack_physical => ack_physical ,sop_out =>audio_sop ,eop_out=> audio_eop ,ADCDAT => ADCDAT,ADCLRC =>ADCLRC,BLCK =>BLCK,r e s e tn =>ac l r ,sys_clk => Clock ,XTI => XTI ,s c l => sc l ,sda => sda

) ;

l 7 : image_txPORT MAP(−−f l a s h i n t e r f a c e

data_f lash=>data_flash ,f l a sh_addres s=>f lash_address ,byte_low_flash=>byte_low_flash ,chip_en_flash=>chip_en_flash ,ch ip_reset=>chip_reset ,out_en_flash=>out_en_flash ,wr_en_flash=>wr_en_flash ,

−− Board i n t e r f a c eimage_mode=>image_mode ,image_change=>image_change ,

−− p h y s i c a l l a y e r i n t e r f a c etx_clk=>clock_12 ,data_out=>image_data_appl ,ack_physical=>ack_physical ,sop_out=>image_sop ,eop_out=>image_eop ,r e s e tn =>ac l r

) ;

l 3 : pll_12MHzPORT MAP(

a r e s e t=> not ( a c l r ) ,i n c l k 0 =>Clock ,c0 =>clock_12 ,locked => locked

) ;

−− Strobe s i g n a l f o r i n i t i a t i n g BER t e s t pat tern generatorber_start_int<=ber_start and not ( ack_physical ) when ber_mode = ’1 ’ and

audio_mode = ’0 ’ else’ 0 ’ ;

−− s t a r t of packet ( sop ) marks f i r s t byte in each packet t h a t are sent toPHY l a y e r

sop<= ber_sop when ber_mode = ’1 ’ and audio_mode = ’0 ’ and image_mode= ’0 ’else

audio_sop when audio_mode = ’1 ’ and ber_mode = ’0 ’ and image_mode= ’0 ’ else

image_sop when audio_mode = ’0 ’ and ber_mode = ’0 ’ and image_mode= ’1 ’ else

key_sop ;

−− end of packet ( eop ) marks l a s t byte in each packet t h a t are sent to PHYl a y e r

51

eop<= ber_eop when ber_mode = ’1 ’ and audio_mode = ’0 ’ and image_mode= ’0 ’else

audio_eop when audio_mode = ’1 ’ and ber_mode = ’0 ’ and image_mode= ’0 ’ else

image_eop when audio_mode = ’0 ’ and ber_mode = ’0 ’ and image_mode= ’1 ’ else

key_eop ;

−− 8− b i t data MUXdata_appl<= ber_data_appl when ber_mode = ’1 ’ and audio_mode = ’0 ’ and

image_mode= ’0 ’ elseaudio_data_appl when audio_mode = ’1 ’ and ber_mode = ’0 ’ and

image_mode= ’0 ’ elseimage_data_appl when audio_mode = ’0 ’ and ber_mode = ’0 ’ and

image_mode= ’1 ’ elsekey_data_appl ;

lcd_ready<= ack_physical when ber_mode = ’0 ’ and audio_mode = ’0 ’ andimage_mode= ’0 ’ else

’ 0 ’ ;

l 6 : tx_phys i ca l l aye rport map (

Clock =>clock_12 ,a c l r =>ac l r ,l ength =>length ,ready => ack_physical ,test_out => keyboard_data ,tx_out =>tx_out_int ,tx_physical layer_tx_clk_pin => clock_12 ,tx_physical layer_tx_data => data_appl ,tx_physical layer_tx_eop =>eop ,tx_physical layer_tx_sop => sop

) ;

end a1 ;

Appendix B

Receiver Baseband (VHDL)

LIBRARY i e e e ;USE i e e e . std_logic_1164 . a l l ;USE i e e e . s td_log i c_ar i th . a l l ;USE i e e e . std_logic_unsigned . a l l ;USE i e e e . numeric_std .ALL;−− This f i l e d e c l a r e s the e n t i t y of r e c e i v e r and component i n s t a n t i a t i o n s−− of implementation of a p p l i c a t i o n l a y e r s and Physica l (PHY) l a y e r of−− the r e c e i v e r . LCD c o n t r o l l e r and ASCII converter from PS2 keyboard−− scan codes components are i n s t a n t i a t e d . A c o n f i g u r a b l e−− Phase−locked loop (PLL) component generated from Altera Quartus I I−− l i b r a r y i s conf igured f o r generat ing a 120 MHz c l o c k . The SSRAM−− memory c o n t r o l l e r ,VGA c o n t r o l l e r and Audio codec implementations−− are component i n s t a n t i a t e d . The code i s s y n t h e s i z a b l e f o r Altera−− DE2−70 Development board .

entity RX_top i sport (

−− packet_no : OUT std_logic_vector ( 9 DOWNTO 0 ) ;address_SSRAM : OUT s td_log ic_vector ( 18 DOWNTO 0 ) ;

−− SSRAM_zz : OUT s t d _ l o g i c;−− s e t to low to d i s a b l epower downout_en : OUT s td_log i c ; −−a c t i v e l o wSSRAM_clk : OUT s td_log i c ; −−synchronous c l k max of 250 MHZglobal_wlow : OUT s td_log i c ;−− a c t i v e low s e t to high f o r byte

operationSSRAM_ads_c : OUT s td_log i c ; −− Address Status C o n t r o l l e r LOW

b u r s t s t a r t . . . . s i n g l e wri te /readSSRAM_ads_p : OUT s td_log i c ;−−Address Status Processor HIGH

b u r s t s t a r t . . . . s i n g l e wri te /readSSRAM_adv : OUT s td_log i c ;chip_en_low : OUT s td_log i c ; −−Synchronous Chip S e l e c tchip_en2_low : OUT s td_log i c ;chip_en2 : OUT s td_log i c ;data_ssram : INOUT s td_log ic_vector ( 15 DOWNTO 0 ) ;bytew_low : OUT s td_log i c ;vga_clk : OUT s td_log i c ;vga_b : OUT s td_log ic_vector (9 DOWNTO 0) ;vga_g : OUT s td_log ic_vector (9 DOWNTO 0) ;vga_r : OUT s td_log ic_vector (9 DOWNTO 0) ;vga_hsync : OUT s td_log i c ;vga_sync : OUT s td_log i c ;vga_vsync : OUT s td_log i c ;vga_blank : OUT s td_log i c ;check_point1 : OUT s td_log i c ;Clock : in s td_log i c ;a c l r : in s td_log i c ;

52

53

c rc : out s td_log i c ;rx_in : in s td_log i c ;LSB : out s td_log ic_vector (7−1 downto 0) ;LSB1 : out s td_log ic_vector (7−1 downto 0) ;LSB2 : out s td_log ic_vector (7−1 downto 0) ;LSB3 : out s td_log ic_vector (7−1 downto 0) ;LSB4 : out s td_log ic_vector (18−1 downto 0) ;dp : out s td_log i c ;e_lsb : out s td_log ic_vector (7−1 downto 0) ;e_minus : out s td_log ic_vector (7−1 downto 0) ;e_msb : out s td_log ic_vector (7−1 downto 0) ;exp : out s td_log ic_vector (7−1 downto 0) ;

−−CODEC i n t e r f a c eDACDAT : OUT s td_log i c ;DACLRC : IN s td_log i c ;BLCK : IN s td_log i c ;XTI : OUT s td_log i c ;s c l : OUT s td_log i c ;sda : INOUT s td_log i c ;power_lcd : out s td_log i c ;rs_lcd : out s td_log i c ;rd_wrlow_lcd : out s td_log i c ;enable_lcd : out s td_log i c ;data_lcd : inout s td_log ic_vector (7 downto 0) :=(others=>’Z ’ )

) ;end RX_top ;

Architecture a1 of RX_top i s

component image_rxPORT(

packet_no : OUT s td_log ic_vector ( 9 DOWNTO 0 ) ;r e s e tn : IN s td_log i c ;rx_clk : IN s td_log i c ;−−50mhzdata_in : IN s td_log ic_vector (7 downto 0) ;rd_memory : OUT s td_log ic_vector (14 downto 0) ;ready : IN s td_log i c ;memory_en : OUT s td_log i c ; −− memory enableimage_ready : OUT s td_log i c ;

−− a c t u a l SSRAM i n t e r f a c e s t a r t s here−−MODE no connect i n t e r l e a v e d b u r s t mode

address : OUT s td_log ic_vector ( 18 DOWNTO 0 ) ;SSRAM_ads_p : OUT s td_log i c ;−−Address Status Processor HIGH

b u r s t s t a r t . . . . s i n g l e wri te /readdata : OUT s td_log ic_vector ( 15 DOWNTO 0 )

) ;end component ;

component SSRAM_read ISPORT(

sys_clk : IN s td_log i c ; −− 50 MHZv_blank : IN s td_log i c ; −−lowblank : IN s td_log i c ; −−highimage_ready : IN s td_log i c ;address : OUT s td_log ic_vector ( 18 DOWNTO 0 ) ;SSRAM_ads_p : OUT s td_log i c ;−−Address Status Processor HIGH

b u r s t s t a r t . . . . s i n g l e wri te /readdata : IN s td_log ic_vector ( 15 DOWNTO 0 ) ;r e s e tn : IN s td_log i c ;pix_data : OUT s td_log ic_vector ( 15 DOWNTO 0 )

) ;


54 Receiver Baseband (VHDL)

END component ;

Component VGA_Ctr ISPORT(

sys_clk : IN s td_log i c ;r e s e tn : IN s td_log i c ;pix_data : IN s td_log ic_vector (15 DOWNTO 0) ;vga_clk : OUT s td_log i c ;vga_b : OUT s td_log ic_vector (9 DOWNTO 0) ;vga_g : OUT s td_log ic_vector (9 DOWNTO 0) ;vga_r : OUT s td_log ic_vector (9 DOWNTO 0) ;vga_hsync : OUT s td_log i c ;vga_sync : OUT s td_log i c ;vga_vsync : OUT s td_log i c ;vga_blank : OUT s td_log i c ;v_blank : OUT s td_log i c −−v e r t i c a l balnk ( a c t i v e low )

) ;


END Component ;

component pll_120PORT(

a r e s e t : IN STD_LOGIC := ’ 0 ’ ;i n c l k 0 : IN STD_LOGIC := ’ 0 ’ ;c0 : OUT STD_LOGIC ;locked : OUT STD_LOGIC

) ;end component ;

COMPONENT audio_appl_rx ISPORT(

sys_clk : IN s td_log i c ;Length_256 : IN s td_log i c ;Length_64 : IN s td_log i c ;Length_32 : IN s td_log i c ;

−−p h y s i c a l l a y e r i n t e r f a c erx_clk : IN s td_log i c ;−−120mhzdata_in : IN s td_log ic_vector (7 downto 0) ;rd_memory : OUT s td_log ic_vector (14 downto 0) ;ready : IN s td_log i c ;memory_en : OUT s td_log i c ; −− memory enable

−−CODEC i n t e r f a c eDACDAT : OUT s td_log i c ;DACLRC : IN s td_log i c ;BLCK : IN s td_log i c ;r e s e tn : IN s td_log i c ;XTI : OUT s td_log i c ;s c l : OUT s td_log i c ;sda : INOUT s td_log i c

) ;


END COMPONENT;

COMPONENT berdecimal_appl_rx i sport (

Clock : in s td_log i c ;LSB : out s td_log ic_vector (7−1 downto 0) ;LSB1 : out s td_log ic_vector (7−1 downto 0) ;LSB2 : out s td_log ic_vector (7−1 downto 0) ;LSB3 : out s td_log ic_vector (7−1 downto 0) ;LSB4 : out s td_log ic_vector (18−1 downto 0) ;a c l r : in s td_log i c ;ber_s ize : in s td_log ic_vector (17−1 downto 0) ;c lk_recovered : in s td_log i c ;

55

data_in_ser ia l : in s td_log i c ;dp : out s td_log i c ;e_lsb : out s td_log ic_vector (7−1 downto 0) ;e_minus : out s td_log ic_vector (7−1 downto 0) ;e_msb : out s td_log ic_vector (7−1 downto 0) ;exp : out s td_log ic_vector (7−1 downto 0) ;no_ber_packets : in s td_log ic_vector (9−1 downto 0) ;sop_de l imiter : in s td_log i c

) ;end COMPONENT;

COMPONENT rx_phys i ca l l aye r i sport (

Clock : in s td_log i c ;a c l r : in s td_log i c ;c lk_recovered : out s td_log i c ;c r c : out s td_log i c ;data_in_ser ia l : out s td_log i c ;decoded_data : out s td_log ic_vector (8−1 downto 0) ;l ength : out s td_log ic_vector (16−1 downto 0) ;ready : out s td_log i c ;rx_in : in s td_log i c ;rx_physicallayer_rx_memory_en : in s td_log i c ;rx_physicallayer_rx_read_memory : in s td_log ic_vector (15−1

downto 0) ;sop_de l imiter : out s td_log i c

) ;end COMPONENT;

COMPONENT kb_conversion i s

port ( c l k : in s td_log i c ;rd : in s td_log i c ;scan_code : in s td_log ic_vector (7 downto 0) ;a s c i : out s td_log ic_vector (7 downto 0) ;output_en : out s td_log i c

) ;END COMPONENT;

COMPONENT lcd_control ler_RX i s

port ( c l k : in s td_log i c ;power : out s td_log i c := ’1 ’ ;a c l r : in s td_log i c ;r s : out s td_log i c ;rd_wrlow : out s td_log i c ;enable : out s td_log i c ;data : inout s td_log ic_vector (7 downto 0) :=(others=>’Z ’ ) ;data_rx : in s td_log ic_vector (7 downto 0) ;ready : in s td_log i c

) ;END COMPONENT;

signal ber_s ize : s td_log ic_vector (17−1 downto 0) ;signal no_ber_packets : s td_log ic_vector (9−1 downto 0) ;

signal c lk_recovered : s td_log i c ;signal data_in_ser ia l : s td_log i c ;signal ready : s td_log i c ;signal memory_en : s td_log i c ;signal ber_sop : s td_log i c ;

−−ver 2 gate i s implemented between p h y s i c a l l a y e r and ber appl l a y e r


signal clk_recovered_pass : s td_log i c ;signal data_in_ser ia l_pass : s td_log i c ;signal ber_sop_pass : s td_log i c ;

signal memory_addr : s td_log ic_vector (14 downto 0) ;signal memory_data : s td_log ic_vector (8−1 downto 0) ;signal l ength : s td_log ic_vector (15 downto 0) ;

signal audio_in : s td_log ic_vector (7 downto 0) ;signal memory_addr_audio : s td_log ic_vector (14 downto 0) ;

signal image_in : s td_log ic_vector (7 downto 0) ;signal memory_addr_image : s td_log ic_vector (14 downto 0) ;signal ready_image : s td_log i c ;signal memory_en_image : s td_log i c ;signal image_ready : s td_log i c ;SIGNAL vga_blank_internal : s td_log i c ;SIGNAL pix_data : s td_log ic_vector ( 15 DOWNTO 0 ) ;SIGNAL v_blank : s td_log i c ;

signal ready_audio : s td_log i c ;

signal memory_en_audio : s td_log i c ;signal ready_kb : s td_log i c ;signal crc_int : s td_log i c ;signal kb_conversion_ready : s td_log i c ;signal output_en : s td_log i c ;signal asc i_out : s td_log ic_vector (7 downto 0) ;

signal Length_256 : s td_log i c ;signal Length_64 : s td_log i c ;signal length_32 : s td_log i c ;

signal rx_clock : s td_log i c ;−−120 mhz

signal address_SSRAM_wr : s td_log ic_vector ( 18 DOWNTO 0 ) ;signal out_en_wr : s td_log i c ; −−a c t i v e l o w

−−s i g n a l SSRAM_clk_wr : s t d _ l o g i c ; −−synchronous c l kmax of 250 MHZ

signal global_wlow_wr : s td_log i c ;−− a c t i v e low s e t to high f o rbyte operation

signal address_SSRAM_rd : s td_log ic_vector ( 18 DOWNTO 0 ) ;signal out_en_rd : s td_log i c ; −−a c t i v e l o w

−−s i g n a l SSRAM_clk_rd : s t d _ l o g i c ; −−synchronous c l kmax of 250 MHZ

signal global_wlow_rd : s td_log i c ;−− a c t i v e low s e t to high f o rbyte operation

signal SSRAM_ads_p_wr : s td_log i c ;signal SSRAM_ads_p_rd : s td_log i c ;

begin

check_point1<=image_ready ;

address_SSRAM<= address_SSRAM_wr when image_ready= ’0 ’ elseaddress_SSRAM_rd ;

out_en<=’1’ when image_ready= ’0 ’ else −−wri te operation’ 0 ’ ;

SSRAM_clk<=Clock ;global_wlow<=’0’ when image_ready= ’0 ’ else

’ 1 ’ ;

57

−− SSRAM_ads_p<=’1’;

SSRAM_ads_p<=SSRAM_ads_p_wr when image_ready= ’0 ’ else −−wri teoperation

SSRAM_ads_p_rd ;

SSRAM_adv<= ’1 ’;SSRAM_ads_c<= ’1 ’;

chip_en_low<= ’0 ’;chip_en2_low<= ’0 ’;chip_en2 <= ’1 ’;bytew_low<=’1’ when image_ready= ’1 ’ else

’Z ’ ;

crc<=crc_int ;

memory_en<=’1’ when l ength=" 0000000000000101 " else −−keyboardmemory_en_audio when l ength=" 0000010000000100 " or l ength="

0000000100000100 " or l ength=" 0000000001000100 " or l ength="0000000000100100 " else −− audio

memory_en_image when l ength=" 0000010000000110 " else’ 0 ’ ;

memory_addr<=" 000000000000011 " when l ength=" 0000000000000101 " else −−keyboard

memory_addr_audio when l ength=" 0000010000000100 " or l ength="0000000100000100 " or l ength=" 0000000001000100 " or l ength="0000000000100100 " else −− audio

memory_addr_image when l ength=" 0000010000000110 " else( others=>’0’) ;

Length_256<=’1’ when l ength=" 0000000100000100 " else’ 0 ’ ;Length_64<=’1’ when l ength=" 0000000001000100 " else’ 0 ’ ;Length_32<=’1’ when l ength=" 0000000000100100 " else’ 0 ’ ;

l 7 : image_rxPORT MAP(

packet_no=>open ,r e s e tn=>ac l r ,rx_clk=>Clock ,data_in=>image_in ,rd_memory=>memory_addr_image ,ready=>ready_image ,memory_en=>memory_en_image ,image_ready=>image_ready ,

−− a c t u a l SSRAM i n t e r f a c e s t a r t s here−−MODE no connect i n t e r l e a v e d b u r s t mode

address=>address_SSRAM_wr ,SSRAM_ads_p=>SSRAM_ads_p_wr,data=>data_ssram

) ;

l 8 : SSRAM_readPORT MAP(

sys_clk=>Clock ,v_blank=>v_blank ,blank=>vga_blank_internal ,image_ready=>image_ready ,address=>address_SSRAM_rd ,SSRAM_ads_p=>SSRAM_ads_p_rd ,


data =>data_ssram ,r e s e tn=>ac l r ,pix_data=>pix_data

) ;vga_blank <= vga_blank_internal ;

l 9 : VGA_CtrPORT MAP(

sys_clk=>Clock ,r e s e tn =>ac l r ,pix_data=>pix_data ,vga_clk=>vga_clk ,vga_b=>vga_b ,vga_g=>vga_g ,vga_r=>vga_r ,vga_hsync=>vga_hsync ,vga_sync=>vga_sync ,vga_vsync=>vga_vsync ,vga_blank=>vga_blank_internal ,v_blank=>v_blank

) ;

l 6 : pl l_120PORT map(

a r e s e t=>not ( a c l r ) ,i n c l k 0=>Clock ,c0=>rx_clock ,locked=>open

) ;

l 1 : rx_phys i ca l l aye rport map(

Clock => rx_clock ,a c l r =>ac l r ,c lk_recovered=>clk_recovered ,c r c => crc_int ,data_in_ser ia l => data_in_ser ia l ,decoded_data => memory_data ,l ength=>length ,ready => ready ,rx_in => ( rx_in ) ,rx_physicallayer_rx_memory_en=> memory_en ,rx_physicallayer_rx_read_memory=> memory_addr ,sop_de l imiter=> ber_sop

) ;

clk_recovered_pass<=clk_recovered when l ength=std_log ic_vector ( to_unsigned(16388 ,16) ) or l ength=std_log ic_vector ( to_unsigned (8196 ,16) )

or l ength=std_log ic_vector ( to_unsigned(4100 ,16) ) or l ength=std_log ic_vector (to_unsigned (2052 ,16) ) else

’ 0 ’ ;data_in_serial_pass<=data_in_ser ia l when l ength=std_log ic_vector (

to_unsigned (16388 ,16) ) or l ength=std_log ic_vector ( to_unsigned (8196 ,16))

or l ength=std_log ic_vector ( to_unsigned(4100 ,16) ) or l ength=std_log ic_vector (to_unsigned (2052 ,16) ) else

’ 0 ’ ;

ber_sop_pass<=ber_sop when l ength=std_log ic_vector ( to_unsigned (16388 ,16) )or l ength=std_log ic_vector ( to_unsigned (8196 ,16) )

or l ength=std_log ic_vector ( to_unsigned

59

(4100 ,16) ) or l ength=std_log ic_vector (to_unsigned (2052 ,16) ) else

’ 0 ’ ;

ber_size<=std_log ic_vector ( to_unsigned (131071 ,17) ) when l ength=std_log ic_vector ( to_unsigned (16388 ,16) ) else

s td_log ic_vector ( to_unsigned (65535 ,17) ) when l ength=std_log ic_vector ( to_unsigned (8196 ,16) ) else



ber_s ize ;

no_ber_packets<=std_log ic_vector ( to_unsigned (32 ,9 ) ) when l ength=std_log ic_vector ( to_unsigned (16388 ,16) ) else

s td_log ic_vector ( to_unsigned (64 ,9 ) ) when l ength=std_log ic_vector( to_unsigned (8196 ,16) ) else

s td_log ic_vector ( to_unsigned (128 ,9 ) ) when l ength=std_log ic_vector ( to_unsigned (4100 ,16) ) else

s td_log ic_vector ( to_unsigned (256 ,9 ) ) when l ength=std_log ic_vector ( to_unsigned (2052 ,16) ) else

no_ber_packets ;

l 2 : berdecimal_appl_rxport map (

Clock => rx_clock ,LSB => LSB,LSB1 => LSB1 ,LSB2 => LSB2 ,LSB3 => LSB3 ,LSB4 => LSB4 ,a c l r => ac l r ,ber_s ize=>ber_size ,c lk_recovered => clk_recovered_pass ,data_in_ser ia l => data_in_seria l_pass ,dp => dp ,e_lsb =>e_lsb ,e_minus => e_minus ,e_msb => e_msb ,exp => exp ,no_ber_packets=>no_ber_packets ,sop_de l imiter=> ber_sop_pass

) ;

ready_audio<=ready when l ength=" 0000010000000100 " or l ength="0000000100000100 " or l ength=" 0000000001000100 " or l ength="0000000000100100 " else

’ 0 ’ ;audio_in<= memory_data when l ength=" 0000010000000100 " or l ength="

0000000100000100 " or l ength=" 0000000001000100 " or l ength="0000000000100100 " else

( others=>’0’) ;

image_in<=memory_data when l ength=" 0000010000000110 " else−−1030( others=>’0’) ;

ready_image<=ready when l ength=" 0000010000000110 " else’ 0 ’ ;

l 3 : audio_appl_rxPORT MAP(

sys_clk=>Clock ,Length_256=> Length_256 ,Length_64=>Length_64 ,Length_32=>Length_32 ,

−−p h y s i c a l l a y e r i n t e r f a c erx_clk => Clock ,data_in => audio_in ,


rd_memory => memory_addr_audio ,ready => ready_audio ,memory_en => memory_en_audio ,

−−CODEC i n t e r f a c eDACDAT => DACDAT,DACLRC => DACLRC,BLCK => BLCK,r e s e tn => ac l r ,XTI => XTI ,s c l => sc l ,sda =>sda

) ;

ready_kb<=ready when l ength=" 0000000000000101 " else’ 0 ’ ;

l 4 : kb_conversion

port map ( c l k => rx_clock ,rd => ready_kb ,scan_code=> memory_data ,a s c i => asci_out ,output_en=> kb_conversion_ready

) ;

output_en<= kb_conversion_ready when crc_int = ’0 ’ else’ 0 ’ ;

l 5 : lcd_control ler_RX

port map ( c l k => rx_clock ,power=> power_lcd ,a c l r => ac l r ,r s => rs_lcd ,rd_wrlow =>rd_wrlow_lcd ,enable =>enable_lcd ,data => data_lcd ,data_rx => asci_out ,ready=> output_en

) ;

end a1 ;

Appendix C

File Transfer ApplicationLayer: Transmitter (VHDL)

LIBRARY i e e e ;USE i e e e . std_logic_1164 . a l l ;USE i e e e . s td_log i c_ar i th . a l l ;USE i e e e . std_logic_unsigned . a l l ;USE i e e e . numeric_std .ALL;

−− This vhdl f i l e implements f i l e t r a n s f e r a p p l i c a t i o n l a y e r . I t encodes−− an image f i l e which i s s tored in the SSRAM memory to many f i x e d−− b y t e s data packets b e f o r e sending i t to the t r a n s m i t t e r PHY l a y e r .−− A byte in the packet i s ass igned with the packet number to−− r e c o n s t r u c t the f i l e in the r e c e i v e r . I t i n c l u d e s in i n t e r f a c e f o r−− connecting to t r a n s m i t t e r p h y s i c a l l a y e r . I t has a b l o c k enable input−− to enable / d i s a b l e f i l e t r a n s f e r mode . D i f f e r e n t image i s trans ferred ,−− s e l e c t e d based on a counter value updated f o r every time an image−− change r e q u e s t i s r e c e i v e d . The code i s s y n t h e s i z a b l e f o r Altera−− DE2−70 Development board .

Entity image_tx i sPORT(−−f l a s h i n t e r f a c e

data_f lash : IN s td_log ic_vector (15 DOWNTO 0) ;f l a sh_addres s : OUT s td_log ic_vector ( 21 DOWNTO 0 ) ;byte_low_flash : OUT s td_log i c ; −−highchip_en_flash : OUT s td_log i c ; −−lowch ip_reset : OUT s td_log i c ;out_en_flash : OUT s td_log i c ; −−here

lowwr_en_flash : OUT s td_log i c ; −−here

high

−− Board i n t e r f a c eimage_mode : IN s td_log i c ;−−j u s t l i k e audio and ber modeimage_change : IN s td_log i c ;−− a l o c a l counter w i l l t rack which

image to send−− p h y s i c a l l a y e r i n t e r f a c e

tx_clk : IN s td_log i c ;−−2.5mhzdata_out : OUT s td_log ic_vector (7 downto 0) ;ack_physical : IN s td_log i c ;sop_out : OUT s td_log i c ;eop_out : OUT s td_log i c ;r e s e tn : IN s td_log i c

61

62 File Transfer Application Layer: Transmitter (VHDL)

) ;END image_tx ;

−− Total p i x e l s 480∗640 "307 ,200"−− f l a s h memory i s 8 Mb 16 b i t s wide memory w i l l have 4 ,194 ,304 l o c a t i o n s−− 13 images can be stored

Architecture A1 of image_tx i s

signal image_counter : s td_log ic_vector (3 downto 0) ;signal f l a sh_address_int : s td_log ic_vector ( 21 DOWNTO 0 ) ;signal s tart_address_int : s td_log ic_vector ( 21 DOWNTO 0 ) ;

signal image_change_int : s td_log ic_vector (1 downto 0) ;signal image_mode_int : s td_log ic_vector (1 downto 0) ;

signal byte_clk_count : s td_log ic_vector (3 downto 0) ;signal enable : s td_log i c ;

signal next_image : s td_log i c ;signal next_image_buf : s td_log i c ;

signal msb : s td_log i c ;signal byte_count : s td_log ic_vector ( 10 DOWNTO 0 ) ;signal kb_count : s td_log ic_vector ( 9 DOWNTO 0 ) ;signal ava i l : s td_log i c ;

signal sop : s td_log i c ;signal eop : s td_log i c ;signal ready : s td_log i c ; −− ack p h y s i c a l l a y e r end of transmissionsignal busy : s td_log i c ;

−−th ese two f u n c t i o n s are must f o r any hardware i n t e r f a c i n g

function r i s e_de t e c t o r ( recent , prev ious : s td_log i c ) return boolean i sbegin

return ( r e cent = ’1 ’ and prev ious = ’0 ’) ;

end ;

function f a l l_d e t e c t o r ( recent , prev ious : s td_log i c ) return boolean i sbegin


end ;

begin

f lash_address<=f lash_address_int ;sop_out<=sop ;eop_out<=eop ;

byte_low_flash <= ’1 ’;chip_en_flash <= ’0 ’;chip_reset <= ’1 ’;out_en_flash <= ’0 ’;wr_en_flash <= ’1 ’;

−− byte c l o c k generatorbyte_clk : process ( tx_clk )

begin

63

i f r i s ing_edge ( tx_clk ) theni f r e s e tn = ’0 ’ then

byte_clk_count<=" 0000 " ;enable <= ’0 ’;

elsei f ( byte_clk_count )=" 0111 " then


elsebyte_clk_count<=byte_clk_count + ’1 ’ ;enable <= ’0 ’;

end i f ;end i f ;

end i f ;

end process ;

−− input synchronizerinput_sync : process ( tx_clk )

begin

i f r i s ing_edge ( tx_clk ) then

i f r e s e tn = ’0 ’ then

image_change_int<=(others=>’0’) ;image_mode_int<=(others=>’0’) ;ready<=ack_physical ;

e l s i f enable = ’1 ’ then

image_change_int (1 )<=image_change ;image_change_int (0 )<=image_change_int (1 ) ;image_mode_int (1 )<=image_mode ;image_mode_int (0 )<=image_mode_int (1 ) ;ready<=ack_physical ;

end i f ;end i f ;end process ;

−−image counter

imagechangeblock : process ( tx_clk )

begin

i f r i s ing_edge ( tx_clk ) thennext_image<=next_image_buf ;

i f ( r e s e tn = ’0 ’) then

image_counter<= ( others=>’0’) ;next_image <= ’0 ’;

e l s i f enable = ’1 ’ theni f r i s e_de t e c t o r ( image_mode_int (1 ) , image_mode_int (0 ) ) then

image_counter<= ( others=>’0’) ;next_image <= ’1 ’;

e l s i f image_mode_int (1 ) = ’1 ’ theni f r i s e_de t e c t o r ( image_change_int (1 ) ,

image_change_int (0 ) ) theni f image_counter=" 1000 " then

image_counter<= ( others=>’0’) ;s tart_address_int <=(others=>’0’) ;


elseimage_counter<= image_counter +

’ 1 ’ ;s tart_address_int<=

start_address_int +std_log ic_vector ( to_unsigned(307200 ,22) ) ;

end i f ;next_image_buf <= ’1 ’;

elsenext_image_buf <= ’0 ’;

end i f ;end i f ;


−− f l a s h address and byte count−− A p i c t u r e of 307 ,200 p i x e l s w i l l be sent in 1024 b y t e s i . e 1 KB packet .

so we send in 600 packets−− i s t byte w i l l have packet number . so a t o t a l of 1026 b y t e s sent in each

packetf lashaddr_gen : process ( tx_clk )begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( image_mode_int (1 ) , image_mode_int(0 ) ) ) then

f lash_address_int <=(others=>’0’) ;msb<= ’1 ’;byte_count<=(others=>’0’) ;kb_count<=(others=>’0’) ;ava i l <= ’0 ’;

e l s i f enable = ’1 ’ theni f image_mode_int (1 ) = ’1 ’ then

i f next_image= ’1 ’ thenf lash_address_int<= start_address_int ;msb<= ’1 ’;byte_count<=(others=>’0’) ;kb_count<=(others=>’0’) ;ava i l <= ’1 ’;

e l s i f busy= ’0 ’ theni f byte_count= std_log ic_vector (

to_unsigned (0 ,11) ) or byte_count=std_log ic_vector ( to_unsigned (1 ,11) )then

i f msb= ’1 ’ thenmsb<= ’0 ’;data_out<= " 000000 " &

kb_count (9 downto 8) ;else

msb<= ’1 ’;data_out<=kb_count (7

downto 0) ;end i f ;byte_count<=byte_count + ’1 ’ ;

e l s i f byte_count= std_log ic_vector (to_unsigned (1026 ,11) ) then−−1026

i f kb_count=std_log ic_vector (to_unsigned (599 ,10) ) then

kb_count<=kb_count ;byte_count<=byte_count ;ava i l <= ’0 ’;msb<= ’1 ’;

65

elsekb_count<=kb_count+ ’1 ’ ;byte_count<=(others=>’0’) ;

−− r e s e t the bytecount f o r next packet

msb<= ’1 ’;end i f ;

elsei f msb= ’1 ’ then

msb<= ’0 ’;data_out<=data_f lash (15

downto 8) ;else

f lash_address_int<=f lash_address_int + ’1 ’ ;

msb<= ’1 ’;data_out<=data_f lash (7

downto 0) ;end i f ;byte_count<=byte_count + ’1 ’ ;

end i f ;

end i f ;

end i f ;end i f ;

end i f ;end process ;

ready_ack : process ( tx_clk )begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( image_mode_int (1 ) , image_mode_int(0 ) ) or r i s e_de t e c t o r ( image_change_int (1 ) , image_change_int (0 ) )) then

busy <= ’0 ’;

e l s i f enable = ’1 ’ theni f image_mode_int (1 ) = ’1 ’then

i f byte_count = std_log ic_vector ( to_unsigned(1026 ,11) ) then

busy <= ’1 ’;e l s i f ready= ’1 ’ then

busy <= ’0 ’;else

busy<=busy ;

end i f ;end i f ;


sop_eop_physica l layer : process ( tx_clk )

begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( image_mode_int (1 ) , image_mode_int(0 ) ) ) then

sop <= ’0 ’;eop <= ’0 ’;


e l s i f enable = ’1 ’ theni f image_mode_int (1 ) = ’1 ’then

i f byte_count = std_log ic_vector ( to_unsigned (0 ,11)) and busy= ’0 ’ and ava i l = ’1 ’ then

sop <= ’1 ’;

else

sop <= ’0 ’;

end i f ;

i f byte_count = std_log ic_vector ( to_unsigned(1025 ,11) ) and ava i l = ’1 ’ then

eop <= ’1 ’;

else

eop <= ’0 ’;

end i f ;

end i f ;end i f ;


end A1 ;

Appendix D

File Transfer ApplicationLayer: Receiver (VHDL)


−− This vhdl f i l e implements f i l e t r a n s f e r a p p l i c a t i o n l a y e r f o r r e c e i v e r .−− The r e c e i v e d data packets from the r e c e i v e r PHY l a y e r are s tored i nt o−− SSRAM memory according to i t s packet and p i x e l addresses . Since , an−− image f i l e i s r e p e a t e d l y sent from the t r a n s m i t t e r the repeated p i x e l s−− are over−w r i t t e n to recover l o s t p i x e l s in the channel . A RGB VGA−− c o n t r o l l e r i s implemented to read image from the memory to the VGA−− screen . I t i n c l u d e s in i n t e r f a c e s f o r connecting to r e c e i v e r p h y s i c a l−− l a y e r and SSRAM memory . The code i s s y n t h e s i z a b l e f o r Altera−− DE2−70 Development board .

Entity image_rx i sPORT(

packet_no : OUT s td_log ic_vector ( 9 DOWNTO 0 ) ;r e s e tn : IN s td_log i c ;rx_clk : IN s td_log i c ;−−50mhzdata_in : IN s td_log ic_vector (7 downto 0) ;rd_memory : OUT s td_log ic_vector (14 downto 0) ;ready : IN s td_log i c ;memory_en : OUT s td_log i c ; −− memory enableimage_ready : OUT s td_log i c ;

−− a c t u a l SSRAM i n t e r f a c e s t a r t s hereaddress : OUT s td_log ic_vector ( 18 DOWNTO 0 ) ;SSRAM_ads_p : OUT s td_log i c ;−−Address Status Processor HIGH

b u r s t s t a r t . . . . s i n g l e wri te /readdata : OUT s td_log ic_vector ( 15 DOWNTO 0 )

) ;END image_rx ;

Architecture A1 of image_rx i s

signal ready_int : s td_log ic_vector (1 downto 0) ;

−− p h y s i c a l l a y e rsignal rd_memory_int : s td_log ic_vector (14 downto 0) ;

67

68 File Transfer Application Layer: Receiver (VHDL)

signal packet_address : s td_log ic_vector ( 9 DOWNTO 0 ) ;signal pixe l_address : s td_log ic_vector ( 8 DOWNTO 0 ) ;signal address_int : s td_log ic_vector ( 18 DOWNTO 0 ) ;signal data_interna l : s td_log ic_vector ( 15 DOWNTO 0 ) ;signal reg_msb : s td_log ic_vector ( 7 DOWNTO 0 ) ;

signal msb : s td_log i c ;signal wr_en : s td_log i c ;signal image_ready_int : s td_log i c ;



end ;



end ;

begin

packet_no<= packet_address ;address<= address_int ;data<= data_interna l when image_ready_int= ’0 ’ else

( others=>’Z ’ ) ;image_ready<=image_ready_int ;memory_en<=wr_en ;rd_memory<=rd_memory_int ;

−−operates at 25 mhzsyncron ize_inputs : process ( rx_clk )begin

i f r i s ing_edge ( rx_clk ) theni f r e s e tn = ’0 ’ then

ready_int<=(others=>’0’) ;

elseready_int (1 )<=ready ;ready_int (0 )<=ready_int (1 ) ;

end i f ;end i f ;

end process ;

set_up_readmode : process ( rx_clk )

begin

i f r i s ing_edge ( rx_clk ) then

i f ( r e s e tn = ’0 ’ ) thenwr_en<= ’0 ’;

e l s i f f a l l_d e t e c t o r ( ready_int (1 ) , ready_int (0 ) ) thenwr_en<= ’1 ’;

69

e l s i f rd_memory_int= std_log ic_vector ( to_unsigned (1026+3 ,15) ) thenwr_en<= ’0 ’;

elsewr_en<=wr_en ;


wr i t e_buf f e r : process ( rx_clk )begin


i f ( r e s e tn = ’0 ’ ) thenrd_memory_int<= std_log ic_vector ( to_unsigned (3 ,15) ) ;packet_address<= ( others=>’0’) ;−− 18 downto 9pixe l_address<= ( others=>’0’) ; −−8 downto 0msb<= ’1 ’;

e l s i f wr_en= ’1 ’ then

i f ( rd_memory_int<= std_log ic_vector ( to_unsigned (1028 ,15) )) then

image_ready_int <= ’0 ’;i f ( rd_memory_int= std_log ic_vector ( to_unsigned

(3 ,15) ) or rd_memory_int= std_log ic_vector (to_unsigned (4 ,15) ) ) then

i f msb= ’1 ’ thenpacket_address (9 downto 8)<=

data_in (1 downto 0) ;msb<= ’0 ’;rd_memory_int<=rd_memory_int+ ’1 ’ ;

elsepacket_address (7 downto 0)<=

data_in (7 downto 0) ;msb<= ’1 ’;rd_memory_int<=rd_memory_int+ ’1 ’ ;

end i f ;

else

i f msb= ’1 ’ thenSSRAM_ads_p<= ’0 ’;reg_msb<=data_in ;msb<= ’0 ’;address_int (18 downto 0)<=

packet_address & pixe l_address;

rd_memory_int<=rd_memory_int+ ’1 ’ ;else

SSRAM_ads_p<= ’1 ’;data_interna l (15 downto 0)<=

reg_msb & data_in ;p ixe l_address<= pixe l_address + ’1 ’ ;msb<= ’1 ’;rd_memory_int<=rd_memory_int+ ’1 ’ ;

end i f ;end i f ;

elserd_memory_int<= std_log ic_vector ( to_unsigned (3 ,15)

) ;p ixe l_address<= ( others=>’0’) ;msb<= ’1 ’;image_ready_int <= ’1 ’;

end i f ;end i f ;

70 File Transfer Application Layer: Receiver (VHDL)


end A1 ;

Appendix E

Audio StreamingApplication Layer:Transmitter (VHDL)

LIBRARY i e e e ;USE i e e e . std_logic_1164 . a l l ;USE i e e e . s td_log i c_ar i th . a l l ;USE i e e e . std_logic_unsigned . a l l ;USE i e e e . numeric_std .ALL;−− This vhdl f i l e implements audio encoder f o r the audio codec of Altera−− DE2−70 development board and a p p l i c a t i o n l a y e r f o r b u i l d i n g encoded−− data in to data packets . I t i n c l u d e s in i n t e r f a c e f o r connecting to−− t r a n s m i t t e r p h y s i c a l l a y e r . I t has a b l o c k enable input to enable /−− d i s a b l e audio mode . I t supports 3 d i f f e r e n t s i z e s of data packet l e n g t h−− through c o n f i g u r a t i o n input . The code i s s y n t h e s i z a b l e f o r Altera−− DE2−70 Development board .

ENTITY aud io_app l i ca t i on l aye r ISPORT(

audio_mode : IN s td_log i c ;Length_256 : IN s td_log i c ;Length_64 : IN s td_log i c ;Length_32 : IN s td_log i c ;s tart_audio : IN s td_log i c ;tx_clk : IN s td_log i c ;−−2.5mhzdata_out : OUT s td_log ic_vector (7 downto 0) ;ack_physical : IN s td_log i c ;sop_out : OUT s td_log i c ;eop_out : OUT s td_log i c ;ADCDAT : IN s td_log i c ;ADCLRC : IN s td_log i c ;BLCK : IN s td_log i c ;r e s e tn : IN s td_log i c ;sys_clk : IN s td_log i c ;−−50 mhz f o r audio i n t e r f a c eXTI : OUT s td_log i c

) ;


END aud io_app l i ca t i on l aye r ;

71

72 Audio Streaming Application Layer: Transmitter (VHDL)

Architecture A1 of aud io_app l i ca t i on l aye r i s

signal wr_address : s td_log ic_vector (10 downto 0) ;signal rd_address : s td_log ic_vector (10 downto 0) ;

signal audio_sample_right : s td_log ic_vector (15 downto 0) ;signal audio_sample_left : s td_log ic_vector (15 downto 0) ;

signal byte_clk_count : s td_log ic_vector (3 downto 0) ;signal enable : s td_log i c ;

signal block1_ready : s td_log i c ;signal block2_ready : s td_log i c ;

signal sop : s td_log i c ;signal eop : s td_log i c ;

type memory_def i s array (0 to 2047) of s td_log ic_vector (7 downto 0) ;−−4number of 512 b y t e s of in−b u i l t memory

signal ram_twoport : memory_def ;

signal s t a r t_ in t : s td_log ic_vector (1 downto 0) ;signal audio_mode_int : s td_log ic_vector (1 downto 0) ;signal ADCLRC_synced : s td_log ic_vector (1 downto 0) ;signal ready : s td_log i c ; −− ack p h y s i c a l l a y e r end of transmissionsignal busy : s td_log i c ;



end ;



end ;

component audio_unit ISPORT(

ADCDAT : IN s td_log i c ;ADCLRC : IN s td_log i c ;BLCK : IN s td_log i c ;r e s e tn : IN s td_log i c ;sys_clk : IN s td_log i c ;audio_sample_left : OUT s td_log ic_vector (15 DOWNTO 0) ;audio_sample_right : OUT s td_log ic_vector (15 DOWNTO 0) ;XTI : OUT s td_log i c ;stable_audio_data : OUT s td_log i c

) ;


END component ;

signal Length_256_sync : s td_log i c ;signal Length_64_sync : s td_log i c ;signal Length_32_sync : s td_log i c ;

73

signal l ength_hal f : i n t e g e r ;signal l e ng th_ fu l l : i n t e g e r ;

begin

l eng th_fu l l<= 511 when Length_256_sync= ’1 ’ and Length_64_sync= ’0 ’ andLength_32_sync= ’0 ’ else

127 when Length_256_sync= ’0 ’ and Length_64_sync= ’1 ’ andLength_32_sync= ’0 ’ else


2047 ;

length_hal f<= 255 when Length_256_sync= ’1 ’ and Length_64_sync= ’0 ’ andLength_32_sync= ’0 ’ else



1023 ;

−−3200 ns period c l o c k (325 khz )−− audio samples max of 96 khz (48 khz two channels )byte_clk : process ( tx_clk )

begin

i f r i s ing_edge ( tx_clk ) theni f r e s e tn = ’0 ’ then


elsei f ( byte_clk_count )=" 0111 " then


elsebyte_clk_count<=byte_clk_count + ’1 ’ ;enable <= ’0 ’;

end i f ;end i f ;

end i f ;

end process ;

−− 1 recent−− 0 previous

input_sync : process ( tx_clk )

begin



s tar t_int <=(others=>’0’) ;ADCLRC_synced <= ( others=>’0’) ;audio_mode_int<=(others=>’0’) ;


e l s i f enable = ’1 ’ then

s t a r t_ in t (1 )<=start_audio ;s t a r t_ in t (0 )<=sta r t_ in t (1 ) ;audio_mode_int (1 )<=audio_mode ;audio_mode_int (0 )<=audio_mode_int (1 ) ;ready<=ack_physical ;

ADCLRC_synced(1) <= ADCLRC;ADCLRC_synced(0) <= ADCLRC_synced(1) ;


−− t h i s process w r i t e s in streaming data in the b u f f e r i r r e s p e c t i v e ofoverwri te

−− f i r s t byte corresponds to l e f t channel

s t r eaming_wr i tebu f f e r : process ( tx_clk )begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) ) orr i s e_de t e c t o r ( audio_mode_int (1 ) , audio_mode_int (0 ) ) ) then

wr_address<= ( others=>’0’) ;

e l s i f enable = ’1 ’ theni f s t a r t_ in t (1 ) = ’1 ’ and audio_mode_int (1 ) = ’1 ’ then −−

only when " s t a r t button " i s pushed streaming s t a r t e dat the t x

i f r i s e_de t e c t o r (ADCLRC_synced(1) ,ADCLRC_synced(0)) then−− r i g h t channel

ram_twoport ( conv_integer ( wr_address ) ) <=audio_sample_right (15 downto 8) ; −−msb

i f wr_address = std_log ic_vector (to_unsigned ( l ength_fu l l , 1 1 ) ) then

wr_address <= ( others=>’0’) ;Length_256_sync<=Length_256 ;Length_64_sync<=Length_64 ;Length_32_sync<=Length_32 ;

e l s i f wr_address = x " 000 " then−− l e f tchannel i s in f i r s t byte

wr_address <= ( others=>’0’) ;else

wr_address <= wr_address + ’1 ’ ;end i f ;

e l s i f f a l l_d e t e c t o r (ADCLRC_synced(1) ,ADCLRC_synced(0) ) then−− l e f t channel

ram_twoport ( conv_integer ( wr_address ) ) <=audio_sample_left (15 downto 8) ; −−msb

i f wr_address = std_log ic_vector (to_unsigned ( l ength_fu l l , 1 1 ) ) then

wr_address <= ( others=>’0’) ;Length_256_sync<=Length_256 ;Length_64_sync<=Length_64 ;Length_32_sync<=Length_32 ;

elsewr_address <= wr_address + ’1 ’ ;

end i f ;

75

end i f ;

end i f ;end i f ;


−−c o n t r o l b l o c k−−ready s i g n a l f o r two b l o c k s f o r two packets in the b u f f e rs e t_r e s e tb l o ck s : process ( tx_clk )begin

i f r i s ing_edge ( tx_clk ) theni f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) ) or

r i s e_de t e c t o r ( audio_mode_int (1 ) , audio_mode_int (0 ) ) ) thenblock1_ready <= ’0 ’;block2_ready <= ’0 ’;

e l s i f enable = ’1 ’ theni f s t a r t_ in t (1 ) = ’1 ’ and audio_mode_int (1 ) = ’1 ’ then

i f wr_address = std_log ic_vector ( to_unsigned (length_hal f , 1 1 ) ) then

block1_ready <= ’1 ’;

e l s i f rd_address = std_log ic_vector ( to_unsigned (length_hal f , 1 1 ) ) then


e l s i f wr_address = std_log ic_vector ( to_unsigned (l ength_fu l l , 1 1 ) ) then


e l s i f rd_address = std_log ic_vector ( to_unsigned (l ength_fu l l , 1 1 ) ) then


end i f ;end i f ;


sop_eop_physica l layer : process ( tx_clk )

begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) )orr i s e_de t e c t o r ( audio_mode_int (1 ) , audio_mode_int (0 ) ) ) then

sop <= ’0 ’;eop <= ’0 ’;

e l s i f enable = ’1 ’ theni f s t a r t_ in t (1 ) = ’1 ’ and audio_mode_int (1 ) = ’1 ’then

i f block1_ready= ’1 ’ and rd_address = x " 000 " andbusy= ’0 ’ then

sop <= ’1 ’;

e l s i f block2_ready= ’1 ’ and rd_address =std_log ic_vector ( to_unsigned ( l ength_hal f +1 ,11)) and busy= ’0 ’ then

sop <= ’1 ’;


else

sop <= ’0 ’;

end i f ;

i f block1_ready= ’1 ’ and rd_address =std_log ic_vector ( to_unsigned ( length_hal f , 1 1 ) )then

eop <= ’1 ’;

e l s i f block2_ready= ’1 ’ and rd_address =std_log ic_vector ( to_unsigned ( l ength_fu l l , 1 1 ) )then

eop <= ’1 ’;

else

eop <= ’0 ’;

end i f ;

end i f ;end i f ;


ready_ack : process ( tx_clk )begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) ) orr i s e_de t e c t o r ( audio_mode_int (1 ) , audio_mode_int (0 ) ) ) then

busy <= ’0 ’;

e l s i f enable = ’1 ’ theni f s t a r t_ in t (1 ) = ’1 ’ and audio_mode_int (1 ) = ’1 ’then

i f eop= ’1 ’ thenbusy <= ’1 ’;

e l s i f ready= ’1 ’ thenbusy <= ’0 ’;

elsebusy<=busy ;

end i f ;end i f ;


s end_phys i ca l l ayer : process ( tx_clk )begini f r i s ing_edge ( tx_clk ) then

i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) )orr i s e_de t e c t o r ( audio_mode_int (1 ) , audio_mode_int (0 ) ) ) then

rd_address<= ( others=>’0’) ;

e l s i f enable = ’1 ’ theni f s t a r t_ in t (1 ) = ’1 ’ and audio_mode_int (1 ) = ’1 ’ then

i f ( block1_ready= ’1 ’ or block2_ready= ’1 ’) and busy= ’0 ’ then

data_out<= ram_twoport ( conv_integer (rd_address ) ) ;

77

i f rd_address = std_log ic_vector (to_unsigned ( l ength_fu l l , 1 1 ) ) then

rd_address <= ( others=>’0’) ;

else

rd_address <= rd_address + ’1 ’ ;

end i f ;end i f ;

end i f ;end i f ;


sop_out<=sop ;eop_out<=eop ;

l 1 : audio_unit port map

( ADCDAT => ADCDAT ,ADCLRC => ADCLRC,BLCK => BLCK,r e s e tn => resetn ,sys_clk => sys_clk ,audio_sample_left => audio_sample_left ,audio_sample_right => audio_sample_right ,XTI => XTI ,stable_audio_data => open ) ;

end A1 ;

Appendix F

Audio StreamingApplication Layer: Receiver(VHDL)


−− This vhdl f i l e implements audio decoder f o r the audio codec of Altera−− DE2−70 development board and a p p l i c a t i o n l a y e r f o r transforming data−− packets in to b y t e s . I t i n c l u d e s in i n t e r f a c e f o r connecting to r e c e i v e r−− p h y s i c a l l a y e r . The audio mode i s enabled / d i s a b l e d by the l e n g t h of the−− r e c e i v e d data packet . This a p p l i c a t i o n l a y e r has 3 d i f f e r e n t s i z e s of−− data packet l e n g t h mapped to r e c e i v e data from PHY l a y e r . The audio−− i s streamed to two b u f f e r s to wri te in one b u f f e r and play ( read )−− s tored audio from the second b u f f e r . The code i s s y n t h e s i z a b l e f o r−− Altera DE2−70 Development board .

ENTITY audio_rx ISPORT(

Length_256 : IN s td_log i c ;Length_64 : IN s td_log i c ;Length_32 : IN s td_log i c ;

−−p h y s i c a l l a y e r i n t e r f a c estart_audio : IN s td_log i c ;r e s e tn : IN s td_log i c ;rx_clk : IN s td_log i c ;−−50mhzdata_in : IN s td_log ic_vector (7 downto 0) ;rd_memory : OUT s td_log ic_vector (14 downto 0) ;ready : IN s td_log i c ;memory_en : OUT s td_log i c ; −− memory enabledata_out : OUT s td_log ic_vector (15 downto 0) ;rd_buf : IN s td_log ic_vector (10 downto 0) ;block1_ready : OUT s td_log i c ;block2_ready : OUT s td_log i c ;DACLRC : IN s td_log i c

) ;

78

79


END audio_rx ;

Architecture a1 of audio_rx i s

signal DACLRC_synced : s td_log ic_vector (1 downto 0) ;signal BLCK_synced : s td_log ic_vector (1 downto 0) ;signal s t a r t_ in t : s td_log ic_vector (1 downto 0) ;signal ready_int : s td_log ic_vector (1 downto 0) ;

−− p h y s i c a l l a y e rsignal rd_memory_int : s td_log ic_vector (14 downto 0) ;

−− Audio Buffersignal wr_buf_address : s td_log ic_vector (10 downto 0) ;signal rd_buf_address : s td_log ic_vector (10 downto 0) ;

signal data_out_int : s td_log ic_vector (7 downto 0) ;

signal wr_enable : s td_log i c ;signal s e t_re s e tb l o ck1 : s td_log i c ;signal s e t_re s e tb l o ck2 : s td_log i c ;



end ;



end ;

type memory_def i s array (0 to 2047) of s td_log ic_vector (7 downto 0) ;−−4number of 512 b y t e s of in−b u i l t memory

signal ram_twoport : memory_def ;

signal l ength_hal f : i n t e g e r ;

begin

l ength_hal f<= 255 when Length_256= ’1 ’ and Length_64= ’0 ’ and Length_32= ’0 ’else

63 when Length_256= ’0 ’ and Length_64= ’1 ’ and Length_32= ’0 ’else

31 when Length_256= ’0 ’ and Length_64= ’0 ’ and Length_32= ’1 ’else

1023 ;

block1_ready<=set_re s e tb l o ck1 ;block2_ready<=set_re s e tb l o ck2 ;

rd_buf_address<=rd_buf ;rd_memory<=rd_memory_int ;memory_en<=wr_enable ;data_out<=data_out_int (7 downto 0) & x " 00 " ;

syncron ize_inputs : process ( rx_clk )

80 Audio Streaming Application Layer: Receiver (VHDL)

begini f r i s ing_edge ( rx_clk ) then


s tar t_int <=(others=>’0’) ;ready_int<=(others=>’0’) ;

elses t a r t_ in t (1 )<=start_audio ;s t a r t_ in t (0 )<=sta r t_ in t (1 ) ;ready_int (1 )<=ready ;ready_int (0 )<=ready_int (1 ) ;DACLRC_synced(1) <= DACLRC;DACLRC_synced(0) <= DACLRC_synced(1) ;

end i f ;end i f ;

end process ;

−− A wri te enable s i g n a l to enable the audio b u f f e r to wri te in ther e c e i v e d data

enab le_buf fe r : process ( rx_clk )

begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) ) ) thenwr_enable <= ’0 ’;

e l s i f s t a r t_ in t (1 ) = ’1 ’ theni f f a l l_d e t e c t o r ( ready_int (1 ) , ready_int (0 ) ) then

wr_enable <= ’1 ’;

e l s i f rd_memory_int= std_log ic_vector ( to_unsigned (l ength_hal f +3 ,15) ) then−− 3+1024 count s t a r t from 0

wr_enable <= ’0 ’;

elsewr_enable<=wr_enable ;

end i f ;end i f ;


−− The b u f f e r s are of s i z e to s t o r e two data packets of 1024 b y t e s each .Two b u f f e r s are used . A set_reset f l a g i s ass igned f o r memories toavoid reading the same read data

s e t_re s e t_ f l ag : process ( rx_clk )begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) ) ) thense t_rese tb lock1 <= ’0 ’;s e t_rese tb lock2 <= ’0 ’;

e l s i f s t a r t_ in t (1 ) = ’1 ’ theni f wr_buf_address = std_log ic_vector ( to_unsigned (1023 ,11) )

thense t_rese tb lock1 <= ’1 ’;

e l s i f rd_buf_address = std_log ic_vector ( to_unsigned(1023+1 ,11) ) then

81

se t_rese tb lock1 <= ’0 ’;else

se t_rese tb lock1<=set_re s e tb l o ck1 ;end i f ;

i f wr_buf_address = std_log ic_vector ( to_unsigned (2047 ,11) )then

se t_rese tb lock2 <= ’1 ’;

e l s i f rd_buf_address = std_log ic_vector ( to_unsigned(2047 ,11) ) then

se t_rese tb lock2 <= ’0 ’;else

se t_rese tb lock2<=set_re s e tb l o ck2 ;end i f ;


−− A two port ( concurrent read and wri te ) RAM i s used

wr i te_buf f e r : process ( rx_clk )begin


i f ( r e s e tn = ’0 ’ or r i s e_de t e c t o r ( s t a r t_ in t (1 ) , s t a r t_ in t (0 ) ) ) thenrd_memory_int<= std_log ic_vector ( to_unsigned (3 ,15) ) ;wr_buf_address<= ( others=>’0’) ;

e l s i f s t a r t_ in t (1 ) = ’1 ’ theni f wr_enable= ’1 ’ then

ram_twoport ( conv_integer ( wr_buf_address ) )<=data_in;

i f rd_memory_int= std_log ic_vector ( to_unsigned (l ength_hal f +3 ,15) ) then

rd_memory_int<= std_log ic_vector (to_unsigned (3 ,15) ) ;

elserd_memory_int<=rd_memory_int+ ’1 ’ ;

end i f ;

i f wr_buf_address= std_log ic_vector ( to_unsigned(2047 ,11) ) then

wr_buf_address<= ( others=>’0’) ;

elsewr_buf_address<=wr_buf_address + ’1 ’ ;

end i f ;end i f ;


−− r e g i s t e r e d address−− when the data i s once read the data output w i l l be ’0 ’

read_buf fer : process ( rx_clk )begin

i f r i s ing_edge ( rx_clk ) theni f conv_integer ( rd_buf_address )<=1023 then

i f s e t_re s e tb l o ck1 = ’1 ’ thendata_out_int<=ram_twoport ( conv_integer (

82 Audio Streaming Application Layer: Receiver (VHDL)

rd_buf_address ) ) ;else

data_out_int<=(others=>’0’) ;

end i f ;

e l s i f conv_integer ( rd_buf_address )>1023 and conv_integer (rd_buf_address )<=2047 then

i f s e t_re s e tb l o ck2 = ’1 ’ thendata_out_int<=ram_twoport ( conv_integer (

rd_buf_address ) ) ;else

data_out_int<=(others=>’0’) ;

end i f ;end i f ;


end a1 ;

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Institutionen för systemteknik - DiVA portalliu.diva-portal.org/smash/get/diva2:660503/FULLTEXT01.pdf · Institutionen för systemteknik Department of Electrical Engineering