Institutionen för systemteknik - DiVA portalliu.diva-portal.org/smash/get/diva2:383331/FULLTEXT01.pdf · Institutionen för systemteknik Department of Electrical Engineering Examensarbete

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

Study of Time-Interleaved SAR ADC andImplementation of Comparator for High Definition

Video ADC in 65nm CMOS Process

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan vid Linköpings universitet

av

Sara Qazi ([email protected])

LiTH-ISY-EX--2010/4344--SE

Linköping 2010

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

Study of Time-Interleaved SAR ADC andImplementation of Comparator for High Definition

Video ADC in 65nm CMOS Process

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av


LiTH-ISY-EX--2010/4344--SE

Handledare: Dr. J. Jacob Wiknerisy, Linköpings Universitet

Examinator: Dr. J. Jacob Wiknerisy, Linköpings Universitet

Linköping, 21 December, 2010

Avdelning, InstitutionDivision, Department

Division of Electronic SystemsDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2010-12-21

SpråkLanguage

� Svenska/Swedish� Engelska/English

�

�

RapporttypReport category

� Licentiatavhandling� Examensarbete� C-uppsats� D-uppsats� Övrig rapport�

�

URL för elektronisk versionhttp://www.systems.isy.liu.se

http://www.es.liu.se

ISBN—

ISRNLiTH-ISY-EX--2010/4344--SE

Serietitel och serienummerTitle of series, numbering

ISSN—

TitelTitle

Studie av Tidsmultiplexad SAR ADC och Konstruktion av komparator för högup-plöst Video ADC i 65nm CMOS.Study of Time-Interleaved SAR ADC and Implementation of Comparator for HighDefinition Video ADC in 65nm CMOS Process

FörfattareAuthor


SammanfattningAbstract

The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.

The thesis initially focuses upon selection of suitable Analog to Digital Con-verter (ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power consumption.

In second phase a mathematical model of a Time-Interleaved Successive Ap-proximation Register (TI-SAR) ADC is developed which emulates the behavior ofSAR ADC in Matlab and the errors that are characteristic of the time interleavedstructure are modeled.

In the third phase a behavioral model of TI-SAR ADC having 16 channels and12 bit resolution, is built using the top-down methodology in Cadence simulationtool. All the modules were modeled at behavioral level in Verilog-A. The func-tionality of the model is verified by simulation using signal of 30 MHz and clockfrequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signalto Noise Distortion ratio) 74 dB is achieved.

In the final phase two architectures of comparators are implemented in 65nmtechnology at schematic level. Simulation results show that SNDR of 71 dB isachievable with a minimal power consumption of 169.6 µWper comparator runningat 300 MHz.

NyckelordKeywords ADC, Comparator, Analog Front End

AbstractThe Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.

The thesis initially focuses upon selection of suitable Analog to Digital Con-verter (ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power consumption.

In second phase a mathematical model of a Time-Interleaved Successive Ap-proximation Register (TI-SAR) ADC is developed which emulates the behavior ofSAR ADC in Matlab and the errors that are characteristic of the time interleavedstructure are modeled.

In the third phase a behavioral model of TI-SAR ADC having 16 channels and12 bit resolution, is built using the top-down methodology in Cadence simulationtool. All the modules were modeled at behavioral level in Verilog-A. The func-tionality of the model is verified by simulation using signal of 30 MHz and clockfrequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signalto Noise Distortion ratio) 74 dB is achieved.

In the final phase two architectures of comparators are implemented in 65nmtechnology at schematic level. Simulation results show that SNDR of 71 dB isachievable with a minimal power consumption of 169.6 µW per comparator run-ning at 300 MHz.

v

Acknowledgments

First of all I would like to thank Allah “Alhamdulilallah”, for giving me thestrength to accomplish this task.I am extremely grateful to my supervisor J. Jacob Wikner for being a guide, amentor, an amazing teacher and most of all a critic. I have learned a lot from himand its been great fun especially with the weekly meetings.I am thankful to Aiysha. A. Khalifa for being a wonderful friend and being a greatsupport throughout my masters studies.I owe my deepest gratitude to my parents (Ama and Aba) and my family (threesisters) for believing in me and for their love and prayers.I am very thankful to my husband Fahad for his friendship, love, support, patienceand believing in my potential. I can never thank him enough for all he has donefor me especially having fruitful technical discussion round the clock even at home(bearing with me).Lastly, I offer my regards and blessings to all of those who supported me in anyrespect during the completion of the project.

Sara Qazi

vii

List of Figures

1.1 Block diagram of video Analog Front End IC [4]. . . . . . . . . . 10

2.1 Ideal ADC characteristic [8]. Copied from Analog-to-Digital Con-verters Testing by Kent. H. Lundsberg 2002. . . . . . . . . . . . 14

2.2 Quantization error for an ideal ADC [8]. Copied from Analog-to-Digital Converters Testing by Kent. H. Lundsberg 2002. . . . . . 14

2.3 Offset and gain errors in ADC [8]. Copied from Analog-to-DigitalConverters Testing by Kent. H. Lundsberg 2002 . . . . . . . . . 15

2.4 Non-linear errors in ADC [8]. Copied from Analog-to-DigitalConverters Testing by Kent. H. Lundsberg 2002 . . . . . . . . . 16

3.1 Block diagram of Flash ADC [9]. . . . . . . . . . . . . . . . . . . 203.2 Block diagram of Pipelined ADC (12-bit ADC with four 3bit

stages and a 4bit flash ADC) [10]. . . . . . . . . . . . . . . . . . 213.3 Block diagram of Sigma Delta ADC (1-bit ADC) [11]. . . . . . . 223.4 Block diagram of SAR ADC [12] . . . . . . . . . . . . . . . . . . 23

4.1 SAR operation [12]. . . . . . . . . . . . . . . . . . . . . . . . . . 244.2 Block diagram showing submodules of Successive Approximation

Register ADC [12]. . . . . . . . . . . . . . . . . . . . . . . . . . . 254.3 Block diagram of Time-Interleaved ADC. . . . . . . . . . . . . . 27

5.1 Block diagram of MATLAB Model of Time-Interleaved ADC. . . 295.2 Input signal (spectrum and time domain graph). . . . . . . . . . . 305.3 Channel input signals (time domain graph). . . . . . . . . . . . . 305.4 Output signal (spectrum and time domain graph). . . . . . . . . 315.5 Output spectrum with gain errors σa = 0.1. . . . . . . . . . . . . 325.6 Output spectrum with offset errors σo = 0.1. . . . . . . . . . . . 335.7 Output spectrum with channel jitter σt = 10ps. . . . . . . . . . . 345.8 Output spectrum with cycle to cycle jitter σc2c = 0.1ns. . . . . . 355.9 Delta signal in absence of error (spectrum and time domain graph). 365.10 Delta signal in the presence of gain error (spectrum and time

domain graph). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375.11 Delta signal in the presence of offset error (spectrum and time

domain graph). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375.12 Delta signal in the presence of channel jitter (spectrum and time

domain graph). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385.13 Delta signal in the presence of long-term/drift jitter (spectrum

and time domain graph). . . . . . . . . . . . . . . . . . . . . . . . 38

1

5.14 Delta signal in the presence of cycle-to-cycle jitter (spectrum andtime domain graph). . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.15 Standard frame for video display testing. . . . . . . . . . . . . . . 405.16 Effect of addition of Additive White Gaussian Noise (AWGN) on

frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405.17 Effect of offset error on frame. . . . . . . . . . . . . . . . . . . . . 415.18 Effect of gain error on frame. . . . . . . . . . . . . . . . . . . . . 415.19 Effect of distortions on frame. . . . . . . . . . . . . . . . . . . . . 425.20 Effect of fine quantization (12-bit) on frame. . . . . . . . . . . . . 435.21 Effect of intermediate level of quantization (8-bit) on frame. . . . 435.22 Effect of coarse quantization (1-bit) on frame. . . . . . . . . . . . 44

6.1 The 16 phases and the system clock. . . . . . . . . . . . . . . . . 496.2 Block diagram of 16 channel 12-bit TI-SAR ADC. . . . . . . . . 506.3 Block diagram of 16 channel 12-bit TI-ADC (Cadence Block). . . 516.4 Block diagram of channel SAR ADC. . . . . . . . . . . . . . . . 526.5 SAR ADC internal block diagram (Cadence block) . . . . . . . . 536.6 TI-SAR ADC test bench (Cadence block). . . . . . . . . . . . . . 556.7 Time domain output of TI-SAR ADC (Cadence block). . . . . . . 56

7.1 Latch-only comparator operation [15]. . . . . . . . . . . . . . . . 61

8.1 Transistor-level schematic of pre-amplifier. . . . . . . . . . . . . . 648.2 Gain of pre-amplifier. . . . . . . . . . . . . . . . . . . . . . . . . 658.3 Offset of pre-amplifier . . . . . . . . . . . . . . . . . . . . . . . . 658.4 Transistor-level schematic of the SR latch. . . . . . . . . . . . . . 678.5 Transistor-level schematic of the comparator1 architecture. . . . 688.6 Propagation delay of comparator1. . . . . . . . . . . . . . . . . . 698.7 Offset of comparator1. . . . . . . . . . . . . . . . . . . . . . . . . 708.8 Transistor-level schematic of comparator2 . . . . . . . . . . . . . 728.9 Propagation delay of comparator2. . . . . . . . . . . . . . . . . . 738.10 Offset of comparator2. . . . . . . . . . . . . . . . . . . . . . . . . 74

9.1 TI-SAR ADC test bench (Cadence block) . . . . . . . . . . . . . 779.2 Histogram plot of ADC for sinusoidal input. . . . . . . . . . . . . 789.3 SNDR versus signal amplitude graph for TI-SAR ADC using

comparator1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799.4 ENOB versus signal amplitude graph for TI-SAR ADC using

comparator1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799.5 Result of FFT test. Output spectrum of TI-SAR ADC using

comparator1 for signal amplitude of 0.25 Vpeak. . . . . . . . . . . 809.6 Result of code density test. Histogram of TI-SAR ADC using

comparator1 for signal amplitude of 0.25 Vpeak. . . . . . . . . . . 819.7 SNDR versus signal amplitude graph for TI-SAR ADC using

comparator2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829.8 ENOB versus signal amplitude graph for TI-SAR ADC using

comparator2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839.9 Result of FFT test. Output spectrum of TI-SAR ADC using

comparator2 for signal amplitude of 0.15 Vpeak. . . . . . . . . . . 84

2

9.10 Result of FFT test. Output spectrum of TI-SAR ADC usingcomparator2 for signal amplitude of 0.45 Vpeak. . . . . . . . . . . 84

9.11 Result of code density test. Histogram of TI-SAR ADC usingcomparator2 for signal amplitude of 0.15 Vpeak. . . . . . . . . . . 85


9.13 Result of FFT test. Output spectrum of TI-SAR ADC usingcomparator1 for signal amplitude of 0.5 Vpeak. . . . . . . . . . . . 87

9.14 Result of code density test. Histogram of TI-SAR ADC usingcomparator1 for signal amplitude of 0.5 Vpeak. . . . . . . . . . . . 88

9.15 Result of FFT test. Output spectrum of TI-SAR ADC usingcomparator2 for signal amplitude of 0.35 Vpeak. . . . . . . . . . . 90


A.1 Video signal composition [22]. Copied from Video Signal Mea-surement and Generation Fundamentals Dec 11, 2009 . . . . . . 94

A.2 Video levels [22]. Copied from Video Signal Measurement andGeneration Fundamentals Dec 11, 2009 . . . . . . . . . . . . . . . 95

A.3 Monochrome composite video signal (luma steps from white toblack) [22]. Copied from Video Signal Measurement and Gener-ation Fundamentals Dec 11, 2009 . . . . . . . . . . . . . . . . . . 98

A.4 Color information signal for a color bar line (including the colorburst) [22]. Copied from Video Signal Measurement and Gener-ation Fundamentals Dec 11, 2009 . . . . . . . . . . . . . . . . . . 98

A.5 Color Composite Video Signal for a Color Bar Line [22]. Copiedfrom Video Signal Measurement and Generation FundamentalsDec 11, 2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3

List of Tables

1.1 Video ADC specification (modified from [2]). . . . . . . . . . . . 12

3.1 Comparison of ADC architectures modified from [13]. . . . . . . . 23

5.1 SNDR in the presence of errors. . . . . . . . . . . . . . . . . . . . 36

6.1 Summary of simulation result of the TI-SAR ADC behavioralmodel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.1 Optimized component values for pre-amplifier. . . . . . . . . . . 648.2 Achieved simulation results of pre-Amplifier. . . . . . . . . . . . 668.3 Optimized component values for comparator1. . . . . . . . . . . . 698.4 Achieved simulation results of comparator1. . . . . . . . . . . . . 718.5 Optimized component values of comparator2. . . . . . . . . . . . 738.6 Achieved simulation results of comparator2 . . . . . . . . . . . . 75

9.1 Summary of the simulation results of the TI-SAR ADC usingcomparator1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.2 Summary of the simulation results of the TI-SAR ADC usingcomparator2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.3 Simulation results of the TI-SAR ADC using comparator1 withideal pre-amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.4 Simulation results of the TI-SAR ADC using comparator2 withideal pre-amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . 91

A.1 Properties of TV and computer video formats [23]. . . . . . . . . 97

4

Contents

1 Introduction 81.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1.1 Video Analog Front End IC . . . . . . . . . . . . . . . . 91.1.2 Time-Reference Channel . . . . . . . . . . . . . . . . . . . 91.1.3 Digitizing Channel . . . . . . . . . . . . . . . . . . . . . . 11

1.2 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 111.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 ADC Fundamentals and Performance Metrics 132.1 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . 13

2.1.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.2 Quantization Error . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Static Performance Metrics . . . . . . . . . . . . . . . . . . . . . 142.2.1 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.2 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.3 Differential Non-Linearity (DNL) . . . . . . . . . . . . . . 152.2.4 Integral Non-Linearity (INL) . . . . . . . . . . . . . . . . 152.2.5 Missing codes . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3 Dynamic Performance Metrics . . . . . . . . . . . . . . . . . . . . 162.3.1 Signal to Noise Ratio (SNR) . . . . . . . . . . . . . . . . 172.3.2 Spurious Free Dynamic range (SFDR) . . . . . . . . . . . 172.3.3 Total Harmonic Distortion (THD) . . . . . . . . . . . . . 172.3.4 Signal to Noise and Distortion Ratio (SNDR) . . . . . . . 182.3.5 Effective Number Of Bits (ENOB) . . . . . . . . . . . . . 182.3.6 Dynamic Range (DR) . . . . . . . . . . . . . . . . . . . . 182.3.7 Effective Resolution Bandwidth (ERB) . . . . . . . . . . 18

3 ADC Architectures 193.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.1 Functionality of Flash ADC . . . . . . . . . . . . . . . . . 193.2 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Functionality of Pipelined ADC . . . . . . . . . . . . . . . 203.3 Sigma Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1 Functionality of Sigma Delta ADC . . . . . . . . . . . . . 213.4 Successive Approximation Register (SAR) ADC . . . . . . . . . . 22

3.4.1 Functionality of SAR ADC . . . . . . . . . . . . . . . . . 223.5 Comparison of the ADC Architectures . . . . . . . . . . . . . . . 22

5

3.6 Selecting the Architecture and Why? . . . . . . . . . . . . . . . . 23

4 Successive Approximation Register (SAR) ADC 244.1 The Successive Approximation (SA) Algorithm . . . . . . . . . . 244.2 SAR ADC Submodules . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.1 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . 254.2.2 Digital to Analog Converter (DAC) . . . . . . . . . . . . 264.2.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 264.2.4 Successive Approximation Register (SAR) . . . . . . . . . 26

4.3 Time-Interleaved SAR ADC . . . . . . . . . . . . . . . . . . . . . 26

5 Mathematical Model of Time-Interleaved SAR ADC 285.1 Introduction and purpose . . . . . . . . . . . . . . . . . . . . . . 285.2 Modelling Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2.1 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . 325.2.2 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . 325.2.3 Channel Jitter . . . . . . . . . . . . . . . . . . . . . . . . 335.2.4 Long Term Jitter (LTJ) . . . . . . . . . . . . . . . . . . . 345.2.5 Cycle to cycle Jitter (Random Jitter) . . . . . . . . . . . 34

5.3 Identifying the killer ... . . . . . . . . . . . . . . . . . . . . . . . . 365.4 Demonstration of Errors . . . . . . . . . . . . . . . . . . . . . . . 395.5 Error Reduction Techniques . . . . . . . . . . . . . . . . . . . . . 44

5.5.1 Two-Rank Sample and Hold . . . . . . . . . . . . . . . . . 445.5.2 Randomization . . . . . . . . . . . . . . . . . . . . . . . . 45

6 Behavioral Model of TI-SAR ADC 466.1 Introduction and Purpose . . . . . . . . . . . . . . . . . . . . . . 466.2 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.2.1 Sample/Track and Hold (S/H or T/H) . . . . . . . . . . . 476.2.2 Digital to Analog Converter (DAC) . . . . . . . . . . . . 476.2.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.4 Successive Approximation Register (SAR) . . . . . . . . . 47

6.3 TI-SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.3.1 Phase Generation Block . . . . . . . . . . . . . . . . . . . 486.3.2 Timing Scheme for TI-SAR . . . . . . . . . . . . . . . . . 48

6.4 Verifying Functionality . . . . . . . . . . . . . . . . . . . . . . . . 54

7 High-speed Comparator Design 587.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587.2 Comparator Performance Metrics . . . . . . . . . . . . . . . . . . 58

7.2.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 587.2.2 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597.2.3 Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 59

7.3 Comparator Non-idealities . . . . . . . . . . . . . . . . . . . . . . 597.3.1 Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 607.3.2 Kick-back Noise . . . . . . . . . . . . . . . . . . . . . . . 607.3.3 Metastability . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.4 Types of Comparators . . . . . . . . . . . . . . . . . . . . . . . . 607.4.1 Open-loop Comparator . . . . . . . . . . . . . . . . . . . 617.4.2 Latch-only Comparator . . . . . . . . . . . . . . . . . . . 61

6

7.4.3 Latch with Pre-amplifier . . . . . . . . . . . . . . . . . . . 62

8 Implementation of High-speed, Low-offset Comparators 638.1 Pre-amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.1.1 Architecture of Pre-amplifier . . . . . . . . . . . . . . . . 638.1.2 Simulation Results of Pre-amplifier . . . . . . . . . . . . . 64

8.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668.2.1 Architecture of Comparator1 . . . . . . . . . . . . . . . . 688.2.2 Simulation Results of Comparator1 . . . . . . . . . . . . . 688.2.3 Architecture of Comparator2 . . . . . . . . . . . . . . . . 718.2.4 Simulation Results of Comparator2 . . . . . . . . . . . . . 72

9 Simulation Results 769.1 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.1.1 FFT Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 789.1.2 Code density Test . . . . . . . . . . . . . . . . . . . . . . 78

9.2 Simulation using Comparator1 . . . . . . . . . . . . . . . . . . . 789.3 Simulation using Comparator2 . . . . . . . . . . . . . . . . . . . 829.4 Simulation using Ideal Pre-amplifier . . . . . . . . . . . . . . . . 87

10 Conclusion and Future Work 9210.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9210.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

A Video Basics Review 93A.1 Video on Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93A.2 Video Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

A.2.1 Video Levels . . . . . . . . . . . . . . . . . . . . . . . . . 95A.3 Video Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 96A.4 Video Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

A.4.1 Television Video Formats . . . . . . . . . . . . . . . . . . 96A.4.2 Computer Video Formats . . . . . . . . . . . . . . . . . . 96

A.5 Video Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98A.5.1 Composite/CVBS Interface . . . . . . . . . . . . . . . . . 98A.5.2 S-video Interface . . . . . . . . . . . . . . . . . . . . . . . 98A.5.3 Component Interface . . . . . . . . . . . . . . . . . . . . . 99A.5.4 Computer Signal Interface . . . . . . . . . . . . . . . . . . 99

7

Chapter 1

Introduction

In this chapter the motivation for the thesis is discussed. The working environ-ment for the project, the objectives and scope of the thesis are explained. Lastlycontents of the thesis work are summarized.Note: It is recommended that reader reads appendix A which contains a briefaccount of video basics, so the discussion in chapter 1 is better understood.

1.1 Motivation

Analog video interfaces are very important parts of digital home and personalentertainment systems. This is due to the fact that they deliver extremely highimage quality with minimal power consumption, still maintaining compatibilitywith most modern and earlier-generation video devices where analog video in-terfaces are the prevalent video interface. Earlier analog video interfaces wereimplemented using external components. To meet the needs of today’s advancedconsumer electronics such as DVD players, digital TVs and set-top boxes, inte-grating high-speed analog interface Intellectual Property (IP) (containing ana-log video interfaces and other multimedia analog and digital interfaces) intoSystems on Chip (SoCs) has become difficult to achieve the desired processingpower and image quality [3].

Currently available video formats can be divided into the following reso-lution categories: standard TV (PAL, NTSC, etc.), HDTV (e.g., 1080p) andwidescreen VGA formats (e.g., 1920x1200) for PC graphics. They demand ab-solutely flawless transmission of color, brightness and synchronism informationover a long cable. To meet this, the video transmitter should be able to trans-mit the video signal reliably and independent of the quality of the transmissioncable. On the other hand the receiver must be able to accurately receive the sig-nal and decode the synchronism information in order to re-create a high-qualityimage [3].

Keeping up with today’s consumer electronic products market trend inte-grating increased functionality into the same digital SoC is the only soundchoice, which further tightens the requirements in terms of power dissipation,form-factor reduction and ability to handle multiple video sources [3].

8

Motivation Introduction

1.1.1 Video Analog Front End IC

The thesis is focused upon Analog to Digital converter (ADC) design for a videoAnalog Front End (AFE) targeting video digitization in handheld devices likemicroprojectors and laptops. The goal is to achieve low power consumptionwith maintained accuracy. The project has the following distinct features.

• High resolution, 12-bit digitizing channel

• Conversion rate as high as 300 MHz

• Usage of reduced power supply as low as 1V

• 65 nm CMOS process

• All digital PLL and DLL

The video AFE project at the Electronics system division at the departmentof Electrical Engineering Linkoping university is unique project following theSCRUM project model. The main project is parsed into different master the-sis works, where all members get together for a weekly meeting, discuss theirprogress and the supervisor delivers tool oriented talks. Information during theweek is mainly shared via email group so all can participate in discussions andlearn. The vision is take the modules all the way to the layout and build a stateof the art video AFE Integrated Circuit (IC) that will be optimized every yearby students and researcher at the division and then eventually taped out.

The detailed block diagram of the video AFE IC is shown in Fig. 1.1.The figure shows that the video AFE consists of two different channels, thetime/reference channel and the digitizing channel.

1.1.2 Time-Reference Channel

The time-reference channel consists of the blocks that generate clock signals,synchronization signals and reference voltage and currents for the rest of thechip. The signals generated in this channel are vital to the chip as the digitiz-ing channel functionality is dependent upon them [4]. The function of blockscontained in the channel are briefly explained below.

Slicer

The slicer detects timing information in the input video signal, it might comefrom the digital domain or an external triggering signal [4].

Multiplexer

The multiplexer selects the correct reference for the current, voltage or timereference [4].

Phase Locked Loop (PLL)

The PLL is designed as an all digital device that aligns its output clock (at ahigher frequency) to the input reference. The PLL output frequency can rangefrom 10 to 300 MHz. The PLL is required to achieve a 50% duty cycle, so thatthe delay chain in the DLL can be implemented with half the number of element[4].

9

Motivation Introduction

Figure 1.1: Block diagram of video Analog Front End IC [4].

Delay Locked Loop (DLL)

The DLL will shift the rising edge of the clock in a controlled manner and willthen produce an output clock which has the same frequency as the input, butwith another phase. It needs to produce a total of 32 equally spaced phases[1, 4].

Oscillator

Oscillator is an ultra low power,RC type wake up-oscillator which maintains astandby mode, unless digitally triggered by some on-screen activity [1, 4].

Bandgap reference

A bandgap reference ensures a supply voltage for all modules that is safe fromProcess-Voltage-Temperature variations [1, 4].

Regulator

The block is responsible for generating voltages required by the chip compo-nents. It will take in supply voltage and generate regulated supply in the rangeof 1-1.2 V and reference voltages for the ADC [1, 4].

10

ADC Specifications Introduction

1.1.3 Digitizing Channel

The digitizing channel is composed of blocks that accept the video signal, processit and digitize it. Digital blocks that are for correction are also a part of thischannel. Some small blocks that generate references for the ADC are also shown.The video AFE IC has five such channels to cover different video standards [1, 4].

Input Multiplexer

The input multiplexer provides an interface with the external world, it shouldhave high linearity around 60 dB and a bandwidth of 500 MHz to meet therequirements of all formats [1, 4].

Clamp circuit

The purpose of the block is DC restoration. This circuit adjusts the clamp levelto the correct brightness of the picture during the back porch or the sync tipsection of the video signal [1, 4].

Anti-Aliasing Filter

This filter acts like a pre-select filter, to remove aliases (images) formed as aresult of Digital to Analog Converter (DAC) and ADC sampling frequency. Theuse anti-aliasing filter results in significant improvement of image quality [1, 4].

Programmable Gain Amplifier (PGA)

Programmable Gain Amplifier takes multiplexed and filtered video signal fromthe mux-clamp block and is referenced from a DAC for Sync-tip compensa-tion. The operational transconductance amplifier designed for the PGA is anovel Cascaded Fully Balanced Pseudo Differential OTA with common modefeedforward and inherent common mode feedback detector.

ADC

The ADC is takes the signal from PGA and digitizes it. The architecture se-lected for the video ADC is Time-Interleaved Successive Approximation Register(TI-SAR) ADC. The ADC is a module that mainly decides the quality of theimage that is quantized, so it is very important for the correct function of thevideo AFE IC. (Details about ADC are discussed in later chapters.)

1.2 ADC Specifications

The ADC for the video AFE needs to meet the specifications, given in Table. 1.1.The requirements of the sub modules within the ADC will be dictated by

these requirements.

1.3 Objectives

The objectives of this thesis work are as follow:

11

Thesis Organization Introduction

Table 1.1: Video ADC specification (modified from [2]).Item Value Unit

Resolution 12 bitsSample Frequency 270 to 330 MHzVideo Bandwidth 6 30 MHzCircuit Bandwidth 500 MHz

SNDR 74 dBInput Range 0.8 to 1.2 Vpp

Supply Voltage (VDD) 1 to 2.5 VLatency 6 20 Clock

cyclesPower Consumption 6 30 mA

• Select a suitable ADC architecture for a video application, which is lowpower, area efficient, scalable with technology, has maintained accuracyand also supports high sampling rates.

• Develop a mathematical model of the selected architecture, modelling er-ror sources, studying their effect on system performance.

• Develop a fully functional behavioral model of the selected ADC,usingVerilog-ams blocks.

• Design a schematic level circuit of the comparator of ADC, study behaviorand verify it meets the specifications.

• Create layout of the comparator used in the ADC.

The thesis report reflects how various goals are achieved and also interpretsthe simulation results obtained.

1.4 Thesis Organization

The thesis report is organized into various chapters. A brief summary of thecontents of the each chapter is provided in this section. Chapter 2, reviews thefundamentals of Analog to Digital conversion, also touching upon the static anddynamic performance metrics of ADCs. Chapter 3 provides brief explanationof the contemporary ADC architectures and gives a comparison of the archi-tectures to motivate the selection of a suitable ADC for the AFE. Chapter 4contains a detail discussion about of SAR ADC. Chapter 5 discusses conciselythe mathematically formulation of ADC and errors modelling of error that arecharacteristic of video and TI-ADCs. Results are used to draw some conclusions.Chapter 6 focuses mainly on the development of a behavioral top level model ofTI-ADC and the timing scheme which is very essential for its proper operation.Results are used to draw appropriate conclusions. Chapter 7 is composed ofcomparator performance metrics, types and some issues of concern while de-signing comparators. Chapter 8 mainly deals with the implementation of thecomparator for the ADC. Chapter 9 presents the simulation setup and discussesthe obtained results. Chapter 10 concludes the thesis work and discusses thefuture prospects. Appendix A provides a brief review of video basics.

12

Chapter 2

ADC Fundamentals andPerformance Metrics

In this chapter the fundamentals and characterization of Analog to Digital Con-verters are presented.

2.1 Analog to Digital Converter (ADC)

An ADC is a device that takes an analog input and outputs digital codes sinceit has both analog and digital functions, it is a mixed-signal device. An ADChas an analog reference voltage against which the analog input is compared.The input signal varies between 0 and Full Scale (FS), and it is converted to adigital word of N-bits. The digital output word signifies what fraction of thereference voltage is the input voltage [5].

2.1.1 Resolution

The resolution of an ADC is the distinct analog levels that can be representedby the binary word. for an ideal N-bit ADC there are 2N analog levels ad thusthe resolution is said to be N-bit. The smallest step that can be discriminatedby an N-bit ADC is VLSB = VFS/2N , where VFS represents the full scale rangeof the converter [6]. The size of the LSB compared to the total code range issometimes also referred to as resolution of the converter so for an N-bit ADC,thus resolution would be 1/2N .

2.1.2 Quantization Error

The quantization error is introduced due to quantization of an analog (continu-ous) signal to set of discrete values. For ideal ADC it is VLSB/2. It is modelledas white noise that is uncorrelated to the signal, which is a good estimationfor large number of quantization levels [6]. Considering the error as white noisehaving equal probability lying in the range of ±VLSB/2 the resulting noise poweris given in an equation below.

Pquantization noise = V 2LSB/12 (2.1)

13

Static Performance Metrics ADC Fundamentals and Performance Metrics

Figure 2.1: Ideal ADC characteristic [8]. Copied from Analog-to-Digital Con-verters Testing by Kent. H. Lundsberg 2002.

Figure 2.2: Quantization error for an ideal ADC [8]. Copied from Analog-to-Digital Converters Testing by Kent. H. Lundsberg 2002.

2.2 Static Performance Metrics

Static errors are deviation of the converter from the ideal characteristics, theydepend only upon the input signal that is being converted. The measures ofstatic performance of an ADC are explained below.

14

Static Performance Metrics ADC Fundamentals and Performance Metrics

2.2.1 Offset Error

Offset error is the deviation in the ADC’s behavior at zero. The first transitionvoltage should be 1/2 LSB above analog ground. Offset error is the deviationof the actual transition voltage from the ideal 1/2 LSB. Offset error can consid-erably reduced by calibration [8]. Fig. 2.3 clearly shows what effect offset errorhas on the ideal ADC characteristic. (Compare Fig. 2.1 and 2.3.)

2.2.2 Gain Error

Gain error is the deviation in the slope of the line through the ADC’s end pointsat zero and full scale from the ideal slope of 2N/VFS codes-per-volt. The gainerror is easily corrected by calibration [8]. Fig. 2.3 illustrates how the slope ofthe ideal ADC characteristic changes due to Gain error. (Compare Fig. 2.1 and2.3.)

Figure 2.3: Offset and gain errors in ADC [8]. Copied from Analog-to-DigitalConverters Testing by Kent. H. Lundsberg 2002

2.2.3 Differential Non-Linearity (DNL)

DNL is the deviation of the code transition widths from the ideal width of 1LSB. For an ideal ADC, DNL is zero everywhere [8].

2.2.4 Integral Non-Linearity (INL)

INL is the distance of the code centers in the ADC characteristic from the idealline. If all code centers land on the ideal line, the INL is zero everywhere [8].

15

Dynamic Performance Metrics ADC Fundamentals and Performance Metrics

Mathematically INL is best expressed as the sum of DNL for each code [7].

INLi =k∑

i+=1

DNLi (2.2)

It important to mention here that in applications offset and gain errors areacceptable INL is specified with respect to a best fit line rather than the idealtransfer characteristic.

2.2.5 Missing codes

Missing codes term corresponds to the output digital codes that are not pro-duced for any input voltage, mainly due to large DNL [8]. Wide codes occur asa result of positive DNL while negative DNL results in narrow codes. Fig. 2.4illustrates narrow, wide and missing codes in an ADC.

Figure 2.4: Non-linear errors in ADC [8]. Copied from Analog-to-Digital Con-verters Testing by Kent. H. Lundsberg 2002

2.3 Dynamic Performance Metrics

Dynamic performance is judged by applying single or sometimes multitone sinu-soidal input signal and observing the response, important measures are discussedbelow.

16


2.3.1 Signal to Noise Ratio (SNR)

The SNR is the ratio of power of the input signal to the sum of total noisepower, within in a certain frequency band. It is expressed in decibels.

SNR = 10 · log10

[Psignal

Pnoise

](2.3)

where Psignal is the power of the signal

Psignal =

(VLSB · 2N−1

)2

2(2.4)

where VLSB · 2N−1 is the maximal amplitude of the sinusoidal input. Pnoise

refers to the sum of thermal noise and quantization noise power in the band ofinterest. putting the value in relation 2.3 from equation 2.4 and equation 2.1

SNR = 10 · log10

(VLSB ·2N−1)2

2V 2

LSB

12

SNR = 10 · log10

[1.5 · 22N

]

SNR = 6.02N + 1.76 (2.5)

Equation 2.5 presents a linear relation between N i.e., the number of bits andSNR.

2.3.2 Spurious Free Dynamic range (SFDR)

The SFDR is defined as the ratio of the power of the signal to the largestspurious that is the distortion tone within the band of interest.

SFDR = 10log10

[Psignal

Pspurious

](2.6)

2.3.3 Total Harmonic Distortion (THD)

The THD is the ratio of the total power of harmonic components to the inputsignal power [8] and [7].

THD =P2 + P3 + P4 + P5 + P6 · · ·+ Pn

Psignal(2.7)

where Psignal is the power of the fundamental tone that is the signal, and Pn

is the power of the nth harmonic. As the number of harmonic distortions areinfinite, calculation is restricted to 10− 20 harmonics, also the power of higherorder harmonics is almost negligible.

17


2.3.4 Signal to Noise and Distortion Ratio (SNDR)

The SNDR is the ratio of power of the input signal to the sum of noise anddistortion power, within in a certain frequency band. It is expressed in decibels.

SNDR = 10 · log10

[Psignal

Pnoise + Pdistortion

](2.8)

where Psignal is the power of the signal, Pnoise refers to the sum of thermalnoise and quantization noise power and Pdistortion, represents the power of theharmonics lying inside the band of interest. It is noteworthy that SNDR isdependent on the input signal frequency and amplitude, degrading at high fre-quency and power.

2.3.5 Effective Number Of Bits (ENOB)

ENOB is simply the signal-to-noise-and-distortion ratio expressed in bits ratherthan decibels by employing the ideal SNR equation.

ENOB =SNDR− 1.76

6.02(2.9)

It is one of the important performance metrics for ADC characterization.

2.3.6 Dynamic Range (DR)

Dynamic range is the ratio between the FS signal to the smallest detectablesignal [7].

DR = 10 · log10

(Pmax

Pmin

)(2.10)

where Pmax is the maximum power for full scale input signal and Pmin corre-sponding to the minimum noise power.

2.3.7 Effective Resolution Bandwidth (ERB)

ERB refers to the input-signal frequency where the SNDR of the ADC has fallenby 3 dB (0.5 bit) from its value for low-frequency input signals [8].

18

Chapter 3

ADC Architectures

This chapter briefly reviews the contemporary ADC architectures in terms ofspeed, resolution, accuracy and applications. Also functionality of each archi-tecture is briefly discussed. The chapter concludes with concise comparison ofADCs to firmly establish the argument behind selection of the proposed architec-ture.

3.1 Flash ADC

Flash ADC are also known as parallel ADC, as the analog to digital conver-sion is done for N-bits in parallel. Flash ADC are have a high conversion ratemaking them suitable for high speed devices. They are suitable for applicationsrequiring very large bandwidth. The downside of this architecture is the hugepower consumption which grows drastically with the increase of resolution ofthe converter, thus making it a good choice only for low resolution (up till 8bits) applications. This is a major problem as low power applications requiringhigh speed and accuracy cannot make use of flash ADC. Flash ADC are suitablefor application like data acquisition, satellite communication, radar processing,sampling oscilloscopes, and high-density disk drives [9].

3.1.1 Functionality of Flash ADC

Fig. 3.1 shows a typical block diagram of flash ADC, for an N-bit converter thearchitecture requires 2N − 1 comparators. A resistor ladder circuit consisting of2N resistors, is used to generate distinct reference voltages for the comparators.The reference voltage of each comparator is 1 LSB less than the one precedingit. The comparator performs comparison between the analog input and thereference value if the input is greater it outputs a “1” else a “0”. Consideringan input lying between Vx3 and Vx4, so the comparators X1 to X3 will producea “1” while the rest will output a “0”. Note that the converter outputs thewhole N-bit digital code corresponding to the analog input in parallel [9].

19

Pipelined ADC ADC Architectures

Figure 3.1: Block diagram of Flash ADC [9].

3.2 Pipelined ADC

The pipelined ADC architecture as the name reflects employs the pipelined ap-proach for analog to digital conversion, using m-bit identical stages to achieveN-bit conversion. It provides sample rates up to a few hundred Mega sam-ples and resolution up till 16-bits. Reasonably high speed and resolution withcomparatively low power consumption and good dynamic performance makeit desirable choice for a wide range of applications like Charge Coupled Device(CCD) imaging, ultrasonic medical imaging, digital receivers, base stations, dig-ital video, xDSL, cable modems, and fast Ethernet [10].

3.2.1 Functionality of Pipelined ADC

The architectural block diagram of a pipelined ADC is shown in Fig. 3.2. Itconsists of four identical stages of 3-bits (which resolve to 2-bits) and 4-bit flashADC for the last four bits. The input is vin is held then provided to first stagethat utilizes a 3-bit ADC to convert it into a digital code, which is then fedto a 3-bit DAC which converts it to corresponding voltage level. The vin issampled and then the output of DAC is subtracted from it, which generates theresidue error. As each stage outputs k = 3 raw bits, the residues is amplifiedby a factor of 2k−1 = 22 = 4 before it is sent to the next stage. This gained-

20

Sigma Delta ADC ADC Architectures

up residue continues through the pipeline, providing three bits (raw) per stageuntil it reaches the 4-bit flash ADC, which resolves the last four LSBs. Bitscorresponding to the same sample are time-aligned with shift registers beforebeing fed to the digital-error-correction logic because the bits are computed atdifferent time points in different stages. When a stage finishes processing asample it can move to the next sample received from the internal sample andhold, this pipeline action is the reason behind high throughput [10].

Figure 3.2: Block diagram of Pipelined ADC (12-bit ADC with four 3bit stagesand a 4bit flash ADC) [10].

3.3 Sigma Delta ADC

The Sigma-Delta ADC, consisting of a relatively simple analog side and rathercomplex digital side consisting of filtering and decimation is inexpensive to de-sign. It provides high resolutionand integration at reduced cost. It has a limita-tion that is has a trade-off between speed and resolution. Suitable for applicationthat require high resolution at low bandwidth, like some audio applications.

3.3.1 Functionality of Sigma Delta ADC

This architecture requires that the input signal should be oversampled such thatOSR = fsignal/2 ·fsample, oversampling has the benefit that it spreads the noiseover a larger bandwidth that is OSR · fsample thus decreasing the average noisefloor which increases the SNR and the ENOB also increases. The block diagramof a sigma-delta modulator of the first order Fig. 3.3. It includes a differenceamplifier, an integrator, and a comparator with feedback loop that contains a1-bit DAC. The DAC acts like a switch that connects the negative input of thedifference amplifier to a positive or a negative reference voltage. DAC servesas the purpose of maintaining the average output of the integrator near thecomparator’s reference level. For increasing input the comparator generatesmore “1” than “0” and for decreasing signal its the opposite. By summing theerror voltage, the integrator behaves like a lowpass filter for the input signaland a highpass filter for the quantization noise. Thus oversampling and noise

21

Successive Approximation Register (SAR) ADC ADC Architectures

shaping change the noise power distribution pushing the quantization noise intohigher frequencies and reducing noise floor. In the digital domain the ADCoutput is filtered by a digital filter that has a positive effect on the SNR [11].

Figure 3.3: Block diagram of Sigma Delta ADC (1-bit ADC) [11].

3.4 Successive Approximation Register (SAR)ADC

SAR ADC provide medium resolution at a couple of mega samples speed (below100) at low power consumption and low cost. IT is well suited for applications,such as portable/batterypowered instruments, pen digitizers, industrial controls,and data/signal acquisition [12].

3.4.1 Functionality of SAR ADC

The Fig. 3.4 shows the architectural block diagram of the ADC. The analoginput voltage vin is held using a track/hold. SAR ADC uses binary searchalgorithm, thus N-bit SA register is first set to the middle value i.e., 100 · · · 00,where the Most Significant Bit (MSB) is set to“1”. This results in the DACoutput VDAC to be VREF

2 , where VREF is the reference voltage provided tothe ADC. The comparator then compares vin and VDAC , if vin = VDAC , thecomparator outputs a“1” and the MSB of the SA Register remains at “1”,otherwise comparator outputs a“0” and MSB is cleared to “0” . The SARcontrol logic then moves to the next bit down, forces that bit high, and doesanother comparison. The procedure continues in similar fashion down to theLSB. After this the conversion is complete, and the N-bit digital word is availablein the register [12].

3.5 Comparison of the ADC Architectures

Comparison of the ADC architectures in terms of performance and functionalityneeds to be done so that decision regarding a suitable ADC architecture for theAnalog videofront end can be made.

22

Selecting the Architecture and Why? ADC Architectures

Figure 3.4: Block diagram of SAR ADC [12]

Table 3.1: Comparison of ADC architectures modified from [13].Architecture Speed Conversion

TimeResolution Area Power

Flash ADC High Constant Low (up till8-bits)

Increasesexponen-tially withresolution

Veryhigh

PipelinedADC

medium-high

Increaseswith resolu-tion

medium-high (up till12-bits)

Increaseslinearly withresolution

medium

Sigma-Delta ADC

medium Trade-offwith resolu-tion

High (up till24-bits)

constant;nochange withincrease inresolution

medium-low

SAR ADC medium-low

Increaseswith resolu-tion

High (up till18-bits)

Increaseslinearly withresolution

medium-low

3.6 Selecting the Architecture and Why?

SAR ADC is most suitable for the analog video front end, as it has low powerconsumption, reasonable resolution and accuracy. The architecture has to bemore “digital” rather than “analog”, as the system design should be “scalable”that is it scales with technology, and digital is scalable. SAR ADC meets thisrequirement, as the comparator is the sole “analog” component in this design,the rest of the modules shrink as the design is implemented in contemporarytechnologies (low). Due to the digital nature reduced power supply can be usedresulting in further power reduction. The sampling speed required is very highand SAR ADC cannot meet that specification but using the Time-Interleavedapproach several low power SAR-ADCs can be placed in parallel to achieve asampling rate around 300M samples/s.

23

Chapter 4

Successive ApproximationRegister (SAR) ADC

This chapter contains a detailed theoretical review of the SAR ADC. Startingwith the explanation of the conversion algorithm employed, the functionality ofthe components of the SAR ADC is discused. Finally the Time-Interleaved ADCis defined and the merits and demerits of the approach are briefly discussed.

4.1 The Successive Approximation (SA) Algo-rithm

The SAR architecture converts the analog input signal level to correspondingN-bit code by using the Successive Approximation algorithmic approach. Inother words the SAR ADC employs the binary search Algorithm to successiveapproximate to the correct digital code. One bit is obtained per clock cycle.

Figure 4.1: SAR operation [12].

In order to better understand the working consider an example of a 4-bitADC as shown in Fig. 4.1. Intially VDAC is set to VREF /2 i. e 10002 and thencompared with the input Vin whose held value is assumed to be below VREF /2,

24

SAR ADC Submodules Successive Approximation Register (SAR) ADC

so the comparison Vin = VDAC is false so the bit3 is cleared to “ 0 ”. Next theDAC is set to 01002 that is, VREF /4 so we are in the lower half now we will befinding the correct value below the VREF /2 as the first bit was “ 0 ” and thesecond comparison is complete, now as Vin > VDAC , bit is set. After this DACis set to 01102 ,now as Vin < VDAC , bit is cleared. Finally for the fourth bitDAC is initialized to 01012 and the comparison is not true again so bit0 is “ 0”. For a 4-bit ADC, one cycle for sampling the input and four cycles are usedfor comparison. At the end of 5 cycles the digital code in the SAR is 01002.

4.2 SAR ADC Submodules

A typical SAR ADC architecture consists of the following submodules whichare shown in Fig. 4.2:

• Sample and Hold

• Digital to Analog Converter (DAC)

• Comparator

• Successive Approximation Register (SAR)

Figure 4.2: Block diagram showing submodules of Successive ApproximationRegister ADC [12].

4.2.1 Sample and Hold

Sample and hold is actually a misnomer, it tracks an input signal and then holdsit, so track and hold is what it actually does. It consists of a sampling switchand a sampling capacitor, at every rising edge of the sample signal it tracksthe input for half cycle and then holds the value for the next half of the cycle.The benefit we achieve by having the input held before comparison is that thecomparator gets a stable value at its input, which yields correct result of thecomparison.

25

Time-Interleaved SAR ADC Successive Approximation Register (SAR) ADC

4.2.2 Digital to Analog Converter (DAC)

As the name indicates it is a mixed signal device for performing the reverseoperation of that of an ADC. It is used for converting digital bits to a corre-sponding analog value. In the SAR ADC the DAC is present in a sort of a loop,it takes the digital bits in the Successive Approximation Register (SAR) andconverts them to the appropriate signal level and provides it to the input of thecomparator to compare with the held input. Popular DAC architectures areR-2R ladder DAC ( consisting of resistors) and a C-2C ladder DAC (consistingof capacitors). As the later architecture relies on ratio of capacitors, bettermatching can be achieved in this way. In contemporary SAR ADCs sometimesa capacitive DAC with an inherent Sample and Hold is used, which is known asa charge re-distribution DAC. It has the benefit of being low power

4.2.3 Comparator

This is the heart of the ADC doing the actual conversion from Analog to digital,as it compares the two analog signals at its input and generates a digital output a“1” or a “0”. The comparator used in SAR ADC is usually a clocked comparator,which compares the held input with the DAC output and yields and outputthat sets a bit in the SAR, and this procedure continues till the LSB For thisparticular ADC, the comparator needs to be fast enough to yield the correctoutput within a clock cycle. Also as the resolution of the ADC is 12-bit, thecomparator needs to be robust enough to differentiate between very small values.(Details about comparator design are covered in Chapter 8 )

4.2.4 Successive Approximation Register (SAR)

This is the part from which the architecture gets its name “Successive Approxi-mation Register”. The register contains N-bits, where N is the resolution of theADC. Each bit can be accessed independently and can be set to “1”, clearedto “0” or retain its value. Intially MSB of the register is set and converted toanalog value by DAC, compared with input by the comparator if the input ishigher than it MSB remains “1” otherwise it is cleared and same is repeated forthe next bit, all the way down to the LSB. At the end of N+1 cycles the SARADC contains the correct digital code corresponding to the input.

4.3 Time-Interleaved SAR ADC

SAR ADC is the selected architecture based upon the facts that it has a scalablearchitecture, burns less power and provides reasonable accuracy but at the sametime for the video AFE the required sample rate is 300 MHz which is a lot morethan typical SAR ADC can provide, so we adopt time-interleaving to achievethis high speed.

Time-Interleaving is a smart technique to achieve an overall high samplerate by operating low sample rate ADCs in parallel. Thus to achieve an overallsample rate of say FClk we can use M ADCs having a sample rate of FClk/Meach, so the speed requirement for ADCs is relaxed by a factor of M at thesame time increasing the number of comparators by M . Luckily the area and

26

Time-Interleaved SAR ADC Successive Approximation Register (SAR) ADC

power consumption don’t necessarily scale by a factor of M as there are somemodules that can be shared among the M-channels.

Mathematically FClk =∑n=M

n=1 FClk−ADC(n)where FClk−ADC(n) is the rate of one of the ADCs.The concept time-interleaved is illustrated in the Fig. 4.3 given below. The

input signal vin is fed to all the channels at the same time as the the Sample andHold units of each channel work at FClk/M and for each channel the sampleinstant is different, M consecutive samples of input signal are picked up by theTime-interleaved ADC, to speed up the conversion process M times. The resultis digitally multiplexed to provide the digital bits.

Figure 4.3: Block diagram of Time-Interleaved ADC.

As good as it sounds time-interleaved ADC is not perfect, its performance islimited by the accuracy of the channel ADCs and also the mismatch between thechannels gives rise to gain errors, offset errors and skew errors. Thus the factorM used for interleaving is also limited by the occurrence of these characteristicerrors, which can adversely affect the system performance.

27

Chapter 5

Mathematical Model ofTime-Interleaved SARADC

The chapter consists of discussion regarding development of a mathematicalmodel of the TI-SAR ADC. The errors modelling in the tool and effects onthe system performance are also observed.

5.1 Introduction and purpose

In order to develop an understanding of the functionality of the ADC, a proto-type in MATLAB is developed. Top-level modelling has the benefit of makingthe designer identify the inputs and outputs of the system, keeping the im-plementation details aside. A mathematical model is helpful in making onevisualize signal as matrices and translate input into output using mathematicalequations. A code for an ideal N-bit SAR ADC was written which functionallymodelled the behavior of SAR ADC. The model is flexible and allows the userto choose sample frequencyFsample, signal frequencyFsignal, number of channelsor slices of the TI-SAR ADC M and the resolution of the ADC N . Firstly thebehavior of the model was observed such that it complies with what we need,next only those errors were modelled that would be difficult to emulate usingthe Cadence environment. The model can be best explained with the help ofa pictorial representation shown in Fig. 5.1.

The model has a coherent sampling unit that ensures that, the input fre-quency is changed such that the criteria for coherent sampling , given below aremet.

• There should be integer number of sinusoid cycles in a record.

• The Number of Cycles (NoC) and Number of Samples (NoS) in a recordshould have no common factor.

Meeting these conditions guarantees that the samples are distributed uni-formly over 0−2π, in phase. If this is not done, one potential disadvantage is thespectral Leakage, such that the output spectrum acquires a skirt and tends to

28

Introduction and purpose Mathematical Model of Time-Interleaved SAR ADC

Figure 5.1: Block diagram of MATLAB Model of Time-Interleaved ADC.

leak into neighboring channels. For this model NoS = 216, Fsample = 300MHz,Fsignal = 30MHz

The NoC is computed using the relation

NoC =Fsignal

Fsample·NoS (5.1)

Next look for a prime of NoS that is very close to the computed NoC and thenfinally substitute in the relation below to compute the new Fsignal

Fsignal =NoC

NoS· Fsample (5.2)

The input signal is generated consisting of NoS points, it is a 1-dimensionalmatrix [1 × NoS]. The errors are added to the input signal one at a time tostudy their impact closely. Next the input needs to split up into M separatechannels. The input is reshaped into a matrix having dimension [M ×L] whereL = NoS/M as for this case M is a multiple of NoS. Each mth row correspondsto the signal provided to the mth ADC, where m = 1 · · ·M . The SAR conversioncode is run M times. This code takes input row by row and also N the numberof bits. The output is then merged back from M-channels to one output. Deltasignal is plotted, to study how the output differs from input. The SNDR iscomputed, from the output signal. The output of the MATLAB model at thispoint demonstrates the normal behavior (in the absence of any sort of error).

29


Figure 5.2: Input signal (spectrum and time domain graph).

Figure 5.3: Channel input signals (time domain graph).

Fig. 5.2, 5.3 and 5.4 show the signal that is provided at the input of thesystem, the channel inputs and the output of the system respectively.

30


Figure 5.4: Output signal (spectrum and time domain graph).

31

Modelling Errors Mathematical Model of Time-Interleaved SAR ADC

5.2 Modelling Errors

The first three errors that are discussed in upcoming sections are characteristicof a TI ADC, the later two are more relevant to video ADCs.

5.2.1 Gain Error

The parallel ADCs may be different and that can result in different channel gainswhich in turn cause distortion in the output signal. To model this behaviorits suitable to consider it as a random process. If the gain in channel m isam, considering it as normally distributed random variables with mean a andvariance σ2

a the SNDR of the TI ADC, having M channels can be approximatedas shown in 5.3.

SNDR = 20 · log10

(a

σa

)− 10 · log10

(1− 1

M

)(5.3)

Equation 5.3 shows that the number of channels will only affect the SNDRonly by 3 dB as M increases from 2 to infinity, so M has very less impact onSNDR. While the first term indicates that the value of σa should be very smallto allow a large value of SNDR, for a 12-bit ADC it is approximately 0. 0199%.This is very difficult to achieve so little higher σa is allowed in the design andsome digital correction are made later [7].

Figure 5.5: Output spectrum with gain errors σa = 0.1.

The distortion tones that result due to gain errors are signal dependent theyare located at Fsignal + m · Fsample/M, m = 1 · · ·M − 1. The tones can be seenclearly in Fig. 5.5.

5.2.2 Offset Error

The offset in the different channels can result in corruption of the output signal.Each channel may suffer from different offset and this is best modelled as arandom process. If the offset in a certain channel m is om, considering it as

32


random variables having a normal distribution with mean zero and variance σ2o ,

then the SNDR in this case is given by the relation given in equation 5.4.

SNDR = 20 · log10

(1σo

)(5.4)

The expression above indicates that to achieve an SNDR of 74dB for a 12-bitADC, the value of σo needs to be as low as 0.04% . This is obviously unrealisticto achieve so a little margin is given in the design and σo is allowed slightlyhigher such that it can be corrected in digital domain [7].

Figure 5.6: Output spectrum with offset errors σo = 0.1.

The distortion tones that result due to offset errors are signal independentthey are located at m · Fsample/M,m = 1 · · ·M − 1. The tones can be seenclearly in Fig. 5.6.

5.2.3 Channel Jitter

The time interleaved ADC structure has the parallel ADCs typically workingupon different subsequent shifts of the original clock. This error occurs as re-sult of the time differences between the channels due to mismatches. The mis-matches in the clock generator MOS transistor and different capacitive load seenby different outputs, can yield certain phase jitter. Even if they are matched, VThreshold mismatch in sampling switches can also result in phase skew. Re-garding the errors as normally distributed random variables with zero mean andσ2

t , the SNDR can be approximated as shown in 5.5.

SNDR = 20 · log10

(1

σt · 2π · Fsignal

)− 10 · log10

(M − 1

M

)(5.5)

The number of channels in a TI ADC have very less impact on the total SNDRas M goes from 2 to infinity. The value of σt should be around 1 ps, in order

33


to get 12-bit resolution at 30 MHz input frequency. This is some what diffi-cult to achieve in a CMOS process. The distortion tones lie at Fsignal + m ·Fsample/M,m = 1 · · ·M − 1, similar to the gain error spurs [7].

Figure 5.7: Output spectrum with channel jitter σt = 10ps.

5.2.4 Long Term Jitter (LTJ)

Long term jitter is a characteristic error associated with video ADCs, its dueto jitter caused by the HSYNC frequency present in the video application. Itis also referred to as drift jitter due to its slowly changing nature. The allowedvalue for our system is 8%/FSample which approximately 267 ps. Simulationresults show that this error does not have an immense adverse impact on thesystem performance.

5.2.5 Cycle to cycle Jitter (Random Jitter)

The cycle to cycle jitter (random jitter) is due to the jitter in the originalclock generated by the DLL, and as the clock phases upon which each of the mchannels operate are derived from the system clock, if it is jitter prone, all thephases will inherit it.

The performance of the time interleaved ADC is severely affected by therandom jitter, because due to the uncertainty of time at which input is sampled,the converted digital code can be erroneous, thus resulting in a poor quality ofvideo.

Fig. 5.8 indicates that the significant rise in noise floor with introduction ofrandom jitter as compared to Fig. 5.5 and Fig. 5.6.

34


Figure 5.8: Output spectrum with cycle to cycle jitter σc2c = 0.1ns.

35

Identifying the killer ... Mathematical Model of Time-Interleaved SAR ADC

5.3 Identifying the killer ...

In the quest to identify the killer of the TI-SAR ADC, the SNDR is used asa measure to gage the effect of the errors on the system performance. Alsothe delta signal is used determine how much the output deviates from what itshould be due to a certain error. The model was simulated for different values ofthe errors modelled above, each time the SNDR was measured. The simulationresults are tabulated in Table. 5.1. (SNDR graphs for the errors are given inthe previous section)

Table 5.1: SNDR in the presence of errors.Error SNDRNone 74 dB

Gain Error 54 dBOffset Error 53 dB

Channel Jitter 52 dBLong Term Jitter 73 dB

Cycle-to-Cycle Jitter 34 dB

The effect of the errors can also be seen by observing the difference betweenthe input and output.

Figure 5.9: Delta signal in absence of error (spectrum and time domain graph).

36


Figure 5.10: Delta signal in the presence of gain error (spectrum and time do-main graph).

Figure 5.11: Delta signal in the presence of offset error (spectrum and timedomain graph).

37


Figure 5.12: Delta signal in the presence of channel jitter (spectrum and timedomain graph).

Figure 5.13: Delta signal in the presence of long-term/drift jitter (spectrum andtime domain graph).

38

Demonstration of Errors Mathematical Model of Time-Interleaved SAR ADC

Figure 5.14: Delta signal in the presence of cycle-to-cycle jitter (spectrum andtime domain graph).

Fig. 5.9, 5.10, 5.11, 5.12 and 5.13 show delta signal in the presence of noerror, gain error, offset error, channel jitter and long-term jitter respectively.Fig. 5.9 shows that the difference between input and output is very negligible.The Delta signal shown in Fig. 5.10,has a significant value and also forms adistinct noticeable pattern. The Delta signal shown in Fig. 5.11, has a lesservalue than in Fig. 5.10. The Delta signal in Fig. 5.12 has a significant value andalso repeats in a unique pattern. The Delta signal in Fig. 5.13 has a very smallvalue.

The observation of the spectrum of the delta signal from the point there isno error and then comparing it with the spectrum after introduction of errors.This helps to identify the error that affects the system the most. The deltasignal for gain and channel jitter occurs in a visible pattern. Also it is noticedthat amplitude of the delta signal in time domain is largest for cycle-to-cyclejitter. The simulation results conclude that the cycle to cycle jitter is the worstenemy for our system. It is good to mention here again that this due to theDLL that generates the system clock and the ADC module only inherits thetroubles.

5.4 Demonstration of Errors

The errors modelled above can affect the video adversely by creating artifactsthat degrade the image quality. In order to demonstrate how video will bedegraded by these errors, a standard frame of testing of display is used anderrors are added to see the effects.

Lastly it is important to investigate the effect of level of quantization on thequality.

39


Figure 5.15: Standard frame for video display testing.

Figure 5.16: Effect of addition of Additive White Gaussian Noise (AWGN) onframe.

40


Figure 5.17: Effect of offset error on frame.

Figure 5.18: Effect of gain error on frame.

41


Figure 5.19: Effect of distortions on frame.

42


Figure 5.20: Effect of fine quantization (12-bit) on frame.

Figure 5.21: Effect of intermediate level of quantization (8-bit) on frame.

43

Error Reduction TechniquesMathematical Model of Time-Interleaved SAR ADC

Figure 5.22: Effect of coarse quantization (1-bit) on frame.

Fig. 5.16 shows that addition of Additive White Gaussian Noise (AWGN)can significantly reduced the quality of the video frame. Fig. 5.17 shows how theoffset errors can visibly distort the image. A pattern of vertical lines is visible onthe screen which is dependent upon the number of ADC channels (slices) usedin the time interleaved structure. Fig. 5.18 shows how the gain errors can affectthe image. A pattern of lines is visible on the screen which is dependent uponthe number of ADC channels (slices) used in the time interleaved structure.Fig. 5.19 demonstrates the effect of distortion on the image, so if distortionsare present the picture looks like Fig. 5.19 instead of Fig. 5.15. ComparingFig. 5.15 and 5.20 there is not any noticeable difference, even Fig. 5.21 doesn’tshow much degradation but Fig. 5.22 shows a drastic effect on the picture. Soif due to some issues the ADC has a reduction in SNDR and its ENOB dropsthere can be a noticeable effect on image quality.

5.5 Error Reduction Techniques

Over the course of years several effective techniques have been developed tocounter the channel mismatches that limit the performance of time interleavedADCs. A few of these techniques are discussed below.

5.5.1 Two-Rank Sample and Hold

This is mainly focused on the elimination of the timing mismatch, the channeljitter as mentioned earlier and has no effect on other errors (gain and offset).The idea is to insert a sample and Hold (S/H) at the input, before the input isgiven to the channels, this removes the phase skew but the obvious disadvantage

44

Error Reduction TechniquesMathematical Model of Time-Interleaved SAR ADC

is the operation of the S/H at the maximum sample rate, as it is cumbersometo design S/H at high speed in CMOS technology [7].

5.5.2 Randomization

This technique is focused on reduction of gain and offset and has little effect onthe timing errors. If the channel to convert the next sample is randomly chosenas opposed to the sequential way the correlation between the input signal andchannel errors is reduced [7]. In [14] it is discussed how randomization can bedone at the cost of introduction of additional ADCs and randomly selecting anADC at each sample instance. The results in [14] show that it can remove theperiodicity of errors, thus transformation the spurious distortions to more noiselike distortion that is spread uniformly over the whole spectrum. The demeritof the scheme is that all the ADCs must operate at the system clock signal, asthe decision regarding which channel samples next is done dynamically, so thebenefit of the TI-SAR is almost lost. Also a potential issue is the design com-plexity of the switches that make this randomization possible,which increaseswith the number of channels.

45

Chapter 6

Behavioral Model ofTI-SAR ADC

This chapter briefly explains the behavioral model of the TI-SAR ADC alsolooking at its purpose. Next the sub-modules are discussed briefly. An efficienttiming scheme for TI-SAR is discussed. The simulation results are provided inthe end.

6.1 Introduction and Purpose

The behavioral model of the ADC is developed in CadenceTool, the purpose ofthis model is to develop an understanding of the architecture of the sub SARADC and then designing the TI-SAR ADC structure.

To understand the behavior of sub modules of the SAR ADC their behavioralmodels were developed using Verilog-ams which is a Language for descriptionof analog and mixed signal blocks that modelled their functionality. The be-havioral modelling of a system usually employs the top down approach, intiallyvisualizing the internal design details as a black box, focussing on the generalbehavior. The TI-SAR ADC is made of 16 parallel SAR ADCs so a mixedapproach was employed, sometimes the bottom up approach was used diggingin the design of the parts of a SAR ADC to build a complete SAR ADC, andsometimes the top down approach was used to design the TI-SAR ADC.

The benefit of this model is that, designer gets to understand the functionof all sub-blocks and how they are put together to build the final block. Asthe model is built using Verilog-ams, one gets to concentrate on how to get thebehavior modelled, setting the hardware (transistor-level) design issues aside.Another merit is that it is fast to design and changes can be made easily, whichmakes it easy to incorporate new ideas to the model. The design consists of sub-blocks model in Verilog-ams, so once a module is implemented at transistor-level,it can be replaced in the behavioral model of the TI-SAR ADC so that, one canassess how well the implemented block works.

46

SAR ADC Behavioral Model of TI-SAR ADC

6.2 SAR ADC

The SAR ADC is composed of track and hold, Digital to Analog Converter(DAC), comparator and Successive Approximation Register (SAR). The SARADC overall functionality as well of its sub-modules has been discussed in Chap-ter 4 in detail. The behavioral model of a SAR ADC is developed by first cre-ating functional models of sub-blocks and then connecting them in accordancewith the architecture. The sub-modules are briefly discussed in the followingsubsections.

6.2.1 Sample/Track and Hold (S/H or T/H)

The single-ended T/H is implemented as Verilog-ams block that tracks the inputsignal or one clock cycle and then holds the value for N-cycles, where N is theresolution of the ADC. The Samplesignal is N+1 times lower then the clockfrequency of the system. The value of input is picked up at the rising edge ofthe Samplesignal signal and held for the next N-cycles. The differential T/His obtained by putting two T/H in parallel working on the same Samplesignal,taking in differential signals and producing differential output.

6.2.2 Digital to Analog Converter (DAC)

The single-ended DAC is modelled as decoder that maps the digital code to thecorrect voltage level. The DAC takes a N-bit digital code as input and yieldscorresponding voltage, the VRange = 1V is set as a parameter in the code, sothe N-bit code for N=12 is mapped onto a voltage level that differ by 1/212.The differential DAC is modelled by putting two single-ended DAC structurestogether in parallel.

6.2.3 Comparator

The comparator is modelled as a block that takes input signal vin and comparesit with reference signal vRefSig. The comparison is done by first perform thesubtraction vin−vRefSig then it is checked whether the result is positive (aboveor equal to zero) or negative (below zero), if former is true comparator outputvoltage is logical high that is the max allowed voltage else it is logical zerothat is ground. The differential structure is developed by adapting the parallelapproach as mentioned above is used.

6.2.4 Successive Approximation Register (SAR)

The 12-bit SAR is implemented by using 12 D-latches, each having a 1-bitinput D and complementary outputs Q and Q′, control inputs for each latchare Setsignal = 1 for setting the value in the latch to logic one, Resetsignal = 1for resetting the value to a logic zero, Enablesignal = 1 to accept the value fromthe comparator output. The bits can be updated individually at each clockcycle and the Enablesignal for each latch decides when that happens. Input issampled at a particular instant indicated by the Samplesignal. The MSB (latch)in the SAR is intially set using the Setsignal = 1 for MSB (latch) and all otherscleared using their respective Resetsignal. The value in the SAR is converted

47

TI-SAR ADC Behavioral Model of TI-SAR ADC

back to voltage using DAC, that is then compared to the held input employinga comparator. Next clock cycle the MSB value is updated by the result of thecomparison and the next bit in line is set. The whole process is repeated untilthe complete 12-bit digital code corresponding to the held input is generated.It is important to note that the hardware is also following the binary searchalgorithm as mentioned in Chapter 4, this is made possible with the help of thecontrol signals to the SAR. The Setsignal and Enablesignal are set one after theother for each bit, for all bits in the register starting from leftmost i.e., the MSBup till the rightmost LSB, each clock cycle. The Enablesignal of a certain latchis the delayed version of its Setsignal.

6.3 TI-SAR ADC

The TI structure is implemented by putting in parallel M- channels (slices) ofN-bit SAR ADCs. The designed structure contains M=16 slices each havinga resolution of N=12 bits. The input is connected to all 16-slices, but eachchannel’s T/H works on different Samplesignal, so each channel samples samplesthe input at a distinct instant decided by its Samplesignal. The computationtime of each SAR ADC is ideally given by

TcomputationChannelADC

= TSampling + TConversion

= 1 · (ClockCycle) + N · (ClockCycle)= (N + 1) · (ClockCycle)

The 16-channels pick up 16 consecutive input values. After 13 (clock cy-cle), the first channel which starts computation during first (clock cycle), hasconverted the its input to a 12-bit digital code, and it is sent to output bufferduring the fourteenth (clock cycle), it idles for a cycle then its SAR is reset fornext input value. The output buffer operates at 16 times faster rate than theSamplesignal frequency i.e., fClk so it picks up the 12-bit digital value everyclock cycle from one of the channels. This achieves multiplexing of the 12-bitoutputs coming from the 16 channels to a single 12-bit output.

6.3.1 Phase Generation Block

The different channels have to operate at different instants to capture distinctinput values. For the parallel channels to function as desired, 16 distinct phasesneed to be created, so phase generator is modelled, using a 4-bit counter and a4X16 decoder behavioral models. The phase generator is actually performing afrequency division by 16, such that each phase has a frequency of 16 times lessthen that of the input clock.

6.3.2 Timing Scheme for TI-SAR

The phases generated by the phase generation block are used by the 16 channelsas Samplesignal and also used as control signals for the SAR control. The samephases are provided to all channels but only shifted to the right as we movedown the ADC channels, e.g., ADC0 operates on φ15φ14 · · ·φ0, while ADC1

48


Figure 6.1: The 16 phases and the system clock.

operates on φ0, φ15φ14 · · ·φ1 and so on. Intially the developed model had asimple timing scheme that led to idling of channel ADC for two clock cycles.The channel ADC that started sampling at φ0 finished the conversion by the endof φ12 (thirteenth cycle), latched out the data at φ13 (fourteenth clock cycle),waited till next φ0 to work again. The approach was functional but not efficientso another timing scheme was developed to improve the design. The improvedversion allows 2 clock cycles for the computation of MSB and MSB-1 so thatthe accuracy of the result is improved, so the channel that starts sampling atφ0, used φ0 ∨ φ1 for computation of MSB and φ2 ∨ φ3 for MSB-1 rest of thephases for the remaining bits and finally the data is latched out at φ14, φ15 isused to reset the SAR, so absolutely no wait is involved.

The Fig. 6.2 and 6.3 show that internal block diagram of the TI-SAR withthe new timing scheme. The Fig. 6.5 and 6.4 shows how the phases from Fig. 6.1are used inside a channel ADC.

49


Figure 6.2: Block diagram of 16 channel 12-bit TI-SAR ADC.

50


Fig

ure

6.3:

Blo

ckdi

agra

mof

16ch

anne

l12

-bit

TI-

AD

C(C

aden

ceBlo

ck).

51


Figure 6.4: Block diagram of channel SAR ADC.

52


Fig

ure

6.5:

SAR

AD

Cin

tern

albl

ock

diag

ram

(Cad

ence

bloc

k)

53

Verifying Functionality Behavioral Model of TI-SAR ADC

6.4 Verifying Functionality

The sub-modules were tested individually with separate testbenches to ensurecorrect functionality. Once the sub-modules desired functionality was achieved,the top-module was tested to observe the results.

The testbench used for the top-module is shown in Fig. 6.6, DACs are usedto used to convert the digital codes to voltage, so we can observe how does thereconstructed sinusoid correspond to the input. A skill script is used to generatea new input frequency fulfilling the coherent sampling criteria. The file containsa stop time that halts the simulation once certain number of samples are reachedfor this case 1024,spectrum of the output is also printed to assess how the systemworks.

A skill script is a LISP code that is used in Cadence simulation environmentproviding more flexibility to the user by defining variables etc.

54


Fig

ure

6.6:

TI-

SAR

AD

Cte

stbe

nch

(Cad

ence

bloc

k).

55


Fig

ure

6.7:

Tim

edo

mai

nou

tput

ofT

I-SA

RA

DC

(Cad

ence

bloc

k).

56


Table 6.1: Summary of simulation result of the TI-SAR ADC behavioral model.Item Value Unit

Resolution 12 bitsSample Frequency 300 MHzVideo Bandwidth 30 MHz

SNDR 74 dBInput Range 0.5 Vpp

Supply Voltage (VDD) 1.2 VLatency 15 Clock cycles

The results of the simulation are shown in Fig. 6.7, the values are writtento a file that it readable via MATLAB so that SNDR can be computed. Thecomputed value of SNDR is 74 dB approximately. The Fig. 6.7 shows veryclearly that after first fifteen clock cycles the sinusoid is tracked exactly, thus ithas a latency of 15 clock cycles for first computation.

57

Chapter 7

High-speed ComparatorDesign

The chapter starts with a brief description of a comparator. Next he performancecharacteristics and non-idealities of a comparator are discussed. The chapterconcludes with discussion of basic comparator types.

7.1 Comparator

Comparator is circuit that detects whether an analog input signal is smaller orlarger then a given reference signal. The output of the device is digital that isin binary format.

If vIn+ > vIn−then vOut = vOH

else if vIn+ < vIn−then vOut = vOL

where vOH & vOL are the output voltage levels for high and low output sig-nal and vIn+ & vIn− are the input voltage signals to be compared.

Comparators are used in a variety of applications such as digital communi-cation, artificial neural networks, signal and functional generation and ADCs.When used in ADCs comparator performance has a large impact on the ) perfor-mance of the whole ADC, as comparator is responsible for the actual conversion.The comparator can limit the performance of the ADC thus it needs to be de-signed carefully.

7.2 Comparator Performance Metrics

Comparators are characterized in terms of the following performance measures.

7.2.1 Resolution

The minimum detectable signal difference by the comparator is termed as theresolution of the comparator. In other words it is the minimum signal level

58

Comparator Non-idealities High-speed Comparator Design

for which a comparator produces correct output. The resolution requirementcan differ depending upon the type of application it is used for. In the currentcase, it has to be used in a 12-bit ADC so it should be capable of detecting oneLSB for an input swing of 1 V, that is 1

212 approximately 244.1 µV. This is therequired resolution (that should be achieved).

ResolutionRequired = VLSB

=1

2N

where N is the number of the bits of the ADC it is used in.The acquired resolution is the minimum input difference that is successfully

detected by the comparator. Note that smaller the input change that can bedetected by a comparator this means it has high resolution.

7.2.2 Gain

The DC-gain of a comparator is defined as the ratio between, the difference ofhigh and low output signal voltage and the difference of high and low inputsignal voltage. mathematically

GainRequired =vOH − vOL

ResolutionRequired(7.1)

GainAchieved =vOH − vOL

ResolutionAchieved(7.2)

A high DC- gain is required for a good comparator, as the equations aboveshow that a high gain indicates a small value of resolution. The comparator tobe used in a 1 Volt 12-bit ADC, the required DC-gain according to 7.1 will beapproximately 4099 linear.

7.2.3 Propagation Delay

The propagation delay of a comparator is the total time elapsed between in-put excitation and output response of the comparator. It is measured as thedifference between the time input signal crosses half the minimum input signaland the time the output reaches its mean value. It is a very important dynamiccharacteristic, as it limits the conversion rate of the comparator, in turn limitingthe speed of the ADC it is used in. Comparator has a speed accuracy trade-off,as for small signal comparator has a large propagation delay while for a largesignal the propagation delay is small [6].

7.3 Comparator Non-idealities

The robust comparator design is a challenging task, as various non-idealitiesplague the design, some of them are discussed below.

59

Types of Comparators High-speed Comparator Design

7.3.1 Offset Voltage

The mismatches between (input) transistor results in DC offset in a circuit. TheDC offset also known as output referred offset is equal to the value of outputvoltage when input voltage is zero. If output voltage is zero for zero input noDC offset is present. Input referred offset voltage of a comparator is voltagethat appears at the input of the comparator due to transistor mismatches. Itcan be inherent to the design or can appear as result of process variations. Inthe presence of offset voltage vos.

If vIn+ − vIn− > vos

then vOut = vOH

else if vIn+ − vIn− < vos

then vOut = vOL

It can be formally defined as the input level which forces the output voltageto go to zero [16]. It can limit the resolution of the comparator, thus adverselyeffecting the accuracy of the comparator and the ADC it is used in.

7.3.2 Kick-back Noise

The voltage variations at the regeneration nodes of the latch can get coupledwith the input via parasitic capacitance of the transistors and disturb the inputvoltages. This is referred to as kick-back noise. The effect of this noise can bereduced by introducing pre-amplifiers before latches, or using isolation switchescontrolled by clock.

7.3.3 Metastability

Metastability according to [17] is a logical error which results from the inabilityof a comparator or a latch to convert a continuous variable in a discrete one.During the conversion process analog input signal can be very close to theboundary between two states, if the decision has to be made in limited timemetastability is bound to occur.

In order to better understand the phenomenon and its consequences, con-sider a small difference signal is fed to a comparator composed of cross-coupledinverters, it is amplified by the inverter pair to give an output that increasesexponentially in time, if the time is limited or the difference too small it may notbe able to reach a distinct logical “1” or “0” but left in some intermediate “MS”value. The metastable value is latched by the latch placed after the comparator,signaling end of decision time and then input to the following circuit. Now oncethis MS value enters the logic it will be interpreted differently as a “1” or a “0”by different gates depending upon their respective trip points. Thus a soft erroris converted to a hard error.

Metastability can lead to amplitude resolution errors in comparators thatdegrade the converters performance significantly when especially used in a highspeed ADC.

7.4 Types of Comparators

There are different sorts of comparators. The choice of comparator to be em-ployed in a design is largely based upon the application.

60


7.4.1 Open-loop Comparator

It is the simplest kind of comparator consisting of a high gain amplifier withdifferential input and large swing single-ended output. In this configuration, thecomparator has a very high gain resulting in a high resolution (is able to detectvery small signal difference). To maintain the same unity gain frequency fu thepole value fp of the comparator needs to be decreased, thus increasing settlingtime of the comparator. Using an open-loop comparator can significantly slowdown the ADC. This architecture also suffers from input referred offset thatdegrades the performance of the comparator. Thus this type is not preferableto be employed in high speed ADCs.

7.4.2 Latch-only Comparator

The Latch-only comparator operates in discrete time domain instead of contin-uous time-domain. It employs amplification and positive feed-back for compari-son of the input. It has a control input (clock signal) that splits the operation intwo phases. When the control is low, circuit output is pre-charged to VDD andwhen it is high its starts the comparison by discharging the output capacitancewith unequal rates.

Figure 7.1: Latch-only comparator operation [15].

The Fig. 7.1 shows the operation of the latch-only comparator, where Vi+−Vi− is the difference of the differential inputs and Latch is the control signal. Itburns power during the whole operation. It has a high input referred offset thatcan adversely effect the operation of the ADC directly adding up to the totalADC offset. It offers the benefit of high speed. If modeled as a single-pole anda positive feed-back system, the delay of the latch-only comparator is given by

τD =CLoad

gminput· ln

(Vout

Vin

)(7.3)

where gminput is the transconductance of the input device and CLoad is theoutput load.

61


7.4.3 Latch with Pre-amplifier

This configuration is also clocked and has a pre-amplifier preceding it. The pre-amplifier serves to amplify the input difference, thus aiding detection of smallinput difference by the comparator. The pre-amplifier can reduce the inputreferred offset of the latch significantly.

σInputReferredOffset =

√σ2

Pre−ampOffset +σ2

LatchOffset

A2Pre−amp

(7.4)

where σInputReferredOffset is standard deviation of the total input referred offsetof the comparator (pre-amp and latch), σPre−ampOffset is variance of the offsetof the pre-amplifier , APre−amp is the gain of the pre-amplifier and σLatchOffset

is variance of the offset of the latch.It is noticed that 7.4 suggests that if a pre-amplifier having high gain and

low offset is placed before a latch, the input referred offset associated with thelatch will be suppressed by the gain of the pre-amplifier there by reducing thetotal input referred offset.

The pre-amplifier has a gain-speed trade-off. The maximum unity gain fre-quency fu (product of gain APre−amp and bandwidth fp) for a certain technol-ogy is determined by its maximum cut-off frequency fT of the device [15].

fu = APre−amp · fp (7.5)

If fu has to be maintained at a certain fixed value, increasing gain forces thepole value to be decreased, thus increasing the settling time τ = 1

2·π·fp. Thus a

large pre-amplifier gain can reduce offset but also slows down the comparator.The delay of the (dynamic latch with pre-amplifier) comparator is given by

τD =CLoad

gminput· ln

(APre−amp

Vout

Vin

)(7.6)

The delay can be reduced by cascading gain stages, the optimum value ofstages Nopt and total gain required AT is

For AT > 1000Nopt ≈ 1 + log2 ·AT (7.7)

For AT ≥ 1000Nopt ≈ ln ·AT (7.8)

Cascading also help to reduce the gain requirement for each stage thus al-lowing larger bandwidth fp which in turn reduces settling time.

62

Chapter 8

Implementation ofHigh-speed, Low-offsetComparators

The chapter discusses the architectural details of the different comparators de-signed for the ADC, their performance is evaluated and results are discussed.

8.1 Pre-amplifier

Pre-amplifier is used to amplify the signal before it is fed to the comparator,it helps to relax requirements on comparators resolution and gain. It is alsobeneficial in terms of reducing offset.

8.1.1 Architecture of Pre-amplifier

The pre-amplifier architecture selected is shown in Fig. 8.1.The pre-amplifier uses diode connected load and also cross coupled structure

to achieve high gain. The gain of the amplifier is given by the relation in 8.1.

Av =gmM1,2

gmM3,4 − gmM3C,4C

(8.1)

For designing the pre-amplifier its good to translate the relation given in 8.1into widths. Transconductance (gm) of a transistor and its width is given by8.2.

gm =

√µ · cox

W

L· ID (8.2)

ThusAv ≈

WM1,2

WM3,4 −WM3C,4C

(8.3)

To achieve high gain the width of input transistors i.e., M1,2 should beincreased, also the difference between the widths of load transistors i.e., M3,4

and cross-coupled i.e.,M3C,4C transistors needs to kept be small.

63

Pre-amplifier Implementation of High-speed, Low-offset Comparators

Figure 8.1: Transistor-level schematic of pre-amplifier.

Table 8.1: Optimized component values for pre-amplifier.Component Parameter Value UnitsM1,2 Width 10 µmM3,4 Width 15 µmM3C,4C Width 20 µmM5 Width 10 µmAll Transistors Length 0.060 µmNon-ideal current Source current 150 µA

The offset voltage can be significantly reduced by increasing the input tran-sistor width, as offset is inversely proportional to width of the input transistoraccording to 8.4 .

σos ≈ 1√W · L (8.4)

The design was optimized to achieve desired performance, the componentvalues are tabulated in the Table. 8.1.

8.1.2 Simulation Results of Pre-amplifier

The designed pre-amplifier was simulated in Cadence to verify its functionality.The Graph in Fig. 8.2 shows the gain of the pre-amplifier. The input referred

64

Pre-amplifier Implementation of High-speed, Low-offset Comparators

Figure 8.2: Gain of pre-amplifier.

offset was measured by running Monte Carlo analysis, result of 100 runs is pre-sented in Fig. 8.3. The specifications achieved are summarized in the Table. 8.2.

Figure 8.3: Offset of pre-amplifier

The results shown in Table. 8.2 indicate that the designed pre-amplifier pro-vides a high gain which can help to reduce the offset introduced by comparator.

65

Comparator Implementation of High-speed, Low-offset Comparators

Table 8.2: Achieved simulation results of pre-Amplifier.Performance Measure Value Units

Gain 13.92 dBBandwidth 550 MHz

Input DC-level 500 mVInput referred Offset 5.2 mVPower consumption 155 µW

The circuit bandwidth for the ADC as mentioned in Table. 1.1 needs to beabove 500 MHz, the designed pre-amplifier has a 3-dB bandwidth of 550 MHz.Although the maximum bandwidth of the video signal input to the system is30 MHz, the circuit bandwidth for video signals should be kept approximately7 times the highest bandwith so that image quality doesn’t get degraded. Inthis design target for circuit bandwidth is set to approximately 16 times so thatif the input signal bandwidth increases to 60 MHz still the design works fine.The design is sensitive to process variations and mismatch as the input referredoffset voltage acquires quite a large when Monte Carlo simulation is run. Thepower consumption is low but even lesser would be better.

8.2 Comparator

Two high speed comparators architectures were implemented, they are discussedin the upcoming sections. The architecture of the comparators consist of a re-generative latch, an output Set Reset (SR) latch followed by a chain of invertersat the output. The regenerative latch yields the result of the comparison. Thepurpose of the SR latch is to hold the result and the chain of inverters serveto make the rise and fall time sharper, which make the comparator suitable forusage at high speed.

66


Figure 8.4: Transistor-level schematic of the SR latch.

67


8.2.1 Architecture of Comparator1

The architecture of the first comparator consists of a regenerative latch from [18]followed by an SR latch and inverters. The regenerative latch works on a clockand performs the actual comparison. The comparator architecture selected isshown in Fig. 8.5. During the pre-charge state i.e., when the clock is low, the

Figure 8.5: Transistor-level schematic of the comparator1 architecture.

PMOS transistors M10,11 turn on and charge the output node capacitance toVDD. The NMOS transistor M5 is switched off thus bring the path between theinput transistors. When the clock becomes high (evaluation state) the NMOStransistors M1 and M2 are switched on establishing a path to ground. TheNMOS transistor M5 is switched on thus connecting the sources of the inputtransistors to ground. Now if a differential input signal is applied at the gatesof the input transistors, it results in discharging of the output capacitance atdifferent rates. The applied voltage is proportional to the flow of current, so ifvinP larger then it causes voutN node to fall rapidly. When it reaches a valuebelow VDD − |VThersholdP | the PMOS M9 is turned on which produce a logic“1” at voutP and consequently a “0” at voutN .

The design was optimized to achieve desired performance, the componentvalues are tabulated in the Table. 8.3.

8.2.2 Simulation Results of Comparator1

The comparator was simulated in Cadence to verify the functionality and ob-serve the results. The resolution of the comparator is found to be 150 µm, it isthe smallest difference it can detect. The gain is calculated to be 6666.6 whichis equivalent to about 76.5 dB. Comparators have a have a longer propagation

68


Table 8.3: Optimized component values for comparator1.Component Parameter Value UnitsM1,2,3,4,6,7 Width 3 µmM5 Width 1 µmM8,9,10,11 Width 2 µmAll Transistors Length 0.060 µm

delay for a smaller input difference, so it was measured for 150 µm as shown inFig. 8.6. The offset of the comparator was measured by running Monte Carloanalysis, result of 100 runs is presented in Fig. 8.7.

Figure 8.6: Propagation delay of comparator1.

69


Figure 8.7: Offset of comparator1.

70


The results achieved are summarized in the Table. 8.4.

Table 8.4: Achieved simulation results of comparator1.Performance Measure Value Units

Gain 76.5 dBResolution (Normal sim) 150 µV

Resolution (Monte Carlo sim) 4 mVInput DC-level 500 mV

Input Referred Offset 2.27 mVPropagation Delay 1.69 nsPower consumption 199 µW

The propagation delay is 1.69 ns being slightly higher than fSample/2 it isundesirable. The function of this comparator is affected by process variationsand mismatch as the resolution as a result of Monte Carlo simulation is 4 mVwhich is high. The input referred offset is also very high. The power consump-tion of comparator1 including the out SR latch and three inverters seems to bereasonable.

8.2.3 Architecture of Comparator2

The architecture of the second comparator consists of a regenerative latch from[19, 20] followed by an SR latch and inverters. This regenerative latch is a dy-namic latch that has low offset and high output load drivablity. The comparatorarchitecture selected is shown in Fig. 8.8.

The input gain stage and out latch stage of this comparator is separated thusallowing the comparator to work at a lower supply voltage and have a stableoffset voltage. This architecture has two additional inverters that are placedbetween the input and output stage of the conventional double-tail dynamiccomparator. These inverters serve to strengthen the regenerative nodes to helpproduce a faster result [20].

During the the pre-charge state i.e., when the clock is low the PMOS tran-sistors M4 and M5 turn on charging the node capacitance at Di+ and Di− toVDD.This in turn leads to switching on the NMOS transistors M16 and M17

of the inverters thus discharging Di′ nodes. This leads to turning on of thePMOS transistors M10,M11,M14 and M15 sequentially and charging of the out-put, Sw+ and Sw− nodes to VDD while the NMOS transistors M12 and M13

are turned off.During the decision-making phase i.e., when the clock is high and the Di

nodes start to discharge from VDD to ground at a rate directly proportional tothe magnitude of the input voltages that are applied. When either of the nodesdrops below VDD−|VThersholdP | then the PMOS transistors M18 and M19 invertthe Di nodes into regenerated amplified Di′ nodes signal. The Di′ nodes havea rise time inversely proportional to the difference between the input signalsapplied. The NMOS transistors M12 and M13 turn on one after the other andlatch regenerates the input difference to a full scale digital level [19, 20]. Thedesign was optimized to achieve desired performance, the component values aretabulated in the Table. 8.5.

71


Figure 8.8: Transistor-level schematic of comparator2

The comparator meets performance for small width of all transistors expectthe ones being used in inverters. During the design optimization process it wasnoticed that making them larger improved the speed of the comparator.

8.2.4 Simulation Results of Comparator2

The resolution of the comparator was found to be 200 µ m , it is the lowestdifference it can detect. The gain is calculated to be 5000 which is about 73.9dB. The propagation delay was measured for 200 µm as shown in Fig. 8.9 is240 ps. The offset of the comparator was measured by running Monte Carloanalysis, result of 100 runs is presented in Fig. 8.10.

72


Table 8.5: Optimized component values of comparator2.Component Parameter Value UnitsM1 Width 0.5 µmM2,3 Width 1.2 µmM4,5,10,11,14,15 Width 0.135 µmM6,7,12,13 Width 0.4 µmM16,17 Width 5 µmM18,19 Width 10 µmAll Transistors Length 0.060 µm

Figure 8.9: Propagation delay of comparator2.

73


Figure 8.10: Offset of comparator2.

74


The specifications achieved are summarized in the Table. 8.6

Table 8.6: Achieved simulation results of comparator2Performance Measure Value UnitsGain 73.9 dBResolution (Normal sim) 200 µ VResolution (Monte Carlosim)

12 mV

Input DC-level 500 mVInput referred Offset Negligible µ mPropagation Delay 240 psPower consumption 169.6 µ W

The propagation delay is much lower than fSample/2 making it suitable for highspeed design. The function of this comparator is sensitive to process variationsand mismatch as the resolution as a result of Monte Carlo simulation is 12 mVwhich is very high. The input referred offset is almost “0” negligible, thus it isvery suitable for high speed high resolution ADCs. The power consumption ofcomparator1 including the out SR latch and three inverters seems to be reason-able but lower would be better.

As both comparator designs meet the need for high gain, speed and low power,but the later has low offset, which makes it a good candidate for the ADC in thevideo AFE. It is good to mention here that the former comparator’s offset canbe suppressed by using a high gain low offset pre-amplifier.

75

Chapter 9

Simulation Results

The simulation setup is described, followed by a brief description of the dynamictesting procedures adopted. The comparator1 and comparator2 transistor-levelschematics were placed in the TI-SAR ADC top module (as discussed in chapter6), replacing the behavioral model of the comparator to check their respectiveperformance. The simulation results are discussed and findings are listed.

9.1 Simulation Setup

It is important to study the response of the ADC to high frequency analoginput with varying amplitude, as such inputs can be encountered in practice.For dynamic testing sinusoidal inputs are used. The system is co-simulated inCadence and MATLAB.

The the simulation setup is a Direct ADC-DAC Test as shown below inFig. 9.1, the ADC output is fed to a DAC which converts the bit stream fromADC to analog voltage, so that we can observe DAC output as the ADC inputchanges. A skill script was used to ensure that the coherent sampling criteria(as discussed in chapter 5) is met so that maximum points on the sine wave aresampled so that all levels of input to the ADC can be examined. A file strobeis used to write the output to a file (which can be read in MATLAB). Theskill script contains a stop time that halts the simulation once 1024 samples arereached after throwing away the initial specified number of samples. Once thesimulation ends and output file is created, it is read and processed in MATLAB.

76

Simulation Setup Simulation Results

Fig

ure

9.1:

TI-

SAR

AD

Cte

stbe

nch

(Cad

ence

bloc

k)

77

Simulation using Comparator1 Simulation Results

9.1.1 FFT Test

The time domain output of the ADC is converted to frequency domain by takingFFT (Fast Fourier Transform), so that quantitative information on output noiseand distortion can be acquired, this type of dynamic testing is called as FFTtest. The SNDR (Signal to Noise and Distortion Ratio) and ENOB (EffectiveNumber Of Bits) are computed, to judge the performance of the system.

9.1.2 Code density Test

Code density test or the histogram, is a test in which large numbers of sam-ples are collected and their respective frequency of occurrence is plotted as ahistogram verses possible output codes. Such histograms are constructed withbins each representing an output code and hence all input values that producethat code. The histogram of behavioral model (Ideal) ADC as shown in Fig. 9.2is found and then compared with the histogram obtained later from non-idealmodel. DNL (Differential Non-Linearity) can be found by subtracting the for-mer from the later, offset error appears as a horizontal shift and gain error isviewed as horizontal compression of the original [21].

Figure 9.2: Histogram plot of ADC for sinusoidal input.

9.2 Simulation using Comparator1

The TI-SAR ADC was simulated employing the former comparator design pre-ceded by the designed pre-amplifier. The amplitude was varied to observe thebehavior trend.

78


Figure 9.3: SNDR versus signal amplitude graph for TI-SAR ADC using com-parator1.

Figure 9.4: ENOB versus signal amplitude graph for TI-SAR ADC using com-parator1.

79


The graphs in Fig. 9.3 and Fig. 9.4, clearly show that firstly reducing am-plitude improves SNDR and ENOB for this particular design and secondly thedesign doesn’t meet the expected SNDR i.e., 74 dB for any amplitude.

Figure 9.5: Result of FFT test. Output spectrum of TI-SAR ADC usingcomparator1 for signal amplitude of 0.25 Vpeak.

The difference between Fig. 9.2 and 9.6 can be viewed but in order to ex-tract qualitative information the number of samples need to be increased in thesimulation.

The simulation results obtained are summarized in Table. 9.1.

80


Figure 9.6: Result of code density test. Histogram of TI-SAR ADC usingcomparator1 for signal amplitude of 0.25 Vpeak.

Table 9.1: Summary of the simulation results of the TI-SAR ADC using com-parator1.

Item Value UnitResolution Approx 9 to 3.1 bits

Sample Frequency 300 MHzVideo Bandwidth 30 MHzCircuit Bandwidth 550 MHz

SNDR 58 to 20 dBInput Range 0.3 to 1 Vpp

Supply Voltage (VDD) 1.2 VLatency 15 Clock

cyclesPower Consumption 5.664 mW

81


9.3 Simulation using Comparator2

The TI-SAR ADC was simulated employing the later comparator design pre-ceded by the designed pre-amplifier. The amplitude was varied to observe thebehavior pattern.

Figure 9.7: SNDR versus signal amplitude graph for TI-SAR ADC using com-parator2.

82


Figure 9.8: ENOB versus signal amplitude graph for TI-SAR ADC using com-parator2.

The graphs in Fig. 9.7 and Fig. 9.8, clearly show that firstly reducing am-plitude improves SNDR and ENOB for this particular design and secondly thedesign doesn’t meet the expected SNDR i.e., 74 dB for any amplitude.

Comparing the two graphs in Fig. 9.9 and Fig. 9.10 shows that as the in-put amplitude increases the system becomes more non-linear as the harmonicdistortions in Fig. 9.10 have significantly high amplitude.

83




84




85


The difference between Fig. 9.2, Fig. 9.11 and Fig. 9.12 can be easily observedbut in order to extract qualitative information the number of samples need tobe increased in the simulation. The horizontal compression in Fig. 9.11 ascompared to the original in Fig. 9.2 is due to the fact that the range of theinput sinusoidal input is very small i-e 0.3 V (peak-to-peak). Comparison of theFig. 9.12 with Fig. 9.2 suggests that due to high amplitude significant amountof clipping is experienced.

The simulation results obtained are summarized in Table. 9.2.

Table 9.2: Summary of the simulation results of the TI-SAR ADC using com-parator2.

Item Value UnitResolution 10.17 to 3.47 bits

Sample Frequency 300 MHzVideo Bandwidth 30 MHzCircuit Bandwidth 550 MHz

SNDR 63 to 22 dBInput Range 0.3 to 1 Vpp


cyclesPower Consumption 5.193 mW

86

Simulation using Ideal Pre-amplifier Simulation Results

9.4 Simulation using Ideal Pre-amplifier

The simulations run on the stand-alone comparators without putting them inthe top-modules (as reported in Chapter 8 ) have been quite promising so it isdesired to search for the bottle-neck in the design.

The initial effort in this regard was made by replacing the the designed pre-amplifier by an ideal one i.e., a Voltage Controlled Voltage Source (VCVS) andre-running the simulation for comparator1 and comparator2.


The simulation results obtained are presented in Table. 9.3.

87



88


Table 9.3: Simulation results of the TI-SAR ADC using comparator1 with idealpre-amplifier.

Item Value UnitResolution 11.96 bits

Sample Frequency 300 MHzVideo Bandwidth 30 MHzCircuit Bandwidth Infinite N/A

SNDR 73.89 dBInput Amplitude 1 Vpp


cycles

89




90


The simulation results obtained are presented in Table. 9.4.

Table 9.4: Simulation results of the TI-SAR ADC using comparator2 with idealpre-amplifier.

Item Value UnitResolution 11.05 bits

Sample Frequency 300 MHzVideo Bandwidth 30 MHzCircuit Bandwidth Infinite N/A

SNDR 71 dBInput Amplitude 1 Vpp


cycles

The ideal pre-amplifier used in the simulation provides fixed output com-mon mode level and no bandwidth limitation thus the SNDR has improveddrastically. The behavior of comparator1 is better than comparator2 in thisconfiguration.

The results show that pre-amplifier is indeed the bottle-neck in the design,thus to achieve the desired performance it has to re-designed.

91

Chapter 10

Conclusion and FutureWork

10.1 Conclusion

The thesis presented the mathematical and behavioral modelling of a TI-SARADC and implementation of high-speed low offset comparator design for theADC. Two architectures have been implemented for the 16 channel TI-SARADC with 12-bit resolution. The SNDR was measured for different amplitudeof input signal having a maximum frequency of 30 MHz at a sample rate of300 MHz. The comparator2 shows better performance than comparator1 whenused with the designed pre-amplifier achieving 63 dB SNDR. Using an ideal pre-amplifier comparator1 achieves SNDR of 73.89 dB which is greater than that ofcomparator2. Simulations using an ideal pre-amplifier reveal that the designedpre-amplifier has some limitations and needs to be re-designed.

10.2 Future Work

Future prospects are the following:

• The simulations run on the stand-alone comparators without putting themin the top-modules have been quite promising so it is desired to search forthe bottle-neck in the designed pre-amplifier and re-design it to achievebetter performance. The large bandwidth could be traded for even bettergain, this may lead to some reduction in offset voltage.

• As the behavioral model is running as expected, next steps would be todesign charge redistribution DAC, replace in the behavioral model andmeasure performance.

• Moving towards the layout of the comparator and DAC once schematicmeets the desired level of performance.

92

Appendix A

Video Basics Review

The Appendix provides information regarding video signal transmission, definingbasic phenomenon. It also gives brief review of the available video formats andinterfaces.

A.1 Video on Screen

The video is defined as “moving picture”, so how is it formed on display sothat it appears to be a moving ? A picture is drawn on a display by sweepingan electrical signal along the display, horizontally line by line. The amplitudeof the signal decides the brightness of the display at certain point in time. Atthe end of each line a part of the signal waveform tells the scanning circuit toretrace the line, and start scanning the next line. This is done for all horizontallines till the whole picture is scanned. Another portion of the signal tells thescanning circuit to retrace to the top of the display and start scanning the nextframe or picture. These steps are repeatedly fast enough so that the pictureappears to be in motion [23].

A.2 Video Signal

An analog video signal consists of a low-voltage signal containing the intensityinformation for each line, in combination with timing information that ensuresthe display device remains synchronized with the signal. Typically the compo-nents of the signal are shown in Fig. A.1.

Horizontal Sync

The horizontal sync signals the start of a new horizontal video line [22].

Vertical Sync

The vertical Sync signals the start of a new frame that is one complete scan ofthe picture [22].

93

Video Signal Video Basics Review

Figure A.1: Video signal composition [22]. Copied from Video Signal Measure-ment and Generation Fundamentals Dec 11, 2009 .

Blanking Interval

There are two types of blanking intervals, horizontal and vertical blanking inter-vals. Horizontal blanking interval is defined as the time it takes to retrace thesignal from right edge back to the left edge, in order to start next (horizontal)scan line. Vertical blanking interval is defined as the time it takes to retrace thesignal from bottom back to the top in order to start next frame [22].

Back Porch

The back porch is area of the video signal defined as the time between the risingedge of the sync and the start of the active video [23].

Clamp Interval

The clamp interval refers to the time period during which the DC part of thevideo signal is set to some value, it happens typically during the back porch[22].

Color Burst

Color burst is also known as the color subcarrier [23]. It is a high frequencyregion located on the back porch, it mainly provides phase and amplitude ref-erence for color information [22].

94

Video Signal Video Basics Review

Front Porch

The front porch is the area of the video signal defined as the time between theend of the active video and the leading edge of the sync [23].

Breezeaway

The Breezeaway is the video signal defined as the time between the color burstand the rising edge of the sync pulse [23].

A.2.1 Video Levels

The video levels define the levels and ranges of different parts of the video signal.The unit used to define video levels is the Institute of Radio Engineers (IRE).

Figure A.2: Video levels [22]. Copied from Video Signal Measurement andGeneration Fundamentals Dec 11, 2009 .

Blanking Level

The blanking level refers to the reference level of the video signal. In otherwords the voltage of the signal during horizontal and vertical periods, it is 0 Vor 0 IRE [23, 22].

White Level

The white level is the level of the video signal corresponding to 100 IRE [22].

Black Level

The black level is level of the video signal that may be higher or equivalentto the blanking level. For NTSC it corresponds to 7.5 IRE and for PAL andSECAM it is aligned with the blanking level [22]

95

Video Resolution Video Basics Review

Sync Level

The sync level is the video signal level around -40 to -43 IRE [22].

Burst Amplitude

The burst amplitude refers to the average video signal level it ranges around20-21. 5 IRE [22].

Peak Level

The peak level is the maximum attainable video signal level it lies around +120to +133 IRE [22].

A.3 Video Resolution

The resolution of video display refers to the amount of detail that can be seen(viewed). The resolution of a television system is specified by “TV lines” pa-rameter which typically indicates horizontal resolution, it can also be vertical.Computer resolution formats are specified by the number of pixels in horizontaland vertical dimension [23].

A.4 Video Formats

There are different video formats for television and computer displays.

A.4.1 Television Video Formats

The television formats differ for different regions. The National Television Sys-tems Committee (NTSC) format is employed in Japan and USA, it’s namestands for the organization that developed it. The standard used in Europe isPhase Alternating Line (PAL), that is an improved version of NTSC. Sequen-tial Color Avec Memoir (SECAM) is a French standard. Each of the formatscontain up to 15 different sub-formats within the format. The formats have acompatibility issue due to different scanning frequencies, number of scan linesand color modulation techniques [23].

A.4.2 Computer Video Formats

The computer formats such as Video Graphics Array (VGA), Extended Graph-ics Array (XGA) and Ultra Extended Graphics Array (UXGA) are the samethroughout the world. They are distinct having unique properties, with differ-ent scan frequencies but they don’t have any compatibility issues, so contentcan be exchanged globally [23].

Table. A.1 summarizes typical characteristics of TV and Computer videoformats.

96

Video Formats Video Basics Review

Tab

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ofT

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dco

mpu

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vide

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s[2

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97

Video Interfaces Video Basics Review

A.5 Video Interfaces

The primary video signal interfaces are explained below.

A.5.1 Composite/CVBS Interface

Composite video is also known as CVBS which stands for Colour Video Blank-ing Sync. It consists of a single wire pair that contains Chroma (C) the coloredportion of video, Luma (Y)the monochrome portion of video containing bright-ness information and synchronizing signal used for synchronization of the videoall in one cable. The level of encoding is high, which result in degradation ofimage [23, 22].

Figure A.3: Monochrome composite video signal (luma steps from white toblack) [22]. Copied from Video Signal Measurement and Generation Funda-mentals Dec 11, 2009 .

Figure A.4: Color information signal for a color bar line (including the colorburst) [22]. Copied from Video Signal Measurement and Generation Fundamen-tals Dec 11, 2009 .

A.5.2 S-video Interface

The term S-video stands for separate-video interface. It has relatively less en-coding, thus it carries the Chroma (C) and Luma (Y) on separate sets of wires.It is also known as Y/C signal and due to lesser encoding has better videoquality [23, 22].

98

Video Interfaces Video Basics Review

Figure A.5: Color Composite Video Signal for a Color Bar Line [22]. Copiedfrom Video Signal Measurement and Generation Fundamentals Dec 11, 2009 .

A.5.3 Component Interface

The component video signal interface consists of three pair of wires, so it hasleast encoding that yields great quality. One wire is for Luma (Y) plus synchro-nization information and the other two contain color difference signals like redminus Y blue minus Y. The key idea is that the each of the base componentRed (R), Blue (B) and Green (G) can be derived from this information. Thevariations of component interface are [23] :

• Y, B-Y, R-Y

The is the generic type consisting of Luma and color difference signals.

• Y, Pr, Pb

This variation is composed of Luma and scaled versions of the differencesignals B-Y and R-Y.

• Y, Cr, Cb

This is the digital counterpart of Y, Pr, Pb.

A.5.4 Computer Signal Interface

Mostly all computer signal interfaces use the RGB signal format. The pictureinformation is carried by three different signal components that are Red (R),Blue (B) and Green (G) while the synchronization information is carried byseparate signals horizontal (H) and vertical (V). Sometimes the sync informationis merged with one of the picture signals, mostly the green one [23].

99

Bibliography

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[2] J. Jacob Wikner, Project Specification:Design of building blocks for an ADCfor video applications. Linkoping University, version 2.0 2009.

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Documents

Institutionen för systemteknik - DiVA portalliu.diva-portal.org/smash/get/diva2:383331/FULLTEXT01.pdf · Institutionen för systemteknik Department of Electrical Engineering Examensarbete