Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece Logic cells and interconnect strategies for nanoscale

Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr

Logic cells and interconnect strategies for nanoscale

reconfigurable computing fabrics

I. O'Connor, K. Jabeur, D. Navarro, N. YakymetsLyon Institute of Nanotechnology, Lyon, France

P.E. Gaillardon, M.H. Ben Jamaa, F. ClermidyCEA-LETI-MINATEC, Grenoble, France

nano.grain


Outline

• Some technology fabric considerations• Logic cells

– Reduced-complexity dynamic standard cells– Reconfigurable logic cells and design methods

• Interconnect strategies– Matrix topologies– Island-style architecture– Metrics and comparisons

• Conclusions


Explaining the jargon

• nanoscale computing fabric (nanoFabric):– nanoFabric: an array of connected nanoscale

logic blocks (nanoBlocks)– nanoBlock: a circuit block containing

programmable devices to compute boolean logic functions and means to route data

• usually hybrid approach (silicon die, or CMOS compatible):– bottom-up structure: chemical self-assembly for

dense and regular arrangement of elements– top-down structure: conventional process options

for interconnect or for computation– and memory …


Double-gate ambipolarity

• In DG-CNTFETS, the Id-Vg characteristic demonstrates ambipolarity– Vbg > 0V:

device behavior = n-type FET

– Vbg < 0V:

device behavior = p-type FET

– Vbg floating / 0V:

device is in the off state

• Verilog-A model developed (IMS)• Reduced-complexity logic cells• Ultra fine-grain reconfigurable logic

cells

Y.-M. Lin et al., IEEE Trans. Nanotechnology, 4(5),2005

-V

-V

+V

+V

-V

-V

on (n)

off (n)

on (p)

off (p)

G PG state

+V

+V

X 0 off (n/p)

CNT

Bulk Si

SiO2

HfO2

CNT

Si3N4

Al

Al2O3

PG

GCNT

Bulk Si

SiO2

HfO2

CNT

Si3N4

Al

Al2O3

PG

G

Bulk Si

SiO2

HfO2

CNT

Si3N4

Al

Al2O3

PG

G

G PG

D/ S

D/ S


Hybrid technology

cnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4w

conventionallithography

and metal layers

layer of alignedsemiconducting

CNTs

inter-layer4x4 omega

interconnect

DRLC_7Tcell

10.4

µm

13.4µm

• "Selective Growth of Well-Aligned Semiconducting Single-Walled Carbon Nanotubes", L. Ding et al., Nano Lett., 9(2), 800 (2009)

• "Monolithic integration of CMOS VLSI and carbon nanotubes for hybrid nanotechnology applications", D. Akinwande et al., IEEE Trans. Nanotechnology, 7(5), 636 (2008)


Outline




• Conclusions


Dynamic logic standard cells

• use the extra gate (PG) to reduce complexity

• function path includes EV phase

• transistor count:– 2n (static logic)– n+2 (conventional DL)– n+1 (this work)

• clocking strategy:– Double clock (DCK)– Multiple clock (MCK)– Single clock (SCK)

EV

function path

PC

Out

+V

+V

In1

In2

Inn

+V

A

B

VbA

VbB

Y

Pc

gnd

Vdd

Ev • Layout flipping: rich set of operators


SCKMCKDCK

Clocking strategies and cell variants

• PUN• EV{0,+V},

PC{0,+V} • Precharge:

(PC=+V, EV=0)• Evaluation:

(PC=0, EV=+V)

• PUN• EV+{0,+V}, EV-

{0, -V}, PC{0,+V}

• mixed N- and P-function path: more complex functions

function path

PC

EV-

Out

+V

+V

In1

In2

Inn

EV+

function path

Clk

Out

+V

In1

In2

Inn

-V

function path

PC

EV

Out

+V

+V

In1

In2

Inn

• PDN• Clk{0,+V}• Precharge:

(Clk=0)• Evaluation:

(Clk=+V)• complementary

functions


Comparison (simulation)

• Vdd=1V fclk=3GHz, tr=tf=20ps, CL=150aF

• av. power +(0-20)%• wc. delay -(30-50)%

– no EV transistor, lower branch resistance

• pdp –(25-40)%

0

0,2

0,4

0,6

0,8

1

1,2

1,4

Av. power (µW)

CDL

DCK

MCK

SCK

0

5

10

15

20

25

30

Worst-case time delay (ps)

CDL

DCK

MCK

SCK

0

2

4

6

8

10

12

14

16

PDP (aJ)

CDL

DCK

MCK

SCK


Reconfigurable logic cell CNT-DR7T

• boolean data inputs A and B, data output Y {0,+V)

• four-phase non-overlapping clock signals PC1, PC2, EV1, EV2 {0,+V)

• ternary configuration inputs VbgA, VbgB, VbgC {-V,0,+V)

EV2

PC2

EV1

PC1

t

C

Y

f(A,B,VbA,VbB)

f(C,VbC)

= 1.5nmIoff = 10-13AIon/Ioff=105

VbAA VbB B

EV1

PC1 EV2

PC2

VbC

Vdd

Y

C

J. Liu, I. O'Connor, D. Navarro, F. Gaffiot,El. Lett., 43(9), April 2007

VbgA VbgB VbgC Y

+V

+V

-V

-V

+V

+V

-V

-V

+V

+V

-V

-V

+V

+V

-V

-V

+V

-V

+V

-V

+V

-V

+V

-V

A+B

A+B

A.B

A.B

A.B

A+B

A.B

A+B

A

A

B

B

1

0

+V 0 +V

+V 0 -V

0 +V +V

0 +V -V

0 0 0

0 0 -V


Towards complete operator sets

Va1

PCPC

OutOut

+V+V+V

+V

BBAA

EVEV +V

Vb1

Va2 BBVb2AA

T1 T2

T3 T4

VG

AA VgA

BVgBB

pc2 +V

ev2+V

Y

C

VgC

Tc1 Tc2

Tc3 Tc4

Tc5

+V

ev1 +V

pc1 +V

Logic function Inv/Follower

VG

AAAA VgA

BBVgBBB

pc2 +V

ev2+V

Y

C

VgC

Tc1 Tc2

Tc3 Tc4

Tc5

+V

ev1ev1 +V

pc1 +V

Logic function Inv/Follower

11

6

15

4

15

9

16

4

19

7

14

3

16 16

38

25

0

5

10

15

20

25

30

35

40

av.power(10-²uW) Transistors # Functions # Config.signals

DRLC-6T

DRLC-9T

CNT-DRLC-7T

PAL

• 1.5X-2X decrease in power consumption

• more functions, fewer transistors, one extra configuration signal

DRLC-6T15 functions

DRLC-9T16 functions


Outline




• Conclusions


Physical view: clusters of matrices

inter_matrix_routing inter_matrix_routing

inter_matrix_routing inter_matrix_routingb

uffer

bu

fferb

uffer

bu

ffer

bu

fferb

uffer

bu

fferb

uffer

SB

bu

fferb

uffer

bu

fferb

ufferS

Bb

uffer

bu

ffer

bu

fferb

uffer

SB

SB

SB

bu

fferb

uffer

bu

fferb

uffer

bu

fferb

uffer

bu

fferb

uffer

SB

SB

SB

SB

cnt_omega_4d4w

cnt_omega_4d4w cnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4wcnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4w

cnt_omega_4d4w


Directed matrix interconnect topologies

Mod_Omega_4d4w

Baseline_4d4w

Flip_4d4w

Banyan_4d4w

A data inputs

frc

B

YY

logic function

data output (x2)

configuration inputs


0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

6 7 8 9 10 11 12 13 14 15 16

% cas exploitable Oméga - 0 défaillance Banyan - 0 défaillance

Baseline - 0 défaillance Flip - 0 défaillance

Mapping success rate for matrices

omega topology can achieve up to 25%

more functions

% exploitable cases

0-fault baseline

0-fault omega

0-fault flip

0-fault banyan

40%@12pt

20%-30%@12pt

90%@6pt

75%-80%@6pt


Towards undirected topologies

f11 f12

f21 f22

f11 f12

f21 f22

f11 f12

f21 f22

Metrics Banyan Systolicarray

Cross-cap

Max. I/O data width / side -- - +

Intra-matrix connectivity - - +

Total wire length wa+2a(w-1)

Max. primary I/O path length wa+2a(w-1)

Av. mapping success rate (2x2) 61% 58% 66%

1)a(w222a

1)a(w222a

1)a(w222a

1)2a(

Cross-capBanyan Systolic array


When to move to island-style?

SB CB

CB

SB CB

CB

SB

CB

SB CB SB CB SB

CB CB CB

I/O I/O

I/O

I/O

SB CB SB CB SB

I/O I/O

I/O

I/O

Notused

Notused

Notused

Notused

NotusedNot

usedNot

usedNot

usedNot

usedNot

used

NotusedNot

usedNot

usedNot

usedNot

usedNot

used

V A

Notused

Notused

VVV AAA

NotusedNot

usedNot

usedNot

usedNot

usedNot

used

AAANot

usedNot

usedNot

used

AAA &&&

AAA &&&

X1

X1

X1

X1

Cin(X1 X2)

Cin(X1 X2)

CinCin

CinX1X2X1X2 Cin(X1 X2)

Cin(X1 X2)

Cin(X1 X2)Sum

X2

X1X2

Cout

Cout

Cout

Cout

Cin

Cin

Cin

Sum

Sum X2

X2Sum

X2

X1X2

X1 X2

X1 X2

X1 X2

X1X2Cin(X1 X2)

X2Switch Box

Connection Box

BBB &&&

AAA VVV

NotusedNot

usedNot

used BBB

&&& AAA

AAA

AAA

AAA AAA

NotusedNot

usedNot

used BBB

Cin

Sum

Cout

X1

X2

Cin

X2

X1

Metrics Island-style Cell matrix

No. transistors involved in mapping, T 258 375

% mapped matrices in a cluster 75 100

No. of switches added to connect matrices 168 0

Island-style Cell-matrix

1-bit FA application


Wrap-up

• Logic with ambipolar DG-CNTFETS:– reduced-complexity dynamic-logic standard cells

with –(25-40)% PDP– complete operator set dynamic-logic

reconfigurable cells with low transistor count and power consumption

• Interconnect strategies:– directed matrix interconnect topology exploration– cross-cap topology proposed to relieve latency

and data-directivity issues– matrices within islands allow efficient packing– routing between islands to be explored …

Documents

Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece Logic cells and interconnect strategies for nanoscale