Emerging Trends: Circuits in Emerging Nanotechnologies

8/10/2019 Emerging Trends: Circuits in Emerging Nanotechnologies

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Circuits in Emerging Nanotechnologies

Rinaldo Castello University of Pavia

Thomas Ernst CEA-LETI

Seok-Hee Lee SK-Hynix

Subhasish Mitra Stanford University

Ion OConnor Ecole Centrale de Lyon

Chair:Adrian Ionescu, EPFL


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Rinaldo Castello

University of Pavia


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Thomas Ernst

CEA-LETI


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FROM INTEGRATED CIRCUITS TO

INTEGRATED SYSTEMS

THOMAS ERNST

Montreux

Symposium on emerging trends in electronics

1/12/2014


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IC technology research is this the end ?

Major semiconductor suppliers' advanced CMOS logic manufacturingtechnology capability in 2011. (Source: IHS iSuppli)

No : several new market drivers Autonomous or ultra low power SoC-

SiP (IoT, ) and related servers Automotive

Health & Biochips

Google

LETI, 2014 IEEE WF on IoT

EPFL / LETI collab.

2014 IEEE Nano


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| 11

IC research technology drivers

Advanced 3D

New materials for advanced options

Low voltage (logic + memory RRAM, MRAM, NEMS RF & Switches)

Energy sources and management

Embedded optics

Embedded sensors (bio, etc. )

Safe electronics

Inexact computing

Neuromorphic

Quantum computing ?

SET, Mott , Spin,

Bio computing?

Adiabatic ? ..others

Device Centric Evolution

(scaling)

CMOS Scaling

NVM & embedded memory

RF/analog/high voltage

System centric

Heterogeneous systems

Breakthrough in data treatments

15 years

25 years

5-10 years

3 IC l i f l i hi h


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Today

The packaging evolution

Heterogeneous Era

Si/Smart Interposers

Memory on Logic

Logic on analog

MEMS on logic

RF/ANALOG

3D imagers

Biochips

0 -10 years

The alternative to More

Moore scaling

Logic-on-Logic :

(Monolithic and 3D-Stacked)

Monolithic 3D memories

PHOTONICS RF/MEMS ANALOG

Biochips

Novel substrates

3DIC evolution, for low consumption, high

performances

5- 15 yearsAdvanced concepts

O

Beyond CMOS hybridization

Bio-inspired 3D process Novel computing paradigms

Pitch ~1m

Pitch


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| 13

Some breakthroughs: toward integrated systems

How to connect /pattern heterogeneous devices at low cost with several types of

interconnections

FUSION : Embed Logic + memory + nano-systems

Source: LETI

(III-V on Si)

Source: TSMC


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E-Health

Flexible substrate integration Interco & RDL flexibles Integrated antenna on foil

U Low power: 65nm28nm FDSOI

RFID , RF supply

Biocompatibility & hermetic packagingIntgration & passivation wafer level

Ultra-small high performance passive capa3D: 1F/mm2

Collaborations: Philips, Infineon, Siemens, Sorin,

Biomerieux

STMicroelectronics


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Seok-Hee Lee

SK-Hynix


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Symposium on Emerging Trends in Electronics

Session 1 : Emerging Technologies - Circuits and Devices in the Nano Era

Panel : Circuits in Emerging Nanotechnologies

2014. 12. 1

Seok-Hee Lee

R&D Division, SK hynix

Design for

Low power & High performance DRAM


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Memory demand split across multiple sub-segments

A variety of device will appear and high performance & low power

DRAM will be needed as one of the most important roles in the system

LowerTr.Leakage(LowPower)

Low Cost

Low PowerHigh Speed

Higher Tr. Performance (High Speed)

Automotive

PC / Server Smart Devices

Wearable

Devices

DRAM


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Jox[A/cm2]

Tox []

Nitrided SiO2

Jox Limit for DRAM Tr

Jox Limit for Logic Tr

HKMG

Tox[]

Gate Length of Peripheral Tr. [nm]

[Source : ITRS 2003~2007]

Logic Tr

DRAM Tr

HKMG

25nm node

Transistor for Higher performance & Lower Power

Needs higher performance peripheral transistor for DRAM and it is affected by the slow scale-

down trend of Tox


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Low Power DRAM design Technique example

Power Gating Multi-VTH Dynamic Body Bias

ObjectiveReduce leakage currents by inserting a

switch transistor into the logic stack

Reduce leakage power where speed

is not needed by high Vt transistor

Controlling body bias, high speed &

low leakage current can be achieved

Scheme

Vdd

Logic

Cell Virtual

Ground

sleep

Vdd

Logic

Cell

Switch

Cell

LL

L

L

L

L

LL

H

L

LL

LL

L

H

High Speed, High Leakage

[Source : Low Power Design Methodology and Design Flow- JAN M. RABAEY

& M. Miyazaki e al, A 1.2GIPS/W uProc using speed-adaptive Vt CMOS]

Reduced Speed, Low Leakage

Various circuit technique is being studied for low power DRAM

Comparator

Decoder

Bias Gen.

Delay line

Clock signal

VDD VSS

LSI

Amp


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Solutions for Higher Performance & Higher Density

Density Conventional Stacking

High Density,

Low Performance

Non-StackingHigh Performance,

Low Density

Wire Bonding

Memory Requirements

. Lower Power

. Higher Performance

. Higher Density

[16Gb TSV, SK Hynix : 40nm 2Gb x 8]

Performance

Require higher speed, less I/Os scheme due to process difficulty and high cost of TSV

TSV-Stacking

High Density

High performance

Low power

but, High Cost &

Process Difficulty


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High Reliability & Low Cost DRAM

Require cost reduction through decreasing defect rate by On-Chip ECC, PPR, etc.

Item Objective Effect, Status Issues

DFR

(Design For

cell

Reliability)

Advanced Refresh RefreshCompensate Retention Time

DegradationIncrease IDD

Smart Refresh Refresh Improve LtRAS

VBB Temp Modulation Write Write Recovery Time

POD (Post Over Drive) Refresh Compensate Sensing Margin Increase IDD

On chip ECC Error Correction Area Overhead

PPR (using ARE) Error Aging Fail


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Subhasish Mitra

Stanford University


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The Next 1,000X

Subhasish Mitra

Collaborator: H.-S. Philip Wong

Department of EE & Department of CS

Stanford University


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Abundant-Data Applications

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N3XT 1,000XEnergy Efficiency

25

0 1 0 1

3D Resistive RAM

Massive storage

Carbon nanotube FET

compute elements

STTRAM

L2, L3,

Carbon nanotube FET

compute elements

1. All data act iveon-chip

2. Computation immersed in memory

3. Variability, yield, reliability

Monolithic 3D

Inter-layer vias:

1,000X TSV

density

thermal

thermal


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Carbon Nanotube FET (CNFET)

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CNT: d = 1.2nm

2 m

Gate

2 m

Gated

CNFET

Sub-litho

pitch

1. First CNFET computer

2. High-performance CNFETs

CNFET

(Stanford fab)

Si FETs

(foundries)

ION

(A

/m)

[Shulaker Nature 13, ISSCC 13, IEDM 14]


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First CNT Monolithic 3D IC

27[Wei IEDM 13, Shulaker VLSI Tech. 14, IEDM 14]

VOUT(V

)

VIN(V)0

1

2

3

0 1 2 3

Inter-layer digital circuits

Conventional vias,

no TSVs

Process temp.

< 250 oC

CN

T

Silicon FETs

Resistive RAM

CNFETs

Logic + memory

Resistive RAM


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Ian OConnor

Ecole Centrale de Lyon


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Institut des Nanotechnologies de Lyon UMR CNRS 5270 http://inl.cnrs.fr

Five Grand Challenges for Circuits in Emerging

Nanotechnologies

Prof. Ian OConnor

[email protected] des Nanotechnologies de Lyon

Universit de Lyon Ecole Centrale de Lyon
mailto:[email protected]:[email protected]:[email protected]:[email protected]


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Five grand challenges

1. Reduce energy consumption and increase energy

efficiency of data processing2. Use technology to its limit throughout its life

cycle, and ensure reliable system operation in thepresence of both unreliable devices and

increasing complexity3. Develop hardware solutions for ZB data storage

suited to the big data era

4. Develop systems adapted to new services (M2M,

IoT, cloud computing ...)5. Promote and exploit the potential of 3D

heterogeneous integration

E


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Energy @22nm

switching 1 bit in a transistor

costs:

~1-10 aJ

Moving a 1-bit data on silicon

costs:

~1 pJ/mm

>GHz switching

>G transistors/cm2

103above theoretical limit(Von Neumann-Landauer

bound)

k.T.ln(2)3 zJ (3x10-21J)

@300K

Source : R. Drechsler, U. Bremen

R li bili


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Reliability Systematic variability (e.g.

proximity effects) can becompensated physically

Random variability cannotbe compensated physically

Worsens with scaling Compensation must be built

into design

Huge challenge

3/ values for thresholdvoltage up to 80%@22nm!

Ex : lithography, mask correction

Ex : dopant concentration

2010 2013 20160

20

40

60

80

100

Variability,

3s

/m

(%)

Year

Critical DimensionsV

DD

VTH,total

VTH,dopants

M


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Memory

Cache hierarchies overcome

distant data access issues,but at the cost of high real

estate and complex

management

3D integration of dense, fast,

low-cost, non-volatile

memorytiers (RRAM,

MRAM ) could make themirrelevant

distributed memory

tiers above cores

RRAM / MRAM / SEM

processing tier:

manycore or reconfigurable

matrix

Configuration memory

also benefits


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Distributed data processing (M2M, IoT )

Ultra-low energy

embedded systems

Energy-constrained

Sense and interact with the

physical environment Real-time constraints

No intervention (intelligent,

adaptive)

Hundreds of Mbps per mobileterminal

High-performance

datacenters

Power-constrained

Handling and storage of

resulting exabytes ofdata

Security and reliability

constraints

Hundreds of Gbps pernode


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Design approaches still inthe Age of Great Explorers

Design space models

bring GPS to design!

3DICs = heterogeneity + complexity

Virtually infinite designspace

Billions of increasingly

diverse and complex

elementary devices

Nonlinear behavior of

transistors, technological

options

Multi-physics

sensors/actuators forminiaturization

Nanoscale devices for

equivalent scaling


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Circuits in Emerging Nanotechnologies

Rinaldo Castello University of Pavia

Thomas Ernst CEA-LETI

Seok-Hee Lee SK-Hynix

Subhasish Mitra Stanford University

Ion OConnor Ecole Centrale de Lyon

Chair:Adrian Ionescu, EPFL

Documents

Emerging Trends: Circuits in Emerging Nanotechnologies