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COMPANY CONFIDENTIALPAGE 1 – OCTOBER 2012 - CONFIDENTIAL
INSIGHT SIPDESIGN PROCESS
PAGE 2 – OCTOBER 2012 - CONFIDENTIAL
PCB Design - Layout
PCB Manufacturing
Board Assembly
Board Debug
3 weeks
1 week
1 week
2-4 weeks
Board Design
Typical Lead Time for 1 loop : 7-9 weeks
Multiple
Design
Loops
SIMPLE PCB DESIGN
PAGE 3 – OCTOBER 2012 - CONFIDENTIAL
SiP Design - Layout
Substrate Manufacturing
SiP Module Assembly
SiP Test
4 weeks
In paralel with
with SiP design
4 weeks
2-4 weeks
4 weeks
SiP design
Typical Lead Time for 1 loop : 14-16 weeks
One or
Two
Design
Loops
EM Simulation
SIMPLE SIP DESIGN
PAGE 4 – OCTOBER 2012 - CONFIDENTIAL
Let’s examine the situation when
the design is more complex!!!
More than 2 die, More than 400
connections
MORE COMPLEX DESIGNS
PAGE 5 – OCTOBER 2012 - CONFIDENTIAL
PCB Design - Layout
PCB Manufacturing
Board Assembly
Board Test
3 weeks
1 week
1 week
2 -4 weeks
Board Design
Typical Lead Time for 1 loop : 11-15 weeks
Multiple
Design
Loops
4-6 weeks and/or
more resources
4-6 weeks and/or
more resources
2 weeks
COMPLEX PCB DESIGN
More than 5 large LGA, BGA components, More than 500 nets
PAGE 6 – OCTOBER 2012 - CONFIDENTIAL
SiP Design - Layout
Substrate Manufacturing
SiP Module Assembly
SiP Test
4 -8 weeks
In paralel with
with SiP design
4 weeks
2-4 weeks
4-6 weeks
SiP design
Typical Lead Time for 1 loop : 14-22 weeks
One or
Two
Design
Loops
EM Simulation
COMPLEX SIP DESIGN
More than 2 die more than 400 nets Complex RF interactions
COMPANY CONFIDENTIALPAGE 7 – OCTOBER 2012 - CONFIDENTIAL
Prepare
Contract
Sign Contract
Ref Design
Schematic BoM
Proposal, Feasibility Study Report…
Contract
Customer Docs, Specifications,
Schematic Ref Design BoM…
Design Phase N
Make Protos N
Measure & Analyse
Prototypes
Schematic Layout BoM
Simulation results CDR (DRC OK) for fab
Measurement report
Analysis of results
Determine modifications for next phaseOK?
Start phase 1
Start new phase
No
Design Process
Complete
OVERALL DESIGN PROCESS
PAGE 8 – OCTOBER 2012 - CONFIDENTIAL
Sign Contract
Contract
Customer Docs
Schematic Ref Design BoM
Feasibility Study Report
Specifications
Preliminary Design report:
•Model validation
•Basic RF matching
•Layout strategy description
•Laminate Stack Up
•Schematic IPD & Laminate
Phase 1
Analyze & Simulate
RF part of reference design
Confirm split IPD/SMT
Layout strategy Laminate
Stack Up
Validate Schematic
IPD/Laminate
Analyze RF matching
From component eval boards
Confirm
Models?Y
N
Preliminary Matching Design
Pre
limin
ary
Desig
n
To 2
DETAIL DESIGN PROCESS 1
PAGE 9 – OCTOBER 2012 - CONFIDENTIAL
Data Base
Validn Report
Detailed IPD layout
RF Matching & Coupling
EM simulation
IPD + Laminate
Detailed RF Laminate layout
From 1
Perf OK?
Create SMT footprints
in EDA data-bases
Validate SMT Footprints
Cf Data sheets
OK?N
Y
YN
To 3
DETAIL DESIGN PROCESS 2
PAGE 10 – OCTOBER 2012 - CONFIDENTIAL
IPD Tapeout
Laminate DRC and CDR
Y
Base-band and power supply
Layout
EM Coupling
BB + RF IPD + Laminate
Perf OK?
Layout adjustment
for coupling
N
IPD DRC and CDR
Laminate Tapeout
Design Report:
•RF matching
•EM coupling
•Yield analysis
•IPD CDR
•Laminate CDR
•IPD GDS2
•Laminate Gerber
Monte Carlo Yield Analysis/
Corner Simulations
To 4
From 2
DETAIL DESIGN PROCESS 3
PAGE 11 – OCTOBER 2012 - CONFIDENTIAL
IPD Fab and Bumping
Laminate Fab
Prototype Assembly
Full system Prototype RF by sections + BB
Power up,
DC verification
Firmware
Power up,
DC verification
Firmware
System tests
End to End
RF characterization
Power, NF, Matching,
Gain, Filtering
From 3
To 5
DETAIL DESIGN PROCESS 4
PAGE 12 – OCTOBER 2012 - CONFIDENTIAL
Retro-simulation of RF
portion to fit
measurements
BoM adjustment
and debug
Evaluation Report
Modifications for
Phase 2
To Phase 2
Phase 1 Analysis Report
•RF Test results
•System test results
•Proposed BoM
•Modifications
•Retro-simulations
From 4
DETAIL DESIGN PROCESS 5
PAGE 13 – OCTOBER 2012 - CONFIDENTIAL
350 400 450 500 550300 600
-40
-30
-20
-10
-50
0
freq, MHz
dB
(S(1
3,1
3))
dB
(S(1
5,1
5))
dB
(S(1
7,1
7))
350 400 450 500 550300 600
30
35
40
45
25
50
freq, MHz
dB
(S(1
4,1
3))
Readout
m13
dB
(S(1
6,1
5))
Readout
m14
dB
(S(1
8,1
7))
Readout
m15
m13freq=dB(S(14,13))=43.305
434.0MHzm14freq=dB(S(16,15))=37.734
434.0MHzm15freq=dB(S(18,17))=30.848
434.0MHz
350 400 450 500 550300 600
-30
-20
-10
-40
0
freq, MHz
dB
(S(1
4,1
4))
dB
(S(1
6,1
6))
dB
(S(1
8,1
8))
-70 dBm
-50 dBm
-40 dBm
sans le SAW
freq (309.0MHz to 559.0MHz)
S(1
5,1
5)
S(1
6,1
6)
mS11LSSP_Freq=dB(S(1,1))=-8.167
4.350E8mS22LSSP_Freq=dB(S(2,2))=-8.622
4.350E8
300.M 400.M 500.M 600.M 700.M200.M 800.M
-35
-30
-25
-20
-15
-10
-5
-40
0
LSSP_Freq
dB
(S(1
,1))
Readout
mS11
dB
(S(2
,2))
Readout
mS22
LimFreq
Lim
S11
Adaptation
mS11LSSP_Freq=dB(S(1,1))=-8.167
4.350E8mS22LSSP_Freq=dB(S(2,2))=-8.622
4.350E8
Acces antenne
Sortie ampli
m2LSSP_Freq=dB(S(2,1))=44.681
4.350E8
300.M 400.M 500.M 600.M 700.M200.M 800.M
30
35
40
45
25
50
LSSP_Freq
dB
(S(2
,1))
Readout
m2
Gain Antenne -> RX
m2LSSP_Freq=dB(S(2,1))=44.681
4.350E8
m3LSSP_Freq=S(1,1)=0.403 / 93.673impedance = Z0 * (0.690 + j0.662)
4.300E8
m6LSSP_Freq=S(2,2)=0.416 / -63.282impedance = Z0 * (1.035 - j0.931)
4.100E8
LSSP_Freq (200000000.000 to 800000000.000)
S(1
,1)
Readout
m3
S(2
,2)
Readout
m6
m3LSSP_Freq=S(1,1)=0.403 / 93.673impedance = Z0 * (0.690 + j0.662)
4.300E8
m6LSSP_Freq=S(2,2)=0.416 / -63.282impedance = Z0 * (1.035 - j0.931)
4.100E8
mS11LSSP_Freq=dB(S(1,1))=-13.492
4.300E8mS22LSSP_Freq=dB(S(2,2))=-15.057
4.300E8
350.M 400.M 450.M 500.M300.M 550.M
-35
-30
-25
-20
-15
-10
-5
-40
0
LSSP_Freq
dB
(S(1
,1))
Readout
mS11
dB
(S(2
,2))
Readout
mS22
LimFreq
Lim
S11
Adaptation
mS11LSSP_Freq=dB(S(1,1))=-13.492
4.300E8mS22LSSP_Freq=dB(S(2,2))=-15.057
4.300E8
Acces antenne
Sortie ampli
m2LSSP_Freq=dB(S(2,1))=49.376
4.300E8
350.M 400.M 450.M 500.M300.M 550.M
30
35
40
45
25
50
LSSP_FreqdB
(S(2
,1))
Readout
m2Gain Antenne -> RX
m2LSSP_Freq=dB(S(2,1))=49.376
4.300E8
m3LSSP_Freq=S(1,1)=0.212 / 8.388impedance = Z0 * (1.525 + j0.099)
4.300E8
m6LSSP_Freq=S(2,2)=0.111 / -74.897impedance = Z0 * (1.035 - j0.224)
4.100E8
LSSP_Freq (300000000.000 to 550000000.000)
S(1
,1)
Readout
m3
S(2
,2)
Readout
m6
m3LSSP_Freq=S(1,1)=0.212 / 8.388impedance = Z0 * (1.525 + j0.099)
4.300E8
m6LSSP_Freq=S(2,2)=0.111 / -74.897impedance = Z0 * (1.035 - j0.224)
4.100E8
Schematic Only
Test Results
EM PCB layout + schematic+Models
Schematic only Simulation Results
EM PCB layout + schematic
+ models Results
Adjust model complexity for fit
SCHEMATIC AND EM LAYOUT
COMPANY CONFIDENTIALPAGE 14 – OCTOBER 2012 - CONFIDENTIAL
• RF matching
• IPD/SMT split
• Schematic with
split
• BoM finalized
• Stack up
finalized
PRELIMINARY DESIGN
COMPANY CONFIDENTIALPAGE 15 – OCTOBER 2012 - CONFIDENTIAL
• Compare SMT
schematic, pinouts,
layout,
– Supplier data
– ADS data base
– Allegro/mentor data
base
DATA BASE VALIDATION
COMPANY CONFIDENTIALPAGE 16 – OCTOBER 2012 - CONFIDENTIAL
• RF Design of IPD/LTCC or other
• RF simulation of Laminate/LTCC
• Yield Analysis
• Layout of IPD/LTCC
• Layout of Laminate
• EM Coupling RF to BB and RF to DC
• GDSII and Gerber files
• Design Report
0.5 1.0 1.5 2.0 2.50.0 3.0
-30
-20
-10
-40
0
freq, GHz
dB
(S(2
,1))
RV1 VCC_RF DECOUPLING C7
DETAIL DESIGN
COMPANY CONFIDENTIALPAGE 17 – OCTOBER 2012 - CONFIDENTIAL
Circuit Design
L, C, Balun…Buried Function
Design
Layout Design
S Parameters
Active Circuits
Circuit Simulation,
ADS, Designer, …EM/Circuit Simulation,
ADS, Designer, HFSS…
Layout/EM
ADS, Cadence, Designer,…
Parametrical/Mechanical
Objects
S Parameters
For Each Object
Substrate Manufacturing
Multi-layers / Thin Film
Test of
Buried FunctionsSiP Final Test
DETAIL BURIED RF FUNCTIONS
COMPANY CONFIDENTIALPAGE 19 – OCTOBER 2012 - CONFIDENTIAL
• System test– CMU200 or alternative
(Project specific)
• RF testing– RS ZVM
– SMIQ/AMIQ vector signal generators
– Cascade Probe station
– Spectrum/modulation Analyser MXA with VSA incorporated for 3G/GSM
Purpose built Cal Kit for VNA
TEST & DEBUG
COMPANY CONFIDENTIALPAGE 20 – OCTOBER 2012 - CONFIDENTIAL
THANK YOU
WWW.INSIGHTSIP.COM
To contact us:
mailto: [email protected]
Tel : +33 (0) 607 771 474 / +33 (0) 678 559 519