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in1200/04-PDS 1TU-Delft
Digital Logic
in1200/04-PDS 2TU-Delft
Unit of Information Computers consist of digital (binary) circuits Unit of information: bit (Binary digIT), e.g. 0
and 1 There are two interpretations of 0 and 1:
- as data values- as truth values (true and false)
in1200/04-PDS 3TU-Delft
Bit Strings By grouping bits together we obtain bit
strings- e.g <10001>
which can be given a specific meaning For instance, we can represent non-negative
numbers by bitstrings:0123
<00><01><10><11>
<10><00><01><11>
in1200/04-PDS 4TU-Delft
Boolean Logic We want a computer that can calculate, i.e
transform strings into other strings:1 +2 = 3 <01> <10> = <11>
To calculate we need an algebra being able to use only two values
George Boole (1854) showed that logic (or symbolic reasoning) can be reduced to a simple algebraic system
in1200/04-PDS 5TU-Delft
Boolean algebra Rules are the same as school algebra:
There is, however, one exception: x.x = x !
x+y = y+xxy = yx
Commutative Law
x(y+z) = xy + xz Distibutive Law
(x+y)+z = x+(y+z) Associative Law
in1200/04-PDS 6TU-Delft
Boolean algebra To see this we have to find out what the
operations “+” and “.” mean in logic First the “.” operation: x.y (or x y ) Suppose x means “black things” and y means
“cows”. Then x.y means “black cows” Hence “.” implies the class of objects that has
both properties. Also called AND function.
in1200/04-PDS 7TU-Delft
Boolean algebra The “+” operation merges independent
objects: x + y (or x y) Hence, if x means “woman” and y means
“man” Then x+y means “man and women” Also called OR function
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Boolean algebra Now suppose both objects are identical, for
example x means “cows” Then x.x comprises no additional information Hence
x.x = x2 = x
x +x = x
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Boolean algebra Next, we select “0” and “1” as the symbols in
the algebra This choice is not arbitrary, since these are the
only number symbols for which holds x2 = x What do these symbols mean in logic?
- “0” : Nothing- “1” : Universe
So 0.y = 0 and 1.y = y
in1200/04-PDS 10TU-Delft
Boolean algebra Also, if x is a class of objects, then 1-x is the
complement of this class It holds that x(1-x) = x -x2 = x-x =0 Hence, a class and its complement have
nothing in common We denote 1-x as xx instead of the usual xx
in1200/04-PDS 11TU-Delft
Boolean algebra A nice property of this system that we write
any function f(x) as
f(x) = a.x + b(1-x) We can show this by observing that virtually
every mathematical function can be written in polynomial form, i.e
f(x) = a0 + a1x + a2x2 +….
in1200/04-PDS 12TU-Delft
Boolean algebra Now xn = xn-1.x = xn-2.x.x = x Hence, f(x) = a0 + a1.x Let b = a0 and a = a0 + a1
Then we have f(x) = a.x + b(1-x) From this it follows that
f(0) = bf(1) = a
in1200/04-PDS 13TU-Delft
Boolean algebra So
f(x) = f(1).x + f(0).(1-x) More dimensional functions can be derived in
an identical way:
f(x,y) = f(1,1).x.y + f(1,0).x(1-y) +
f(0,1).y(1-x) + f(0,0).(1-x)(1-y)
in1200/04-PDS 14TU-Delft
Binary addition We apply this on the modulo-2 addition
xy = x(1-y) + y(1-x) = x.y +x.y
x y ⊕
0 0 01 0 10 1 11 1 0
in1200/04-PDS 15TU-Delft
Binary multiplication Same for modulo-2 multiplication
xy = x.y
x y ⊗
0 0 01 0 00 1 01 1 1
in1200/04-PDS 16TU-Delft
Functions Let X denote bitstring, e.g. <x4 x3 x2 x1 >
Any polynomial function Y=f(X) can be constructed using Boolean logic
Also holds for functions with more arguments Functions can be put in table form or in formula form
in1200/04-PDS 17TU-Delft
Gates We use basic components to represent
primary logic operations (called gates) Components are made from transistors
xy
OR
x+y xy
x.y
x x
AND
INVERT
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Networks of gates We can make networks of gates
x
y
x.y+x.y
EXOR
xy
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Sum of product form
x y f
0 0 01 0 10 1 11 1 1
f = x.y +x.y +x.y
xy
f
simplify
in1200/04-PDS 20TU-Delft
Minimization of expressions Logic expressions can often be minimized Saves components Example:
f = x.y.z + x.y.z + x.y.z + x.y.z
f = x.y(z +z) + (x +x)y.z
f = x.y.1 + 1.y.z
f = x.y + y.z
in1200/04-PDS 21TU-Delft
Karnaugh maps (1) Alternative geometrical method
00 01 11 10
00 1 1 0 1
01 1 1 0 1
11 0 0 0 0
10 1 1 1 0
x yv w
f = v.x + v.w.x + v.w.y + v.x.y
iuh
in1200/04-PDS 22TU-Delft
Karnaugh maps (2)
x y
w
v
y
x
Different drawing
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don’t cares Some outputs are indifferent Can be used for minimization
x y f
0 0 01 0 10 1 d1 1 1
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NAND and NOR gates NAND and NOR gates are universal They are easy to realize
x.y = x + y x + y = x.y
de Morgans Law
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Delay Every network of gates has delays
input
output
transition time
propagation delay
1
0
1
0time
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Packaging
Vcc
Gnd
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Making functions nand gates
time
A,B Y
delay
A
BYADD
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Functional Units It would be very uneconomical to construct
separate combinatorial circuit for every function needed
Hence, functional units are parameterized A specific function is activated by a special
control string F
in1200/04-PDS 29TU-Delft
Arithmetic and Logic Unit
F
addsubtractcompareor
f1 f0
0 00 11 01 1
A
BYF
F
F
A B
Y
F
in1200/04-PDS 30TU-Delft
Repeated operations
Y : = Y + Bi, i=1..n Repeated addition requires feedback Cannot be done without intermediate storage
of results
BYF
F
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Registers
BYF
F = storage element
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SR flip flop Storage elements are not transient and are
able to hold a logic value for a certain period of time
S R Qa Qb
0 0 0/1 1/0
0 1 0 1
1 0 1 0
1 1 0 0
R
S
Qa
Qb
in1200/04-PDS 33TU-Delft
Clocks In many circuits it is very convenient to have
the state changed only at regular points in time
This makes design of systems with memory elements easier
Also reasoning about the systems behavior is easier
This is done by a clock signalclock period
in1200/04-PDS 34TU-Delft
D flip flop D flip flop samples at clock is high and stores
if clock is low
Qn
Qn
C
D
D Qn+1
0 0
1 1
in1200/04-PDS 35TU-Delft
Edge triggered flip flops In reality most systems are built such that the
state only changes at rising edge of the clock pulse
We also need a control signal to enable a change
state change
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Basic storage element
C D
Q
C
I
O
R/W
O
C
I
R/W
time
enables a state change
in1200/04-PDS 37TU-Delft
4-bit register
C
R/W
C D
Q
I
O
C D
Q
I
O
C D
Q
I
O
C D
Q
I
O
in1200/04-PDS 38TU-Delft
Some basic circuits
Y
MPLEXm
A B
Y = A if m=1Y = B if m=0
Y
Decoder
A
Only output yA= 1, rest is 0
in1200/04-PDS 39TU-Delft
DecoderY
Decoder
A
Only output yA= 1, rest is 0
a2
a1
0
1
2
3
a1 a2 #y0 0 00 1 11 0 21 1 3
in1200/04-PDS 40TU-Delft
Multiplexer
Y
MPLEXm
A B
Y = A if m=1Y = B if m=0
y
m
a
b
in1200/04-PDS 41TU-Delft
Memory
REG1
REG2
REG3
REG4
mplex
decoder
Address
Din
Dout
R/W
in1200/04-PDS 42TU-Delft
Counter
MPLEX
INC
0001
R/W
preset
output
REG
in1200/04-PDS 43TU-Delft
Sequential circuits The counter example shows that systems have
state The state of such systems depend on the
current inputs and the sequence of previous inputs
The state of a system is the union of the values of the memory elements of that system
in1200/04-PDS 44TU-Delft
State diagrams We call the change from one state to another
a state transition Can be represented as a state diagram
S0 S1
S2
state
0 0 S00 1 S11 0 S20 0 S0
code
in1200/04-PDS 45TU-Delft
Conditional Change
S0 S1
S2
x=0
x=1
Presentstate
Nextx=0
Statex=1
S0 S1 S2
S1 S2 S2
S2 S0 S0
in1200/04-PDS 46TU-Delft
Coding of State
Presentstate
yz
Nextx=0YZ
Statex=1YZ
00 01 10
01 10 10
10 00 00
in1200/04-PDS 47TU-Delft
Put in Karnaugh map
0 0 d 1
1 0 d 1x
y
z
1 0 d 0
0 0 d 0x
y
z
Y
Z
Y = x.y + z
Z = x.y.z = (x+z).y
in1200/04-PDS 48TU-Delft
Scheme
DQ
DQ
x
Y
Z
z
y
x.y x.y+z
x+z
(x+z).y
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General scheme
Combinatorial Logic
Delay elements
Inputs Outputs
in1200/04-PDS 50TU-Delft
Procedure FST
1. Make State Diagram
2. Make State Table
3. Give States binary code
4. Put state update functions in Karnaugh Map
5. Make combinatorial circuit to realize functions