In This Lecture: Lecture 8: ROM & Programmable Logic Devices

E1.2 Digital Electronics 1 8.1 7 November 2008

Lecture 8: ROM & Programmable Logic Devices

Dr Pete SedcoleDepartment of E&E Engineering

Imperial College Londonhttp://cas.ee.ic.ac.uk/~nps/

(Floyd 10.1, 10.3 – 10.5, 11.1 – 11.3)(Tocci 12.1, 12.4, 12.5, 12.7, 12.8, 13.1 – 13.4)


In this lecture:

• Read-only memory• Implementing logic with ROM• Programmable Logic Devices• Implementing logic with PLDs• Static hazards


Memory terminology

• Memory cell: circuit that stores one bit of information• Byte: a group of 8 bits• Word: a group of n bits (usually 8 – 64)• Capacity:

4096 20-bit words = 81920 bits (written 4096x20 or 4k x 20)1 kilo (k) = 1024 = 210

1 Mega (M) = 220

1 Giga (G) = 230

• Address• Read operation• Write operation



Read-only Memory (ROM)• A ROM cell can store one bit of information• Data can be read but not changed (written)

– although some ROMs can be erased– unlike RAM, which can be read and written

• ROM is non-volatile– the data is kept even when the power supply to the circuit is

turned off– the data can be read again after the power is turned back on– unlike RAM, which is volatile

• Applications:– permanent storage of programmes for microprocessors– look-up tables of data– implementing combinational logic


A ROM device example

0 8 16 24 32 40 48 56

1 9 17 25 33 41 49 57

2 10 18 26 34 42 50 58

3 11 19 27 35 43 51 59

4 12 20 28 36 44 52 60

5 13 21 29 37 45 53 61

6 14 22 30 38 46 54 62

7 15 23 31 39 47 55 63

7

0

.

.

.

0

2} 0_

7G

OUT

MUX

BIN/1 of 8

A0

A1

A2

A5

A4

A3

.

+5 Volts64x1 bit ROM

row select decoder


• 64 x 1 bit ROM example:– 6 address inputs: half are used for selecting the row, and half for

selecting the column– the row-select decoder energises all 8 cells in one row– the column-select MUX chooses just one column signal to pass

through to the output– column lines are normally “pulled high” by resistors– a ROM cell programmed with a 0 pulls the line low


A ROM cell

• A voltage level is stored to represent a 0 or 1• If the “row-line” is addressed, the switch closes and the stored

voltage appears on the “column-line”• The switch is implemented with a transistor (typically a MOSFET)

0 or 1

Row

ColumnStora

ge


Mask Programmed ROM• In a Mask Programmed ROM (MROM):

– The data to be stored in the ROM is fixed at the time of manufacture

– The presence or absence of a wire determines whether a cell is programmed with a 0 or a 1

0

5V

row line

columnline0

stores 0 stores

1E1.2 Digital Electronics 1 8.10 7 November 2008

Programmable ROMs• MROM are inflexible – the data are fixed when the chips are

fabricated• Programmable ROMs (PROMs) can be programmed after

manufacture– A fuse is used instead of a wire link– Certain types of fuses can be reset under UV light

• Electrical Erasable PROMs (EEPROMs) use another transistor instead of a fuse

0

row line

0columnline

PROM cell EEPROM celldata stored in a

gate capacitance


Different ROM technologies


Implementing logic with ROM

• A 2n x m ROM has n inputs (the address) and m outputs• E.g.: 24 x 6

• This can be used to implement logic functions directly– connect the input signals to the address lines– programme the ROM data with the truth table

11101000Z

111011101001110010100000CBA

16x6ROM

Addr[3:0] Data[5:0]

0101010001000000

Data (hex)

0706050403020100

Addr (hex)

Truth table:

ROM contents:


Programmable Logic Devices (PLDs)

• Several different “architectures” available, but we will only look at the PAL architecture

• PAL: Programmable Array Logic

– These implement SOP expressions in canonical form

– Typically, the SOP expressions can have between 7 to 16 product terms

– Construction: a programmable AND section and a fixed OR section

• CPLD: Complex Programmable Logic Device

– Larger devices containing several PALs


PALs use programmable fuses or transistors similar to PROM

Original devices in the 1970s used fuses which could not be reset: such devices were called “one-time programmable”(OTP)

PALs and CPLDsavailable today usually use reprogrammable fuses


PAL architecture

&

&

&

&

&

&

&

&

>1

f

A0 A1 A2 A3 A4 A5 A6 A7

f A A A A A A A A= +0 1 2 4 6 1 3 4. . . . . .

A0 A1 A2 A3 A4 A5 A6 A7

All inputs and their complements are provided

To simplify the diagram, only one input line is drawn for each AND gate

A dot indicates an active connection


Detail of AND gates in PALs

1 1 1

&

≥1

A0 A1 A2 A3

f A A A= +0 1 3. .

f

1

the other input connections are

not shown


Summary of combinational logic building blocks

• Combinational: logic output is a function of the inputs – it has no memory or storage

• Gates– seven fundamental gates from which all other circuits are made– NOT, AND / NAND, OR / NOR, XOR / XNOR

• Multiplexers– act as switches to connect one output to one of a number of

input signals– can also be used to implement logic functions

• Decoders– inverted multiplexers– a demultiplexer connects one input to one of a number of outputs– also includes circuits such as binary to 7 segment decoders


• Arithmetic circuits– binary adders, comparators, multipliers– need to cope with negative numbers using signed number

representations• Programmable Logic Devices (PLDs)

– ROMs• can implement arbitrary logic functions• efficient for large combinational logic circuits

– PLAs (and CPLDs)• implement canonical SOP Boolean expressions

– Advantages of PLDs• reduction in chip count• easy to fix bugs and upgrade by reprogramming

– Disadvantages• requires programming equipment


Timing and glitches

• It takes a finite amount of time for a signal to travel through a logic gate - this is called the “propagation delay” of the gate

• This delay can cause “glitches” in signals• Example – consider this circuit which contains an inverter with a

propagation delay of 2ns

&

&

≥11

A

B

CB

B

B

2ns

There will be a 2ns window where B and B are both

low - causing a glitch


Avoiding static hazards• The case on the previous slide is an example of a static hazard

– the output of the circuit glitches when it shouldn’t change– in some circuits static hazards can cause malfunctions

• To avoid static hazards, use a Karnaugh map and add redundant groups such that all groups have some overlap

01101

11000

10110100A \ BC

Groups and do not overlap, so are potential hazards

Add the group so that all groups overlap

BA ACBC

BCACBAf ++=

ACBAf +=

Documents

In This Lecture: Lecture 8: ROM & Programmable Logic Devices