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Doctoral Thesis

GaN-based HEMTs for High Power RF Applications

Author(s): Tirelli, Stefano

Publication Date: 2014

Permanent Link: https://doi.org/10.3929/ethz-a-010220728

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GaN-based HEMTs forHigh Power RF

Applications

A dissertation submitted for the degree of

Doctor of Sciences of ETH Zurich

(Dr. sc. ETH Zurich)

presented by

Stefano TirelliMSc, University of Pisa

born on 02.07.1979citizen of Italy

accepted on the recommendation of:

Prof. Dr. C. R. Bolognesi, examinerProf. Dr. G. Meneghesso, co-examiner

Acknowledgements

Recollecting the contributions of all the people who had a role in thiswork during the last years is a challenging task. The first person to thankis my supervisor Prof. Colombo Bolognesi, who made this experiencepossible and offered his continued personal and professional supportthroughout this time. Secondly, I thank Prof. Gaudenzio Meneghesso whoagreed to review this work.

One of the main contributions to the success of this dissertation camefrom the extensive work on the epitaxial growth carried out by the peopleat the LASPE Laboratory of Prof. Grandjean, at Ecole PolytechniqueFédérale de Lausanne. In particular, I thank Lorenzo Lugani for hisdedicated effort on the MOCVD growth, as well as fruitful and stimulatingdiscussions which greatly contributed to this project. Marco Malinverniand Jean-François Carlin are also to thank for their contribution on theregrowth and MOCVD growth, respectively.

At the Millimeter-Wave Electronics laboratory, I would like to thankDr. Haifeng Sun for his training; Diego Marti for his collaboration on theGaN project and the fruitful discussions; Dr. Andreas Alt for developingthe applications for the measurement equipment as well as a solid gateprocess. Prof. Valeria Teppati deserves to be thanked for developingan innovative 94 GHz load-pull setup and for the expertise on large-signal measurements that she brought to the group. My colleagues, RalfFlückiger, Rickard Lövblom, Tamara Saranovac, Yuping Zeng, MariaAlexandrova and Dr. Olivier Ostinelli for the discussions and nice timespent together. The staff members Aldo Rossi, Hansrüdi Benedikter andMartin Lanz are also gratefully acknowledged.

At the FIRST clean room laboratory, the operating team members Dr.Otte Homan, Dr. Emilio Gini, Dr. Silke Schön, and Dr. Yargo Bonetti aregratefully acknowledged for keeping the lab up and efficiently running. Iwould also like to thank the technical team members for their help anddaily support. A collective mention goes to all the other PhD studentsworking in FIRST, from the groups of Prof. Faist, Prof. Ensslin and many

others, for the cheerful moments in the bright undergrounds of FIRSTlaboratory.

On the personal side, I would like to thank my mother and all myother relatives who offered me their support and endured these yearsspent far apart. Finally this thesis is dedicated to my supportive andpatient partner Ivana as well as the most special and beautiful thing thathappened to me in these years, our daughter Arianna.





Abstract

GaN-based high electron mobility transistors (HEMTs) have emergedas a promising technology for delivering high power at high frequency.Their use in RF power amplifiers may lead to increase efficiency andreduce energy consumption. AlGaN/GaN-based HEMTs were studiedextensively and demonstrated power densities up to 10 W/mm at 40 GHz.Since the AlInN/GaN material system was put forward in 2001, AlInN-based HEMTs have attracted intense research efforts because of theirpromise of higher power and superior scalability to higher frequency.

This work focused on the development of high-performance man-ufacturable AlInN- and AlGaN-based HEMTs for high-power applica-tions at high frequencies. In order to achieve this, the existing workflowfor GaN HEMTs was further developed. Low-damage gate recess etchand regrown contacts processes were established. Record-high cutofffrequencies in AlGaN/GaN-on-silicon HEMTs were attained thanks toprocess enhancements. Gate lengths as short as 35 nm were implemented,achieving record fT and fMAX for fully-passivated AlInN-based HEMTs.fMAX = 300 GHz was achieved on AlInN-based HEMTs with regrownohmic contacts. The main impediments to the high-power performance ofAlInN-based HEMTs were investigated in detail. Insights were providedon the physical origins of short-channel effects and gate leakage on shortgate length AlInN/GaN HEMTs. AlInN-based epitaxial layers aimed todeliver high RF powers were designed. The epitaxial growth was carriedout with state-of-the-art MOCVD process at the LASPE Laboratory of theEcole Polytechnique Fédérale de Lausanne. An extensive large-signal char-acterization was carried out by load-pull measurements. The optimizeddevices delivered high power densities at 40 GHz, and demonstratedrecord-high RF powers at 94 GHz.

Finally, the insights provided in this work allowed the design ofoptimized epitaxial layers. HEMTs fabricated on these layers are currentlyunder test. Promising results suggest a further boost in RF output powerand power-added efficiency.

RiassuntoLa tecnologia dei transistor basati su GaN riscuote oggi un forte

interesse per le alte potenze ad alta frequenza raggiungibili grazie ad essa.L’implementazione di GaN in amplificatori di potenza a radiofrequenzapuò portare a una maggiore efficienza e a una riduzione del consumoenergetico. Potenze fino a 10 W/mm a 40 GHz sono state raggiuntecon transistor ad alta mobilità (HEMT) basati su AlGaN/GaN. HEMTbasati su AlInN sono stati proposti nel 2001 e hanno destato interesse nelmondo della ricerca per la possibilità di aumentare ulteriormente potenzae frequenza di operazione.

Lo scopo di questo lavoro di tesi è stato realizzare HEMT basati suAlInN e AlGaN per applicazioni in radiofrequenza ad alta potenza. Perottenere questo risultato, il processo esistente per HEMT basati su GaNè stato ulteriormente sviluppato. Sono stati implementati processi perassottiliare la barriera selettivamente in corrispondenza del gate (gaterecess) e per realizzare contatti ohmici tramite ricrescita epitassiale. Lalunghezza dei gate è stata ridotta fino a 35 nm, raggiungendo valori recordper fT e fMAX in HEMT su AlInN passivati. Grazie ai contatti ohmiciricresciuti è stata ottenuta una fMAX di 300 GHz. Sono stati analizzatidettagliatamente i principali limiti alle prestazioni degli HEMT basati suAlInN. Sono state proposte delle interpretazioni fisiche sull’origine deglishort-channel effects e della corrente di leakage nei gate su AlInN. Sonostati progettati nuovi layer epitassiali basati su AlInN per ottenere altepotenze ad alta frequenza. La crescita epitassiale è stata effettuata con iprocessi più avanzati presso il laboratorio LASPE all’Ecole PolytechniqueFédérale de Lausanne. È stata condotta un’ampia caratterizzazione deidispositivi in ampio segnale tramite misure “load-pull”. Con i dispositivisviluppati sono state raggiunte alte potenze a 40 GHz ed è stato stabilitoun record per densità di potenza a 94 GHz.

Infine, la conoscenza accumulata durante questo lavoro di tesi hapermesso di progettare nuovi layer epitassiali ottimizzati. La caratteriz-zazione dei transistor fabbricati su questi layer è attualmente in corso.Risultati preliminari nelle misure a radiofrequenza suggeriscono un’ulte-riore aumento della densità di potenza e dell’efficienza.

1

Contents

1 Introduction 5

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Motivation and Outline . . . . . . . . . . . . . . . . . . . . 7

2 Process Development 9

2.1 Device Process . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Gate Recess . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.1 Annealed Contacts . . . . . . . . . . . . . . . . . . . 17

2.3.2 Regrown Contacts . . . . . . . . . . . . . . . . . . . 19

3 Elements of GaN-based High Electron Mobility Transistors 23

3.1 GaN-based Heterostructures . . . . . . . . . . . . . . . . . 23

3.2 GaN High Electron Mobility Transistors . . . . . . . . . . . 29

3.2.1 DC Characteristics . . . . . . . . . . . . . . . . . . . 29

2

3.2.2 2DEG Access Resistances . . . . . . . . . . . . . . . 31

3.2.3 Schottky Gates and Leakage . . . . . . . . . . . . . 34

3.2.4 Short-Channel Effects . . . . . . . . . . . . . . . . . 38

3.2.5 Trapping Effects . . . . . . . . . . . . . . . . . . . . 42

4 GaN HEMTs in Small-Signal Operation 47

4.1 Small-Signal Modeling . . . . . . . . . . . . . . . . . . . . . 47

4.2 AlGaN-on-silicon . . . . . . . . . . . . . . . . . . . . . . . . 52

4.2.1 Recessed AlGaN Devices . . . . . . . . . . . . . . . 57

4.3 AlInN-on-SiC . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.3.1 Thin-barrier HEMTs . . . . . . . . . . . . . . . . . . 66

4.3.2 Reduction of Short-Channel Effects . . . . . . . . . 71

4.3.3 Regrown Contacts Devices . . . . . . . . . . . . . . 81

4.4 Leakage in AlInN-based layers . . . . . . . . . . . . . . . . 88

5 GaN HEMTs in Large-Signal Operation 99

5.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . 99

5.1.1 Amplifier Classes . . . . . . . . . . . . . . . . . . . . 102

5.2 Large-Signal Measurements at 10 GHz . . . . . . . . . . . 106

5.2.1 Load-Line Analysis . . . . . . . . . . . . . . . . . . . 106

5.2.2 Large-Signal Measurements at 10 GHz . . . . . . . 109


5.3.1 AlN-capped HEMTs Geometry Optimization . . . 111

5.3.2 Record Performance at 40 GHz . . . . . . . . . . . . 114


5.5 Summary of Large-Signal Results . . . . . . . . . . . . . . . 118

6 Summary and Conclusion 121

2







4.2 AlGaN-on-silicon . . . . . . . . . . . . . . . . . . . . . . . . 52


4.3 AlInN-on-SiC . . . . . . . . . . . . . . . . . . . . . . . . . . 62

















2







4.2 AlGaN-on-silicon . . . . . . . . . . . . . . . . . . . . . . . . 52


4.3 AlInN-on-SiC . . . . . . . . . . . . . . . . . . . . . . . . . . 62

















3

6.1 Summary of Results . . . . . . . . . . . . . . . . . . . . . . 121

6.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Bibliography 125

List of Figures 141

List of Tables 153

List of Publications 155

Curriculum Vitae 159

4

44

1Introduction

1.1 Background

The development of semiconductor technology allowed the developmentof a huge industry and a multitude of applications that revolutionizedour daily lives. Traditionally, when one mentions of semiconductors,one thinks of silicon, which became the main work horse of modernelectronics. Silicon-based transistors have found application in a vastrange of domains, but III-V semiconductor technologies are maturing andprovide enough performance benefits to justify their adoption in special-ized functions. GaAs-based amplifiers are widely used in cellphones andRF applications. InP-based high electron mobility transistors (HEMTs)[1, 2] and heterojunction bipolar transistors (HBTs) [3, 4, 5] are the lead-ing technologies where ultra-high cutoff frequency devices are needed( fT> 300 GHz). In wireless communication, where high-power is required,GaAs transistors and Si-based laterally diffused transistors (LDMOS) havebeen challenged by the advancement of GaN-based technology [6, 7]. SiC-based devices offer an alternative to Si-based transistors in applicationswhere efficient heat dissipation and high breakdown voltage are required,thanks to the better thermal conductivity and breakdown field of SiC[8]. The performance of SiC-based devices ultimately falls short at high

6 I. Introduction

Si GaAs InP SiC GaN

EG (eV) 1.1 1.42 1.35 3.26 3.40

µ (cm2/V·s) 1500 8500 5400 700 1000-2000

vsat (107 cm/s) 1 1.3 1 2 2.5

Ebr ( × 106 V/cm) 0.3 0.4 0.5 3 3.3

κ (W/cm·K) 1.5 0.5 0.7 4.5 >1.5

εr (static) 11.8 12.8 12.5 10 9

Table 1.1: Fundamental parameters of the most widely used semiconductors:bandgap (EG), electron mobility (µ), saturation velocity (vsat), breakdownfield (Ebr), thermal conductivity (κ) and static relative dielectric constant (εr).

frequencies because of its less than optimal transport properties, howeverthis is not the case with GaN.

The main characteristics of the mentioned semiconductors are sum-marized in Table 1.1. GaN has the widest bandgap (EG) along with thehighest critical breakdown field (Ebr), and a good thermal conductivity (κ)that matches silicon. The wide bandgap allows operation at very high tem-peratures [9]. Therefore, GaN promises to deliver rugged devices whichwould be able to withstand high voltages and dissipate heat efficiently.

The superior breakdown field and saturated velocity make GaN-baseddevices capable of delivering higher RF power than GaAs and LDMOS-based technologies [10]. Power densities of 41.4 W/mm and 30.5 W/mmwere reported at 4 and 8 GHz, respectively [11, 12]. This is five to tentimes more than what was achieved with GaAs HEMTs in the S-band [13].In the Ka-band (26.5-40 GHz) AlGaN/GaN-based HEMTs devices havedemonstrated powers up to 10 W/mm at 40 GHz [14]. The high mobilityof GaN and its high critical field allows aggressive scaling of the transistorsize, which makes it the leading technology for high-power applicationsat high frequency. In the W-band (75-110 GHz), some GaN-based MMIChave been demonstrated with 1-2 W/mm [15, 16, 17]. While AlGaN/GaN

6 I. Introduction

Si GaAs InP SiC GaN

EG (eV) 1.1 1.42 1.35 3.26 3.40

µ (cm2/V·s) 1500 8500 5400 700 1000-2000

vsat (107 cm/s) 1 1.3 1 2 2.5

Ebr ( × 106 V/cm) 0.3 0.4 0.5 3 3.3

κ (W/cm·K) 1.5 0.5 0.7 4.5 >1.5

εr (static) 11.8 12.8 12.5 10 9





6 I. Introduction

Si GaAs InP SiC GaN

EG (eV) 1.1 1.42 1.35 3.26 3.40

µ (cm2/V·s) 1500 8500 5400 700 1000-2000

vsat (107 cm/s) 1 1.3 1 2 2.5

Ebr ( × 106 V/cm) 0.3 0.4 0.5 3 3.3

κ (W/cm·K) 1.5 0.5 0.7 4.5 >1.5

εr (static) 11.8 12.8 12.5 10 9





Motivation and Outline 7

HEMTs have already found their way into some niche applications, intenseresearch efforts are being devoted to the AlN/GaN [18], AlInN/GaN [19]and AlInGaN/GaN [20, 21] material systems, which enable higher carrierdensities and allow aggressive gate length downscaling to reach evenhigher frequencies of operation.

1.2 Motivation and Outline

Beside their great promise, technological issues still impede the fullexploitation of the potential foreseen for GaN-based devices. Due to thelack of native substrates, the epitaxial growth is carried out on foreignsubstrates. GaN-based epitaxial layers contain a higher defect densitycompared to other III-V material systems. Obtaining good ohmic contactson wide-bandgap materials like GaN is also a challenge. These issuesneed to be addressed with improvements in both epitaxial growth anddevice fabrication.

The purpose of this work was to improve the present GaN-basedHEMT technology, increasing maximum speed of operation and powerdensity. This dissertation addressed some specific drawbacks of GaN-based technology which demanded a better physical understanding.

AlGaN- and AlInN-based HEMTs were explored as candidates for out-standing high-power RF performance. The AlInN/GaN material systemwas then selected to develop HEMTs with high powers and frequenciesof operation. This work then set on tackling the challenges of AlInN-based HEMTs so that it could be brought from a promising technologyto one ready for marketable applications. The main shortcomings of ourGaN-based HEMTs were analyzed, providing insights on the underly-ing mechanisms that are must be tackled in order to achieve furtherperformance improvements.

The outline of the dissertation is as follows:

Chapter 2 presents the HEMT fabrication process workflow. The pro-cess steps developed in the course of this work are illustrated in detail.

8 I. Introduction

Chapter 3 provides elements on the physical operation of GaN-basedHEMTs required to interpret the results presented in the following chap-ters. A short review of the effects that mostly impairs the performance ofGaN HEMTs is presented.

Chapter 4 presents DC and small-signal RF measurements of AlGaN-and AlInN-based HEMTs. Small-signal equivalent circuit analysis is inves-tigated in detail for recessed and non-recessed AlGaN-on-silicon devices.AlInN-based HEMTs on different epilayer structures were fabricated andcharacterized comparatively. DC, small-signal as well as current collapsemeasurements on AlInN-HEMTs are reported. A short analysis of gateleakage in AlInN-based HEMTs is given, providing some insights on itsphysical origins.

Chapter 5 reports the large-signal RF performance of the optimizedAlInN-based devices. The results of load-pull measurements at 10, 40 and94 GHz are presented. Special attention is devoted to the analysis of theload-line at 10 GHz. Record performance in terms of power density isreported at 94 GHz.

Chapter 6 summarizes the achievements of this dissertation and envi-sions the future work on high-performance AlInN/GaN HEMTs.

8 I. Introduction





8 I. Introduction





2Process Development

This Chapter presents the workflow for the fabrication process used in thiswork, with focus on the newly developed process steps. The first Sectionillustrates the process steps carried out for the GaN-HEMTs fabrication.The second Section is dedicated to the process development for gaterecess and regrown ohmic contacts.

2.1 Device Process

The workflow required to fabricate an HEMT, from the as-grown epilayerto the finished device, is illustrated in Fig. 2.1. The individual processsteps are detailed below:

1a. Dicing and cleaningThe as-grown wafer is diced, cleaned and prepared for the firstlithography step. A preliminary characterization is performed mea-suring the as-grown sheet resistance and mobility.

The process continues as follows if annealed ohmic contacts are used:

2a. Ohmic contact metallization

10 II. Process Development

n++-GaN

AlN or GaN capAlInN or AlGaN barrier

AlNspacer

GaN buffer

SiC or Si substrate

Barrier

1) as-grown epilayer

3b) regrowth area recess

n++-GaN

4b) regrowth and metallization

2b) mesa isolation

4a) isolation (mesa or ion impl.)

3a) annealing

2a) ohmic metal deposition

6) gate lithograpy and liftoff

7) passivation

8a) measurement pads 8b) insulated meas. pads

BarrierBarrier

SiO2 hard mask

5) recess lithograpy and etching

Figure 2.1: HEMT fabrication process flow.


n++-GaN


AlNspacer

GaN buffer

SiC or Si substrate

Barrier



n++-GaN


2b) mesa isolation


3a) annealing



7) passivation


BarrierBarrier

SiO2 hard mask




n++-GaN


AlNspacer

GaN buffer

SiC or Si substrate

Barrier



n++-GaN


2b) mesa isolation


3a) annealing



7) passivation


BarrierBarrier

SiO2 hard mask



Device Process 11

The ohmic contact regions are patterned through optical lithography.The ohmic metal stack is evaporated and lifted off. A process usingdeep-UV contact lithography was newly implemented to achievesource-drain spacings of 0.5 µm.

3a. Annealing of the ohmic contactsOhmic contacts are rapid-annealed for 20 to 60 s at a temperatureT ≈ 850C in nitrogen atmosphere. The metals react and diffuse intothe barrier forming a ohmic contact to the 2DEG. As a consequenceof the reactions at high-temperatures, the surface morphology isstrongly degraded. Further details on the annealed ohmic contactprocess are given in Sec. 2.3.

4a. Device isolationThe isolation between different devices can be implemented intwo ways if annealed ohmic contacts are used. The first optionis with mesa etching, which electrically isolates each device byremoving 200 nm of epilayer by means of dry etching. After aphotolithography step to mask the active regions, the etching isperformed with reactive ion etching (RIE) in a Cl2-based plasma.The second option to isolate devices is by implantation of high-energy phosphorous and helium ions. The active regions are maskedby patterned photoresist. Then, P ions are first implanted with75 kV and a dose of 2 · 1012 cm−2, followed by two He ion implants,with energies of 50 and 200 kV and doses of 3.5 · 1013 cm−2 and6 · 1013 cm−2, respectively. The implants introduce defects in theepilayer down to a depth of 800 nm from the surface, making theepilayer insulating. Further details on the differences between thetwo processes can be found in Ref. [22].

Steps 2a-4a are substituted by 2b-4b if regrown ohmic contacts are imple-mented. The steps after 4b are again common to both contact implemen-tations.

2b. Mesa isolationWith regrown ohmic contacts, alignment markers fabricated with


the mesa etching step are used in the subsequent lithography steps.Ion implantation isolation produces no visible markers, and is there-fore not compatible with regrown contacts. An additional step tofabricate markers could be implemented to allow more processflexibility.

3b. Regrowth area recessTo achieve good ohmic contacts, the wide-bandgap barrier must beremoved. To this purpose, we first deposit a SiO2 hard mask overthe whole chip. The SiO2 is then patterned by photolithographywith PMMA in deep-UV (for LSD = 0.5 µm) or standard photoresist.Inside the ohmic regions defined in this way, the SiO2 mask isremoved and the epilayer etched to a depth of approximately 50 nm.This removes the large-bandgap barrier layer and provides directaccess to the 2DEG. The soft mask is then removed, while the SiO2

mask stays in place and allows selective regrowth in the etchedareas.

4b. Regrowth and metallizationA custom regrowth process using ammonia-MBE was developed byL. Lugani and M. Malinverni (LASPE Laboratory, Ecole Polytech-nique Fédérale de Lausanne). 70 nm of Si-doped GaN are grownselectively in the ohmic areas defined in step 3b. The remainingSiO2 hard mask is then removed with hydrofluoric acid (HF). Ahighly doped regrown n++-GaN layer remains only in the ohmicareas. At this point, ohmic contacts are fabricated by depositing andlifting off a Ti/Au (5/100 nm) layer, in a separate optical lithographystep. No thermal annealing step is required. Further details on theregrowth contacts are given in Sec. 2.3.

5. Gate recessA PMMA-based soft mask is used for the gate recess, when this stepis needed. The areas to be recessed, usually 50 nm wider than thetarget gate length, are defined by e-beam lithography. The etchingis performed with RIE in an ultra-low power Cl2-based chemistry.Further details are provided in Sec. sec:recessing.













Device Process 13

6. Gate lithography and liftoffThe gate is fabricated and lifted-off with a two-exposures e-beamprocess. The resist stack used is a tri-layer consisting of, from the bot-tom up, ZEP520A/polymethylglutarimide (PMGI)/ZEP520A. Thetop ZEP520A is patterned in the first e-beam lithography. A very lowexposure dose is used (≈ 0.2 µC/cm2), along with a low-contrast de-veloper consisting of a 3:2 mixture of methyl-isobutyl-ketone (MIBK)and methyl-ethyl-ketone (MEK). This first lithography defines thegate head length. Next, the PMGI is developed with a selectivedeveloper, providing the required undercut for liftoff. At this step,the bottom ZEP520A layer is uncovered for the gate foot lithography.Due to the low-dose used in the first e-beam lithography, the bottomlayer can be developed with a high contrast 1:1 isopropyl alcohol(IPA)-to-MIBK solution, without significant broadening of the gatehead opening. A low-temperature (140C) annealing is performedto shape the bottom resist, thus enabling a high gate length-to-footstem aspect ratio. A cross sectional micrograph of a gate is shownin Fig. 4.11c.

7. PassivationA 70 nm-thick layer of SiN is deposited a 300C with plasma-enhanced chemical vapor deposition (PECVD). The deposition ofSiN, as well as the surface preparation before is crucial to achievehigh reliability and low dispersion. The PECVD-plasma conditionshave an influence on the post-process sheet resistance, especiallyon the thin-barrier material. The stress in the deposited SiN layercan be controlled by mixing high (13.56 MHz) and low (380 kHz)frequency power to sustain the plasma during deposition [23]. Theuse of significant low frequency power was found to be detrimentalto the sheet carrier density in AlInN-based layers with 6 nm-thinbarriers. The deposition conditions must be thus fine-tuned for eachepilayer structure.

8a. Measurement padsTo fabricate the measurement pads, the passivation is etched awayto provide access to the ohmic contacts. When insulated metal pads


are implemented (8b. in Fig. 2.1) the passivation is removed only ina small area on top of the ohmic metal. The measurement pads sittherefore mostly on the passivation. Otherwise (8a. in Fig. 2.1), thepassivation is removed everywhere except from the area around thegate. After patterning the passivation layer, another lithography stepis performed to define the measurement pads. A Ti/Au (5/300 nm)metal stack is deposited and lifted off. At this point, the device canbe measured through coplanar probes.

2.2 Gate Recess

A gate recess process for high-performance HEMTs requires followingcharacteristics:

• Minimal increase of surface roughness.

• Low damage induced in the etched areas.

• High etch depth accuracy (≤ 1 nm).

A smooth surface and a reduced defect density are crucial becausethey may have a significant impact on current dispersion and gate leakagecurrent. Wet etching of the c-plane in wurtzite nitrides is poorly controlleddue to lack of etch-stop layers and may enhance defects in the material[24]. Dry etching is therefore a more suitable technique for the gate recess.However, the etching depth is time-controlled and strongly depends onthe conditioning of the machine and of the semiconductor surface priorto the etching. Hence, the high-accuracy requirement demands very slowetching rates. To meet this and the other requirements above, we useda very low-power Cl2-based plasma. The dry etching was carried out ata low pressure of 10 mTorr, which reduced the rate and increased theetching anisotropy. A low RIE power of 10 W was used to further slowdown the etch rate and reduce ion-induced damage.

Figure 2.2a shows the etch rate calibration for an AlGaN-on-Si epilayer.The as-grown barrier thickness and sheet resistance were 20 nm and



2.2 Gate Recess









2.2 Gate Recess







Gate Recess 15

0 40 80 120 160 200 2400

6

12

18

24

30

36AlGaN-based layer

with metal without metal

Rec

ess

dept

h (n

m)

Etch time (s)(a)

0 80 160 240 320 4000

3

6

9

12

15

18

data linear fit

Rec

ess

dept

h (n

m)

Etch time (s)

AlInN-based (Layer D)

(b)

0 4 8 12 160.00.51.01.52.02.53.03.54.0

RSH(k

Ω/

)

Recess depth (nm)

as-etchedannealed

permanentdam

age

100 nm

(c)

Figure 2.2: (a) Etch rate versus time on an AlGaN-GaN epilayer with andwithout metal on the surface. (b) Etch rate versus time on the AlInN-basedLayer D. (c) Sheet resistance as-etched (black line) and after 5s rapid anneal-ing at 500 (red line) of AlGaN-on-Si samples. The inset shows a micrographof a 15 nm-deep recess.

300 Ω/, respectively. After the recess was patterned and etched, thedepth was measured by atomic force microscope (AFM). A low etch rateof 0.16 nm/sec was established, fulfilling the requirement for etch-depthaccuracy. From the beginning of the process, a certain dead-time elapsedbefore actual recess started to take place. When metal was present on atest sample, the etching started almost immediately. On bare samples,instead, a dead-time of about 90 s before the etching started was found.This significant difference had to be taken into account when the process


(a) (b)

Figure 2.3: (a) 3D image generated from AFM scans of a 70 nm-wide, 8 nm-deep recess in a LSD = 1 µm spacing. The rough annealed ohmic contactmorphology is also visible on the sides. (b) Detailed scan of the recess area.

was used to recess the ohmic areas for the regrown contacts (see Sec. 2.3).

Recess etch was also characterized on the AlInN-based Layer D (seeTable. 4.4). Shallow recesses (≤ 5 nm) needed for this layer proved techno-logically challenging. A typical scattering ≈ 2 nm can be seen in Fig. 2.2bfor an etching time of 240 s. The etch depth was extremely sensitive on themachine and sample conditioning, and reproducibility was achieved onlyby repeating the recess calibration prior to each device process. Eventually,gate-recess of AlInN-based material did not yield promising results (seeSec. 4.3.2) and was not further developed.

On AlGaN-on-Si substrate, gate recess provided significant perfor-mance improvements and was further characterized. Dry etching-induceddamage was quantified in the following way. Transmission-line measure-ment (TLM) structures were fabricated in order to monitor the sheetresistance. The whole semiconductor surface was etched, then the TLMstructures were re-measured, obtaining a value for the sheet resistance(RSH) representative of the recess damage. In order to recover the damage,the sample were subjected to a rapid annealing for 5 s at 500C. Theresults are reported in Fig. 2.2c. Up to a recess depth of about 8 nm, theslight sheet resistance increase could be recovered by annealing. From


(a) (b)






(a) (b)





Ohmic Contacts 17

8 to 12 nm-deep recesses, RSH increased significantly but could still bepartially recovered by annealing. For recesses deeper than 13 nm, thesubstrate underwent permanent degradation. A conservative recess depthof 8 nm was thus selected, and rapid thermal annealing was performedto heal the etching-induced damage.

To ensure that the surface roughness had not excessively increased,the recess morphology was inspected by AFM,. Fig. 2.3 shows AFM scansof a 75 nm-wide, 8 nm-deep recess in a 1 µm source-drain spacing. Awide scan and a detailed one of the recess are are shown in Figs. 2.3a and2.3b, respectively. The RMS roughness was estimated to be 0.5 nm on thesurface and 0.9 nm inside the recess. This increase was deemed acceptableand did not have a major impact on the current collapse. The performanceof gate-recessed AlGaN-on-Si HEMTs is presented in Sec. 4.2.1.

2.3 Ohmic Contacts

2.3.1 Annealed Contacts

The literature on the attempts to achieve high-quality ohmic contactsto GaN is vast. In the past years, research groups have attempted toachieve low-resistance, reliable ohmic contacts with several techniques.The initial approaches involved Ti/Al-based metallizations, subsequentlyannealed at temperatures as high as 900C [25]. The process was furtherdeveloped and optimized in different ways. A gold layer was added ontop, in order to prevent Al-oxidation and reduce the metal stack resistance.A refractory-material interlayer was also added between Al and Au toprevent intermixing. Groups have experimented with interlayers of, e.g.,platinum [26], nickel [27], titanium [28], and molybdenum [29, 30].

The devices presented in this work used a metal stack of Ti/Al/Au(28/47/50 nm) and Ti/Al/Mo/Au (16/64/30/50 nm) annealed at 850Cin nitrogen atmosphere. The molybdenum-interlayer was subsequentlyintroduced to improve the surface morphology and prevent intermixing.However, the molybdenum-based interlayer was ineffective at preventing


1 µm

Cross-sectional SEM image

1 µm MolybdenumFIB cut

Oxygen TitaniumTop-view SEM image

GoldAluminumEDX

Figure 2.4: EDX measurements of an annealed Ti/Al/Mo/Au metal stackon AlInN-on-SiC layers. The leftmost micrograph shows the rough surfacemorphology and the area where the FIB cross-section is performed. On theright side, the SEM image of the cross-section (grayscale) is shown, as wellas EDX-mappings of different elements (color-coded). A higher brightnessof each image corresponds to a higher concentration of the element.

intermixing between the metals when annealed at 850C. Figure 2.4 showsenergy dispersive x-ray (EDX) analysis of an annealed Ti/Al/Mo/Aucontact. The SEM micrograph shows a rough surface morphology, com-mon to most high-temperature annealed contacts on GaN. The elementspresent in the anneales stack can be identified by their EDX emission,stimulated by the electron beam of the SEM column. The brightness of theimages in Fig. 2.4 shows the concentration of each element (color-coded).The measurements show that gold and molybdenum remain segregated,but form unwanted lumps in different regions of the contact. Titanium dif-fuses throughout the stack, while aluminum floats mostly on top, whereit oxidizes. This is shown by the increased presence of Al and O at thesurface (dark blue, Fig. 2.4). Similar interdiffusion was also reported byother groups with different metal stacks and measurement techniques[28].

The EDX measurements suggest that high-temperature annealingleads to chaotic reactions and interdiffusion inside the ohmic metal stack.As a result, the quality of the contacts and their morphology can be veryinconsistent even within the same wafer. Significant variations may also be


1 µm




GoldAluminumEDX





1 µm




GoldAluminumEDX




Ohmic Contacts 19

due to due local composition variations [31]. The fabrication conditionsneed to be carefully optimized for each wafer. However, the optimalprocessing parameters are characterized by a narrow processing window.By careful tuning of all the parameters we could achieve annealed ohmiccontacts with resistances as low as 0.35 Ω/mm. A regrown ohmic contactworkflow was then implemented, which provided a much improvedreproducibility at the expense of few extra processing steps.

2.3.2 Regrown Contacts

As shown in the previous Section, ohmic contacts on undoped GaN-HEMTs epilayers pose reliability and reproducibility concerns due to therequired high annealing temperature. Contacts to heavily n-doped GaN,instead, showed very low contact resistances with reduced annealingtemperatures [32]. Some research groups have deposited an n-GaN layeronly in the ohmic contact regions of the epilayer using epitaxial regrowth.High-speed HEMTs with regrown ohmic contacts, without any post-annealing, have been recently demonstrated [33, 34].

Our regrown-contact process was developed in collaboration withL. Lugani and M. Malinverni (LASPE Laboratory, Ecole PolytechniqueFéderale de Lausanne) who developed and carried out the MBE-regrowthstep. Several preparatory steps are required before regrowth can beperformed. As shown in Sec. 3.2.2, the large-bandgap AlGaN- or AlInN-barrier represents a major impediment for achieving low contact resis-tance. Hence, the barrier needs to be etched away in order to enabledirect contact to the GaN-buffer and the 2DEG. This was carried out asfollows. The chip was first covered with a hard mask of PECVD-depositedSiO2. A photoresist soft mask was then patterned to define the ohmiccontacts. Both the hard mask and the barrier were then etched away inthese areas, using a 2-steps dry etching process. The same low-damageprocess developed for the gate recess was employed (see Sec. 2.2) to etchinto the epilayer. The recess depth varied from 20 to 40 nm. Finally, thesoft mask was removed and the chip was cleaned and prepared for theregrowth.


Barrier

GaN buffer

n++-GaN2DEG

Ti/AuRREGRINT

e-

(a)

(b)

(c)

Figure 2.5: (a) Schematic drawing of a regrown contact cross-section, show-ing the electron conduction path from the metallization to the 2DEG. (b)Micrograph after etching the ohmic contact areas (right side), recessed by20 nm. The SiO2 mask is shown in dark grey (left side). (c) Micrograph ofthe ohmic contacts after regrowth. The n++-GaN is shown in light blue. Thedark spots are pits in the regrown layer, probably originating from defectsor impurities on the growth surface. The SiO2 mask is still visible on the left(dark grey).

The regrowth was then performed in ammonia-MBE, with a slowgrowth rate in order to achieve high doping concentrations. A 70 nm-thicklayer of n++-GaN with a very high dopant concentration (≈ 1020 cm−3)was regrown. The growth occurred selectively only in the regions wherethe SiO2 mask was removed. After the regrowth was completed, the SiO2

mask was completely removed with hydrofluoric acid-etching, leavingonly n++-GaN in the ohmic contact areas. Due to the high doping, goodohmic contacts could be achieved by metallizing these areas with a Ti/Au(5/100 nm) stack, without any post-annealing. The metallization wasdeposited and lifted off after an optical lithography step. The resultingcontact is schematically shown in Fig. 2.5a. The sheet resistance of then++-GaN-layer was 60 Ω/, while the Ti/Au metal stack had a negli-


Barrier

GaN buffer

n++-GaN2DEG

Ti/AuRREGRINT

e-

(a)

(b)

(c)





Barrier

GaN buffer

n++-GaN2DEG

Ti/AuRREGRINT

e-

(a)

(b)

(c)




Ohmic Contacts 21

gible resistance. The main contributions to the access resistance comefrom metal-regrowth interface (RREG) and the n++-GaN-2DEG interface(RINT). Process monitor measurements revealed RREG = 0.08 Ω/mm.Hence, RINT contributes more than RREG to the total contact resistance of0.25 Ω/mm. It is therefore crucial to achieve a slanted side-profile for therecess. This allows a wider contact area between the n++-GaN and theGaN buffer where the 2DEG is located, reducing RINT.

Finally, Figs. 2.5b and 2.5c show micrographs of the contact areasbefore and after regrowth. The regrown layer presented sparse hexagonalpits, probably seeded at defects or impurities on the etched areas. Alow contact resistance of 0.25 Ω/mm was consistently achieved on bothAlGaN- and AlInN-based epilayers. The process did not require any mod-ification when applied to different epitaxial layers. This demonstrates asuperior reproducibility compared to the annealed ohmic contacts process,which requires layer-by-layer optimization. Because the metallization doesnot require annealing, the surface morphology is excellent. This grants aprecise detection of the markers for e-beam lithography, improving thealignment accuracy. The potential degradation and oxidation of the GaNsurface as a consequence of the high-temperature annealing are avoided.Hence, the advantages of regrown contacts do not reside only in theachieved low-access resistances, but also on an improved versatility andreproducibility of the process. The characteristics of HEMTs fabricatedwith regrown contacts are presented in Sec. 4.3.3.


22 II. Process Development22 II. Process Development

3Elements of GaN-based High Electron

Mobility Transistors

This chapter provides the critical elements to understand GaN-basedheterostructures and devices which will be used to interpret the exper-imental data presented in the rest of this work. The first part of thischapter focuses on the crucial design aspects of GaN-based epilayersfor the fabrication of high electron mobility transistors (HEMTs). Thesecond part provides an overview of some notable features of HEMT DCoperation, and gives insights on the physical origin of the main issueslimiting their RF performance.

3.1 GaN-based Heterostructures

In order to assess the potential and, by the same token, the challengesof nitride-based material systems it is necessary to understand the pe-culiarities of the epitaxial growth of GaN-based heterostructures for thefabrication of HEMTs. Because of the significant lattice mismatch of GaNwith respect to widely used substrates like silicon and sapphire, it was notuntil recent times that researchers were able to grow smooth, low-defectGaN epilayers. The lattice mismatch of nitrides with respect to some

24 III. Elements of GaN-based High Electron Mobility Transistors

Figure 3.1: Lattice constant and bandgap of nitride compounds and someother common semiconductors. Adapted from [39].

commonly used substrates is shown in Fig. 3.1. Because of the significantmismatch, stress-mitigating layers like AlN and SiN were introduced,which eventually allowed to achieve very low defect densities on largelymismatched substrates. While the first smooth growth was obtained in1990 [35], one had to wait until 2002 for layers with dislocation densi-ties lower than 109 cm−2 to become available [36], promoting a thrivingresearch on high-mobility electron devices. With the advancement ofgrowth techniques, high-quality GaN-based heterostructures grown onsapphire, SiC and, more recently, Si<111> and Si<110>[37, 38] becameavailable.

GaN can be found in nature in both the zincblende and wurtzitephases, the latter being the most stable and most widely used for the fab-rication of HEMTs. Due to the large difference in the electronegativity ofthe Ga and N atoms, the charge distribution in the GaN lattice is stronglypolar, and the semiconductor exhibits both spontaneous and piezoelectricpolarization fields. Because of the bond asymmetry, two orientations inwurtzite GaN must be distinguished, the Ga-face and the N-face. Theseterminologies are employed to refer to which side is up along the growth









GaN-based Heterostructures 25

(a) (b)

Figure 3.2: Panel (a): Structure of GaN with relevant crystal planes. Panel(b): illustration of the Ga-face polarization. Adapted from [40, 41].

direction. The orientation determines on which side the 2-dimensionalelectron gas (2DEG) is formed. Figure 3.2a shows a representation of theGa-face oriented crystal, while Fig. 3.2b shows the basic lattice structurewith the different crystal planes in the wurtzite structure. HEMT epilay-ers commonly have the c-plane as growth-terminating plane. Because noselective wet etchants exist for c-plane GaN, an additional challenge inthe processing of electron devices is posed by its etching (see Sec. 2.2).

The spontaneous and piezoelectric polarization fields of the nitridesallow the design of epilayers with 2DEGs without the use of any doping.The 2DEG is formed at a junction between GaN and a different, nitride-based barrier material (see Fig. 3.4a). The barrier material is chosen tohave a strong polarization field, which creates the 2DEG in the underlyingGaN-layer, called the GaN buffer layer. The barrier deposited on the GaNbuffer attains a total polarization field (P), made up of two contributions:the spontaneous polarization (Psp) and the piezoelectric polarization(Ppz). These two contributions give rise to a surface charge σpol at thesurfaces and at the interface with the GaN buffer, as shown in Fig. 3.4b.For ternary compounds like Al1−xInxN and AlxGa1−xN, the magnitudeof the spontaneous polarization can be calculated by linear interpolationfrom the binary values [42], while the piezoelectric polarization depends


Figure 3.3: Spontaneous and piezoelectric polarization in Al1−xInxN andAlxGa1−xN versus composition. The substrate lattice constant is taken asthat of relaxed GaN.

on additional material parameters and on the material strain, whichoriginates mainly from the lattice mismatch of the barrier material withrespect to the relaxed GaN buffer. The piezoelectric polarization can beexpressed as [43]:

Ppz = 2· a − a0

a0

(e31 − eee·

C13

C33

), (3.1)

where a0 is the unstrained lattice constant, the exx and Cxx are composition-dependent piezoelectric and elastic constants, respectively. The layer stressin Eq. 3.1 is considered to be only tensile or compressive and equal tothe length a of the hexagonal edge measured along the a-plane (seeFig. 3.2b). In the common case of AlxGa1−xN/GaN and Al1−xInxN/GaNheterostructures the barrier is considered to be strained to match thelattice constant a = 3.189 Å of the GaN buffer. Figure 3.3 shows thetrend of the different polarization components according to the abovedefinitions. The different magnitudes of Psp and Ppz highlight the impor-tance of the choice of a barrier material and of its composition. Whilelarge lattice mismatch gives rise to intense piezoelectric polarization, itsdependence on the stress in the layer makes the 2DEG density sensi-




Ppz = 2· a − a0

a0

(e31 − eee·

C13

C33

), (3.1)





Ppz = 2· a − a0

a0

(e31 − eee·

C13

C33

), (3.1)


GaN-based Heterostructures 27

−σpol

+σsurf

−qns 2DEG

d

Charge EC

GaN

barrier+σpol

(a) (b) (c)

∆EC

∆EF

qΦS

P

Figure 3.4: Panel (a): A basic GaN epilayer for HEMTs. Panel (b): Surfaceand interface charges and (c) conduction band edge (EC) profile.

tive to all stress-releasing processes such as dislocation formation andpost-growth annealing. This proves to be a reliability concern and sourceof process variability. Therefore, barrier materials like Al1−xInxN whichattain a stronger total polarization fields even in close-to-lattice-matchedcompositions thanks to the Psp component, are increasingly employed asbetter alternatives for the fabrication of rugged HEMTs [9, 44].

In addition to the polarization field, another factor has a direct in-fluence on the density of the 2DEG: surface charges. It is generally ac-knowledged that an additional charge layer σsurf due to surface defects orvacancies is present at the surface of the epilayer. This additional sheetcharge pins the surface potential to a value of ΦS (see Fig. 3.4). Thesurface states can also act as trap states, and have a major impact onthe RF operation of the transistor (see Sec. 3.2.5). Summing up all thesecontributions, the density of the 2DEG (ns) can be expressed as[45]:

ns =σpol

q− εbarrier

d·q

(ΦS +

∆EF − ∆EC

q

), (3.2)

where q is the elementary charge of the electron, ∆EF is the offset betweenthe fermi level and the conduction band at the barrier/buffer interface,and ∆EC is the conduction band offset between the barrier and the GaNchannel/buffer. A thinner barrier leads to a reduced 2DEG density, while


Figure 3.5: Mobility components in an AlGaN/GaN epilayer structure, ∆ rep-resents the RMS roughness and λ the lateral roughness correlation. Adaptedfrom [46].

σpol is determined by polarization in the barrier and can be controlled bychoosing the alloy composition of the barrier material. One of the most im-portant parameters for HEMT epilayers is the sheet resistance (Rsh), whichcan be written in terms of 2DEG density and electron mobility (µ) asRsh = 1/(q·ns·µ). While the electron density is determined by Eq. 3.2, themobility is influenced by all the electron scattering mechanisms. The mainlimiting factor in GaN-formed 2DEGs is polar optical (PO) phonon scat-tering, which at room temperature, for ns ≈ 1013 cm−2, limits the mobilityof the 2DEG in GaN to about 2000 cm2/V·s. This is the main physicallimit which cannot be circumvented. The mobility at room temperature isfurther reduced by additional scattering mechanisms, as shown in Fig. 3.5.Below 100 K, scattering contributions from dislocations, ionized impuri-ties and surface roughness are almost temperature-independent. On thecontrary, PO scattering becomes less important in this range, playing norole in reducing the mobility below a threshold temperature. Therefore, aconstant mobility below a certain temperature is an indication that thelimiting scattering mechanisms have become dislocation, impurities orroughness. The lower the threshold temperature, the better the quality of







GaN High Electron Mobility Transistors 29

the GaN epilayer. Measuring the mobility at low temperature is thereforea practical test to check whether the room-temperature µ is limited byPO or, for example, surface or dislocation scattering. The best GaN-based2DEGs achieve µ ≈ 2000 cm2/V·s at room temperature [47]. While GaNdoes not excel in terms of absolute mobility (see 1.1), it can make up forit with high ns. This way the sheet resistance of a GaN epilayer can stillattain very low values. The best GaN epilayers achieve sheet resistancesbetween 100 and 200 Ω/, which make GaN extremely attractive for avery wide range of applications.

3.2 GaN High Electron Mobility Transis-tors

This Section focuses on some key features that impact the DC operationof GaN HEMTs. An accurate analysis and understanding of the DC andpulsed characteristics already allows to identify the main shortcomingsof a device meant to be used in RF large-signal operation.

3.2.1 DC Characteristics

The regimes of operation where the HEMTs can provide an advantage overother technologies are high-current, high-voltage RF-operation modes.Drain current densities can exceed 2 A/mm, at drain voltages higher than10 V. With significant DC powers being dissipated, the strong electric fieldand the high local temperatures involved create several non-idealitieswhich can be identified in the I-V characteristics of a device. Figure 3.6shows drain current vs. drain voltage (ID - VDS) curves for different valuesof gate-source voltage (VGS) in the ideal case (solid lines) compared tosome real measurements (dotted lines). The main differences between thestandard saturated current model, and real measurements are highlighted.Heating due to the significant DC currents can generate a drop in themaximum drain current (ID,MAX). Trapping can lead to a non-sharp tran-sition from the linear to the saturation regime (knee walkout), making the


Figure 3.6: Model (solid lines) and typical DC (dotted lines) I-V characteris-tics of a HEMT. Most of the common non-idealities in GaN-based HEMTsare highlighted.

knee voltage (Vknee) loosely defined. Short-channel effects can producefinite output conductance, and prevent a complete turn off of the transis-tor (IOFF > 0). Loss of channel control can also produce non-saturatingID with increasing drain-source voltages (VDS) for VGS values close topinch-off. In the saturated velocity (vsat) approximation, one can writeID,MAX = q·vsat·ns: it follows that achieving high maximum currentsrequire high 2DEG densities which, according to Eq. 3.2 are attainedwith stronger polarization field and thicker barriers. Beside driving highcurrents, a high-performance HEMT should provide high gain both inRF and DC mode of operation. In DC, the gain is represented by thetransconductance (gm). The saturated velocity model tells us that

gm,int =vsat·CGS

LG, (3.3)

where CGS is the gate-source capacitance, and LG is the gate length.Because CGS becomes smaller with decreasing LG, scaling down the gatelengths does not produce an increase in transconductance. In deeplyscaled gate lengths the proportionality between CGS and LG becomedominated by fringing capacitances. For this reason, in modern GaN




gm,int =vsat·CGS

LG, (3.3)





gm,int =vsat·CGS

LG, (3.3)



Semiconductor χS (eV)

Al0.3Ga0.7N 3.53

Al0.83In0.17N 2.67

GaN 4.16

AlN 2.05

Metal WM (eV)

Al 4.08

Ni 5.7

Ti 4.3

Pt 6

Table 3.1: Electron affinity and work function of some nitride semiconductorsand metals. χS of compounds were calculated from [48] using Vegard’s law.

based deep-submicron gate lengths, the maximum transconductance isbetter expressed as [41]

gm,int ≈W·vsat·ε

d, (3.4)

where W is the transistor width, and d is the distance between the gateand the 2DEG, which can be approximated with the barrier thickness.A comparison of Eqs. 3.2 and 3.4 highlights one of the trade-offs thatmust be evaluated upon the design of a GaN-based epilayer for HEMTs.Thinner barrier layers lead to higher transconductance, but then to providereduced 2DEG densities. Inspection of Eq. 3.2 reveals that the loss ofelectron density can be avoided by increasing the polarization sheet chargedensity (σpol), which is mostly a material-dependent parameter. This isone of the main reasons why research on GaN-HEMTs has increasinglyfocused on materials with strong total polarization fields even in thinnerlayers, shifting from AlGaN-based barrier layers to other nitrides likeAlInN and AlN.

3.2.2 2DEG Access Resistances

Having a 2DEG channel with high densities and mobilities is of limitedvalue if it cannot be accessed through low-resistance ohmic contacts. Thesource and drain resistances (RS and RD) have a major impact on themaximum oscillation frequency ( fMAX) and on the cutoff frequency ( fT),


2DEG

Rmet

RC

Rbar

Source DrainGate

(a) current

annealing-induced spikes

met

al a

lloy

epila

yer

EF

Rmet RC Rbar)c()b(

Metal Semiconductor

EC

non-annealed contact

EC>0

EC<0

(e.g. AlGaN)

EC(e.g. TiN)

annealed contact

lle

d e- s

tate

s

Figure 3.7: Panel (a): Scheme of the resistance network on the source-side ofan HEMT from the metallic contact to the 2DEG. contact. Panel (b): schematicconduction band diagram of non-annealed ohmic contacts. Panel (c) cross-sectional SEM micrograph of an annealed ohmic contact on an AlGaN/GaNepilayer.

and ultimately on the RF power output of a HEMT-based amplifier. Theeffect of RS is apparent on the extrinsic transconductance (gm,ext), whichcan be easily assessed through an ID vs. VGS curve, and is related to theintrinsic value of Eq. 3.4 by

gm,ext =gm,int

1 + RS·gm,int. (3.5)

A high RS value therefore reduces the extrinsic transconductance. RS andRD are also lead to an increased RON (see Fig. 3.6), and a shift of the Vknee

to higher voltages, which is detrimental to the RF power output.

In a HEMT, the total access resistance from the metallic contact to the2DEG is made up by three components, as shown in Fig. 3.7a. The totalsource or drain contact resistance consists of RS or D = RC + Rbar + Rmet,


2DEG

Rmet

RC

Rbar

Source DrainGate

(a) current


met

al a

lloy

epila

yer

EF

Rmet RC Rbar)c()b(

Metal Semiconductor

EC


EC>0

EC<0

(e.g. AlGaN)

EC(e.g. TiN)

annealed contact

lle

d e- s

tate

s



gm,ext =gm,int

1 + RS·gm,int. (3.5)





2DEG

Rmet

RC

Rbar

Source DrainGate

(a) current


met

al a

lloy

epila

yer

EF

Rmet RC Rbar)c()b(

Metal Semiconductor

EC


EC>0

EC<0

(e.g. AlGaN)

EC(e.g. TiN)

annealed contact

lle

d e- s

tate

s



gm,ext =gm,int

1 + RS·gm,int. (3.5)





where Rmet is the resistance of the metallic stack, RC is the contribution ofthe interface, and Rbar that of the barrier. To reduce the access resistanceto the 2DEG, each contribution must be minimized. To achieve low RC

the work function of the metal (WM) used for the contact has to be lowerthan the electron affinity (χS) of the barrier semiconductor, this impliesthat upon contact ∆EC = WM − χS < 0. An ohmic contact is achievedwith high-χS semiconductors (e.g. TiN), which achieve a high electrondensities at the interface, as shown in in Fig. 3.7b. However, because of thelow χS of the large-bandgap nitride compounds used as barrier materials(see Table 3.1), most of the metals give rise to blocking contacts. Thesecond component of RC is the contribution due to the resistance of thebarrier semiconductor. Because large-bandgap, undoped semiconductorsare used in barrier layers, they usually result in a high Rbar.

A common approach to achieving low RC is to perform a rapid high-temperature annealing, heating up a metal stack containing titanium andaluminum to temperatures around 850C. Reactions between the metalsand with the surface happen, forming new alloys which achieve a low RC.While the details of the formation of the contacts in this way are still notcompletely understood, it was suggested that two main mechanisms areresponsible for creating ohmic contacts with this technique [49]. On onehand, a layer of TiN forms at the interface and promotes the formation ofa highly conductive interface, as the one shown in Fig. 3.7b. The formationof TiN leaves nitrogen vacancies on the interface which create a stronglyn-doped GaN layer helping achieve a contact with low RC to TiN. Onthe other hand, metal spikes penetrate deeply into the epilayer, down toand beyond the 2DEG, thus overcoming the resistive barrier layer andeffectively reducing the total Rbar component. An example of this spikingis shown in Fig. 3.7c. While the metal resistance is usually negligiblein non-alloyed ohmics, this approach usually requires the introductionof a refractory material (Ni, Mo, W) in the ohmic metallization, whichgives rise to an increased Rmet. This problem is usually circumvented byplacing an additional metallization on top of the alloyed contacts.

High-temperature annealing often causes problems in terms of re-peatability and morphology. For this reason, regrown ohmic contacts to


EF

Metal Barrier

EC

TE

TFE

FP

φB

TATφ

FP

Figure 3.8: Schematic representation of the possible reverse conductionmechanisms through a Schottky contact. The circles represent trap states. Thegray quantities represents the band profile and the mechanism of conductionin the Frenkel-Poole case.

GaN are increasingly used, fabricated by etching away the barrier on thecontact regions, thus removing Rbar, and growing a highly doped n-GaNlayer on the GaN buffer (see Sec. 2.3).

3.2.3 Schottky Gates and Leakage

Achieving high-quality Schottky contacts to nitride-based HEMTs is cru-cial to their operation. In particular, the gate Schottky diode must showvery low reverse-bias currents and be able to withstand wide voltageswings in large-signal operation. The reverse gate current may also im-pact the amplifier power-added efficiency (PAE) in large-signal operation.Additionally, in many power-amplifier applications (e.g. RF Transmitters)the individual devices operate in Class B or Class C to increase the totalefficiency [50], the gate is therefore biased most of the time below thresh-old. For these applications the fabrication of low-leakage gate contactsis crucial to reduce energy consumption in the off-state. When the metal


EF

Metal Barrier

EC

TE

TFE

FP

φB

TATφ

FP






EF

Metal Barrier

EC

TE

TFE

FP

φB

TATφ

FP






work function is higher than the electron affinity of a semiconductor, ablocking contact with a barrier height of ΦB ≈ WM − χS is achieved. Dueto the low electron affinity of GaN-based materials used as a barrier layerin nitride HEMTs, it is easy to create a blocking contact with a barrier ofmore than 1 eV (see Table 3.1). While a high electron barrier should implyvery low reverse leakage currents, a number of non-idealities can lead tohigh leakage currents on Schottky contacts on GaN.

Figure 3.8 summarizes most of the mechanisms responsible for areverse leakage current. Thermionic Emission (TE) and Thermionic FieldEmission (TFE) require a thermal activation energy of the order of ΦB sothat an electron can travel above the barrier to the conduction band of thebarrier (TE) or reach a thinner region of the barrier and tunnel through it(TFE). Because significant barrier heights are commonly achieved in GaN-based HEMTs, these processes would require very high temperaturesand are unlikely to cause significant leakage. A high barrier also meansthat direct tunneling of electrons with energies E ≈ EF is unlikely (notshown in Fig. 3.8), because the region the electrons must tunnel throughis thick enough to prevent it. However, our group and others [51] havereported high reverse leakage currents, of IG = 1 − 102 A/cm2 for VGS <

−6 V. Therefore, additional leakage mechanisms must be taken intoaccount. This anomalously high leakage current stems most likely fromthe significant number of traps in GaN-based epilayers. Some authors haveidentified Frenkel-Poole thermionic emission (FP) as the main leakagemechanisms in Schottky contacts on GaN [51, 52, 53, 54]. This conductionmechanism assumes the existence of one or more ionized traps next to themetal-semiconductor interface. The charge of this trap causes a significantmodification of the barrier profile, shown in Fig. 3.8 (grey lines). In thiscase the electron travels easily from the metal into the potential wellcreated by the trap and from there, with an additional thermal activationenergy χFP, travels into the conduction band of the semiconductor orinto a continuum of states originated by a dislocation. The expression forFrenkel-Poole current (JFP) is given by [55]:

JFP = CEy exp

[−

q(φFP −

√qEy/πε0εS

)

kBT

], (3.6)


2DEG

Gate

Barrier

Emid Eedge

GaN buer

Schottky Contact

High eld regions

x

y

(a)

µ

(b)

Figure 3.9: Panel (a): Scheme of a Schottky contact on a GaN-based HEMTshowing the regions of high field. Panel (b): Field under the middle of thegate and at the edge, showing the different behavior with different gatelengths.

where C is a material-dependent constant, Ey is the electric field compo-nent perpendicular to the junction, and ε is the high-frequency dielectricconstant of the material. Inspection of Eq. 3.6 reveals that a logarithmicplot of JFP/Ey vs.

√Ey should show linear dependence. This behavior

is considered a signature when FP conduction dominates. An accuratecomputation of JFP requires the knowledge of the field under the gate.As will be shown in the following, the calculation of the field under thegate depends heavily on the gatelength and must be taken into carefulconsideration.

Figure 3.9a shows a typical gate on a HEMT epilayer. Two regions withwidely different vertical fields (Ey) can be identified: one in the middle ofthe gate (Emid) and one close to its edges (Eedge). Due to the well-knowneffect of bunching of the field lines around sharp corners, the field atthe edge can be much larger than that in the middle. Figure 3.9b showsthe behavior of the field at the specified points for different gate lengths,extracted from a device simulation performed with Silvaco ATLAS, whereVDS = 0 V and VGS is swept from 0 down to −10 V. The relationshipbetween VGS and Emid is linear until the threshold voltage is reached,


2DEG

Gate

Barrier

Emid Eedge

GaN buer

Schottky Contact

High eld regions

x

y

(a)

µ

(b)







2DEG

Gate

Barrier

Emid Eedge

GaN buer

Schottky Contact

High eld regions

x

y

(a)

µ

(b)







µ

µ

Figure 3.10: Vertical field (Ey) profile along the x direction, 0.5 nm below aNi-on-AlInN Schottky contact, extracted from a simulation. The differencebetween short and long gates widens as the bias becomes more negative.

i.e. around VGS = −4 V, then the behavior changes. For the longer gatesLG = 10 µm and 200 nm, Emid remains almost constant down to 10 V.For the shorter 35 nm gate, Emid reaches increasingly negative values,following the trend of Eedge. In fact, Eedge continues to increase for allgate lengths, but in the case of the shortest, 35 nm gate, this has an impactalso on the field in the center of the gate (Emid). A longitudinal profileof the vertical field is also shown in Fig. 3.10. The plot shows the fieldalong a line located 0.5 nm below the gate. The middle point of the gateis located at x = 0. Figure 3.10 shows that in the shorter gate lengths notonly the field at the edge is more intense, but even its average value overthe whole gate length. For short gates, the high field regions at the edgesstart overlapping, thus increasing also the average field under the gate.This behavior also depends strongly on the details of the shape of theedges [56]. Therefore an accurate computation of the FP leakage currentmust take into account not only the gate length and trap states, but alsothe shape of the whole gate, in particular its edges.

Some authors [56, 57] found stronger evidence of trap-assisted tun-neling (TAT) instead of FP. This leakage mechanism assumes a quasi-


(a) (b)

Figure 3.11: Panel (a): Simulated I-V characteristics of a HEMT with LG = 75nm for VGS = 0 to −6 V in 2 V steps. Panel (b): current density in the regionbelow the gate at (VGS, VDS) = (−6, 8) V. The 2DEG is located at y = 0. Thelegend shows the value of log[J/(A/cm)].

continuum of traps available for tunneling at an energy close to the Fermilevel of the metal. The electron moves from the metal to the semiconduc-tor conduction band or to a conductive dislocation state (not shown inFig. 3.8) by tunneling through one or more trap states. The calculation ofthe reverse leakage current in this case is challenging because it requiresself-consistent solution of the Schrödinger-Poisson equation, togetherwith the knowledge of the trap energies and Schottky barrier height,which are often hard to obtain. For shorter gates, a rigorous treatmentwould also involve the knowledge of the specific morphology of the gateedges, which have a major influence the electric field.

3.2.4 Short-Channel Effects

The term Short-Channel Effects (SCEs) encompasses a wide range ofphysical phenomena which arise when shrinking the lateral dimensionof a HEMT. In GaN-based HEMTs these effects become relevant at LG <

100 nm, and may become critical in devices with a source-drain separation(LSD) of less than 2 microns. SCEs usually limit the performance of a


(a) (b)







(a) (b)







(a)

(b)

Figure 3.12: Simulation of the electron concentration under a gate contactbiased in different conditions. The legend shows the value of log(ns/cm−3).Panel (a): (VGS, VDS) = (−6, 8) V. Panel (b): (VGS, VDS) = (−6, 0) V.

transistor through a reduced control of the channel as manifested by adegraded transconductance, or an incomplete pinch-off of the 2DEG. Thislast point is especially critical in GaN-based HEMTs, as an incompletepinch-off is detrimental to the large-signal performance of a device, andresults in unnecessary power consumption and reduced power output(see Chap. 5).

Figure 3.11 shows an example of SCEs in a HEMT. The I-V charac-teristics were simulated with Silvaco ATLAS for a HEMT device on an


epilayer composed of: 1.5 nm AlN / 3.5 nm Al0.87In0.13N / 1 nm AlN /2 µm GaN buffer. The total thickness of the barrier is thus d = 6 nm. ALG = 75 nm gate was centered in a source-drain spacing of 2 µm. The I-Vcurves of Fig. 3.11a show significant residual currents and finite outputconductance at VGS = −6 V. The ratio LG/d is larger that 12, well abovethe limit of 5 suggested by the standard treatment in GaAs [58]. Thissuggests that the problem lies in the backside confinement rather thantopside. For the bias of (VGS, VDS) = (−6, 8) V in Fig. 3.11b, the depletionregion reaches barely 0.03 µm into the material, and the simulation showsa finite current flowing through the buffer, indicated by the light greenregions between 0.1 and 0.2 µm under the gate in Fig. 3.11b.

The reduced extent of the depletion region is partially due to drain-induced barrier lowering (DIBL), but is also a consequence of the bandalignment in the GaN buffer. The limited impact of DIBL is suggestedby the comparison of Fig. 3.12a and Fig. 3.12b, which show the electrondensity throughout the device biased at (VGS, VDS) = (−6, 8) V, and(−6, 0) V, respectively. At VDS = 8 V, the depletion region (purple area inFig. 3.12a) reaches about 0.02 µm into the material, but also at VDS = 0 V,when DIBL is not effective, it does not extend deeper than 0.04 µminto the GaN buffer (Fig. 3.12b). For both VDS value, the 2DEG is fullydepleted, but the deeper regions of the buffer are still populated byelectrons. This indicates that the main cause of SCEs in this type ofdevice is poor backside confinement, arising from the reduced EC − EF

separation in the GaN buffer below the 2DEG. This interpretation issupported by Fig. 3.13a, which shows the EC profile of an undoped GaNlayer, exhibiting EC − EF EG/2 down to 0.2 µm under the gate.

The band alignment can be modified through several approaches,which were simulated and are shown in Fig. 3.13a. The bottom-most EC

curve was obtained with a undoped GaN buffer. The one immediatelyabove and partially overlapping was obtained with a compensated bufferdoping with a donor density (ND) and acceptor density (NA) so thatNA = ND = 1018 cm−3. Then, a p-doped buffer with NA = 0.5·1016 cm−3

was simulated. A third approach was simulated with the implementa-tion of a different buffer layer made up of only 0.05 µm of GaN and
















µ µ

Figure 3.13: Panel (a): Effect of different buffers on the conduction band(EF = 0). Panel (b): Electron concentration.

1.95 µm of Al0.04Ga0.96N. Figure 3.13b shows the electron density profileobtained in the configuration described above. The compensated bufferoffers only marginal improvement over the undoped one. More significantimprovements are provided by a p-doped buffer and, above all, by theAl0.04Ga0.96N back-barrier. These two provide a much better confinementof the 2DEG. Figure 3.14 shows the effect of the different buffers on thecurrent-voltage characteristics. Compensated doping and p-doping ofthe buffer (Figs. 3.14a and 3.14b) display reduced currents and outputconductances at VGS = −6 V (black lines of Figs. 3.14a and 3.14b), butin both cases the channel is not completely pinched off. In the case ofcompensated doping, the maximum current is also reduced, due to a re-duction of ns from 2.2·1013 cm−2 (p-doping) down to 1.65·1013 cm−2 (com-pensated doping). The best results are obtained with the Al0.04Ga0.96Nwhich achieves null residual currents at (VGS, VDS) = (−6, 8) V, withns = 2.1·1013 cm−2, and a marginal decrease in IDS,MAX with respect tothe p-doping case (Fig. 3.14a). This analysis suggests that the best ap-proach to the reduction SCEs with this layer configuration is the introduc-


(a)

(b) (c)

Figure 3.14: Simulated I-V characteristics for VGS=0 to −6 V in −2 V stepsof a HEMT with (a) p-doping (NA = 0.5·1016 cm−3), (b) compensated bufferdoping (NA = ND = 1018 cm−3), and (c) Al0.04Ga0.96N back-barrier.

tion of a back-barrier. Experimental results for some of these approacheswill be presented in Chap. 4.

3.2.5 Trapping Effects

One of the main limiting factors to high performance in GaN-basedHEMTs is the so-called “current collapse” caused by trapping effects. Tounderstand its origin, one must keep in mind that the defect densityin GaN-based heterostructures is in general much higher than in more


(a)

(b) (c)






(a)

(b) (c)






2DEG

Gate

Barrier

GaN buer

Surface Traps

Bulk Traps (barrier)

Bulk Traps (buer)

Interface Traps

Drain

(a) (b)

Figure 3.15: Panel (a): Traps around the gate regions (circles) which cancause a “virtual gate” effect when they become negatively charged. Panel(b): Model of a pulse measurements from a quiescent point Q1= (0, 0) V andQ2, in pinch-off and high VDS.

mature materials like GaAs. Surface defects like N-vacancies can alsoact as trap states [59]. For this reason, it is reasonable to expect a highdensity of electron-trapping states at the surface, in the bulk, and at theinterfaces of the epilayer. Figure 3.15a depicts such situation. The circles inFig. 3.15a represent available electronic states which can trap an electron.As a consequence of the strong fields in the vicinity of the gate of a biasedGaN HEMT electrons in the 2DEG may acquire enough energy to occupya trap state. Each state is characterized by a detrapping time τ after whichthe electron is released. A transistor operating in a large-signal RF mode,is subjected to an alternating field with a period T = 1/ f , where f isthe frequency measurement. A significant concentration of traps withtime constants τ > T/2 prevents the device from reacting effectively tothe voltage change of the alternating signal. The effect of the occupiedtraps can be interpreted as a “virtual gate” which reacts sluggishly withrespect to the variations in the gate voltage. Therefore, when the bias isremoved, it takes an additional time τ for the transistor to recover thenon-biased state. This effect lowers the maximum frequency of operationof the transistor. For this reason, current collapse is also referred to as“frequency dispersion.”


In HEMTs, the effect of collapse can be assessed with pulsed DCmeasurements, an example of which is shown in Fig. 3.15b. In this typeof measurement, the device is biased at a quiescent point Q1 for a certaintime τ1, then is it biased at a second point (VGS, VDS) for a time τ2 τ1. The second point is then swept throughout the measurement rangeand the current is measured during this bias time τ2 thus obtainingan I-V curve. Because τ2 is kept as short as possible, the I-V curve isrepresentative of the traps state at the bias Q1. A comparison betweenQ1 = (VGS, VDS) = (0, 0) V and a point Q2 = (V′

GS, V′DS) with high V′

DSand V′

GS much below the threshold voltage (VTH) gives an idea of theamount of trapping in the structure. In the case of Fig. 3.15b, the curvedtraced from the quiescent point Q2 attains lower currents at all voltages, asif the very negative voltage of the gate at Q2 had not been fully removed.Pulsing from Q1 = (VGS, VDS) = (0, 0) also allows assessing the impactof thermal effects on the transistor I-V.

From a point of view of the device development, it would be importantto be able to discern between surface traps (processing-induced) and bulktraps (growth-induced). The only way to discriminate between differentdevice regions during the pulsed measurements is to apply stress eitheronly to the drain (drain lag measurements) or only to the gate contact(gate lag measurements). The generally different responses to either drainor gate lag pulsed measurements are often linked to surface or buffertraps, respectively [60].

To understand which traps can be excited via each kind of measure-ment, field simulations were performed, showing the distribution of thefield with the device biased in condition of either drain or gate stress.The regions where the field is higher correspond to where the electronscan achieve higher kinetic energies, and thus have a higher chance ofeventual capture in a trap state. Figure 3.16 shows the results of the fieldintensity in three different bias conditions where (VGS, VDS) = (a) (−6, 8)V, (b) (6, 0) V and (c) (0, 8) V, respectively. In case (a), the electric field ishighest under the gate and tails deeply into the material at the drain-sideedge of the gate. However, cases (b) and (c) also show similar patterns. Inboth cases, a spike of high field is present at the drain-side edge of the




DSand V′







DSand V′





(a)

(b)

(c)

Figure 3.16: Field simulation of the region around the gate for different biaspoints, the legend shows the value of log(E), where E is measured in V/cm.The simulated gate has Lg = 200 nm. Panel (a): (VGS, VDS) = (−6, 8) V.Panel (b): (VGS, VDS) = (−6, 0) V. Panel (c): (VGS, VDS) = (0, 8) V.


gate, and the only notable difference between (c) and (a) is a lower fieldvalue under about half of the gate on the source side in (a). Therefore, inall cases (a,b,c) the traps under the drain side of the gate may becomeoccupied by an electron. Also, in all cases (a,b,c), the field is high in thebarrier region, along the whole surface between the gate and the drain.The traps at the surface are therefore also excited in every bias condition.We can conclude therefore that the only strategy to acquire informationabout the traps from device measurements is to compare different de-vices fabricated on the same epilayer which underwent different surfacetreatments. Drain and gate lag differential analysis cannot be considereda reliable way to discern the location of trap states.

One of the few insights that can be inferred about the trap location,is whether the traps are located either mostly under the gate or in theaccess regions between the source or drain and the gate. The surfacetraps present in these regions have the effect of making the RS and RD

increase, according to the virtual gate effect. This translates in a decreaseof the maximum gm, in accordance with Eq. 3.5, and in a shift of thethreshold voltage, according to V′

TH = VTH − ∆RS ID, where V′th is the

threshold voltage with occupied traps, and ∆RS is the increase in thesource resistance due to the surface traps, according to the virtual gateeffect. Conversely, the traps directly below the gate influence only themagnitude of VTH. However, no information can be inferred on whetherthese traps reside at the interface or in the bulk of the epilayer.

Surface traps can be “passivated” with different surface coatings andtreatments, which goal is either to shift the surface potential in order tobring the trap level below the Fermi level, or compensate surface defectslike N-vacancies [61, 62].















4GaN HEMTs in Small-Signal Operation

This chapter focuses on the DC and small-signal characterization of GaNHEMTs. While GaN HEMTs should deliver their full potential in large-signal RF operation, excellent small-signal and DC characteristics are keyprerequisites for high-power applications. DC and pulsed measurementsare used to estimate the potential RF large-signal capabilities. Assessmentof maximum operation frequencies is carried out by extraction of thecutoff frequencies from the s-parameters. A small-signal equivalent circuitcan help identify the critical aspects of the device which need to beimproved.

4.1 Small-Signal Modeling

Interpretation of the small-signal RF performance of a GaN transistor canbe assisted by an equivalent circuit which reproduces the behavior ofthe device via lumped circuit elements often linked to specific regions ofthe device. Several FET models and equivalent element extraction tech-niques were reported in the literature [63, 64, 65]. Some were specificallydeveloped for GaN HEMTs [66], often introducing additional lumped ele-ments to achieve better agreement with measured data [67]. The elements

48 IV. GaN HEMTs in Small-Signal Operation

substrate substrate

draingate

source

LS RS

RDSRGS

RG RDLG LD

CDSSCGSS

CDG

CDS

CGS gm(VGS,τ)

extrinsic elements

intrinsic elements

Figure 4.1: Small-signal equivalent circuit of a HEMT.

can be split into extrinsic and intrinsic elements, as shown in Fig. 4.1.In general, not all the extrinsic elements can be extracted from a singles-parameter measurement. Therefore thorough modeling of the device re-quires extraction techniques based on additional measurements. The mostcommon approach is the so-called cold-FET method [68] which makesuse of additional s-parameter measurements performed with VDS = 0 V.This technique was expanded to accurately model all the extrinsic para-sitic components, making use of both an Open dummy structure and acold-FET measurement sweep [69]. For device-diagnostic purposes, it isoften enough to rely on an equivalent circuit with a reduced number ofelements: while unable to achieve perfect fit to the s-parameters over thewhole frequency range, it still allows us to identify the main shortcomingsof the device, with the convenience of a simplified direct extraction of thelumped element values. For the purpose of assessing the performance ofHEMTs, the rest of the chapter will refer to the equivalent circuit shownin Fig. 4.1 [64]. In this case, before the extraction, a standard Open-Shortde-embedding is carried out on the measured s-parameters, thus remov-ing parasitics associated with measurement pads. The equivalent circuitshown in Fig. 4.1 is then used to model the device itself.


substrate substrate

draingate

source

LS RS

RDSRGS

RG RDLG LD

CDSSCGSS

CDG

CDS

CGS gm(VGS,τ)

extrinsic elements

intrinsic elements




substrate substrate

draingate

source

LS RS

RDSRGS

RG RDLG LD

CDSSCGSS

CDG

CDS

CGS gm(VGS,τ)

extrinsic elements

intrinsic elements



Small-Signal Modeling 49

gate cross-sectional area,

gate metallization resistance

source geometry,

source-side ohmic contact

drain geometry,

drain-side ohmic contact

epilayer quality

(buffer)

epilayer quality

(buffer)

buffer isolation,

pinch-off, 2DEG

confinementbarrier thickness,

electron transport properties,

gate length

epilayer quality

(electron confinement, mobility, sheet density)

gate-related capacitance,

strong bias dependencegate cross-sectional area,

strong bias dependencestrong bias dependence


gate length


pinch-off, 2DEG

gate cross-sectional area,

gate metallization resistancestrong bias dependence

drain geometry,

drain-side ohmic contact


strong bias dependence

epilayer quality

source geometry,


epilayer quality

(electron confinement, mobility, sheet density)

strong bias dependencegate metallization resistance drain-side ohmic contact

barrier thickness,

strong bias dependence

gate length

epilayer quality

source geometry,


buffer isolation,

pinch-off, 2DEG

confinementelectron transport properties,

gate length

barrier thickness,

LS RSsource geometry,Ssource geometry,

RDSRRRGS

RGgate cross-sectional area,Ggate cross-sectional area,RDLGgate cross-sectional area,Ggate cross-sectional area,

LDdrain geometry,Ddrain geometry,

CDSSCGSS

Cgate-related capacitance,Cgate-related capacitance,DGgate-related capacitance,DGgate-related capacitance,

C confinementC confinementDS confinementDS confinementCCGS gbarrier thickness,gbarrier thickness,mbarrier thickness,mbarrier thickness,(barrier thickness,(barrier thickness,VGSGSVGSV ,ττ)pinch-off, 2DEG)pinch-off, 2DEG

buffer isolation,

Figure 4.2: Main contributions to the equivalent circuit elements of Fig. 4.1.

Figure 4.2 shows the main device and epilayer characteristics asso-ciated with the circuit elements shown in Fig. 4.1. In general, most ofthe elements of the equivalent circuit are influenced by more than onephysical feature, but identifying the most relevant to each element canhelp isolate a performance bottleneck in a device.

In the following, we give a brief summary of which device aspectshould be investigated if a specific model element presents a detrimentalvalue. In the extrinsic region, the most influential parameters for theperformance of the device are the access resistances RS and RD, whichare made up of the source and drain ohmic contacts resistances, plusthe 2DEG-associated resistance of the source-gate and gate-drain regions,respectively. RG depends on the metallurgical resistivity and on the cross-section of the gate, has a significant impact on fMAX. The capacitancesCDSS and CGSS represent parasitic couplings between source, drain andgate and in first approximation can be neglected; each terminal has also acharacteristic associated inductance (LS,D,G).

The intrinsic elements are directly linked to the physical and geo-metrical features of the device active region, i.e., the region around thegate. CDS and RDS account for coupling between source and drain. RDS,in particular, is related to the residual ohmic-like conduction between


source and drain at the VGS bias used for the s-parameter measurement.For example, a low value for RDS in pinch-off condition (VGS < VTH)is a signature of prominent short-channel effects (SCEs). The intrinsictransconductance gm is mainly dependent on the transport properties(vsat) and barrier thickness (see Eq. 3.4) of the epilayer. CGD dependson the gate-drain distance and strongly on the VDS bias. At high VDS

where the channel depletion extends far toward the drain, we usuallyhave CGD CGS.

A closed-form expression for fT and fMAX is provided as a function ofthe circuit elements listed so far, in principle enabling a direct assessmentof their individual contributions. The following expression for fT allowsto identify the impact of the capacitance and other equivalent circutelements [70]:

fT =gm

2π· 1

(CGS + CGD) +(

RS+RDRDS

)(CGS + CGD) + gmCGD (RS + RD)

.

(4.1)In the above equation, the three denominator terms can be associated tothree partial delay times, which add up to τ = 1/2π fT . In the devicespresented in this chapter, the first delay term accounts for ≈ 60% of thetotal delay. The second term amounts to 5-30%, and can be neglected onlywhen RDS (RS + RD). For measurements close to pinch-off, SCEs aredetrimental to this condition and thus source of additional delay. Thethird term becomes more relevant in devices with high gm where reducingRS, RD and CGD becomes particularly relevant. The access resistancesplay a crucial role in the determination of fMAX. Analytical expressionsfor fMAX,U and fMAX,MAG can be worked out as [71]:

fMAX,MAG =fT

2√

RS+RG+RGSRDS

+ π fTCGD (RGS + RS + 2RG), (4.2)

fMAX,U =fT

2√

RS+RG+RGSRDS

+ 2π fTCGDRG

. (4.3)

fMAX has an explicit dependence on RS and RG. Because fMAX is therelevant cutoff frequency for power-related applications, it is therefore





fT =gm

2π· 1

(CGS + CGD) +(

RS+RDRDS


.


fMAX,MAG =fT

2√

RS+RG+RGSRDS

+ π fTCGD (RGS + RS + 2RG), (4.2)

fMAX,U =fT

2√

RS+RG+RGSRDS

+ 2π fTCGDRG

. (4.3)






fT =gm

2π· 1

(CGS + CGD) +(

RS+RDRDS


.


fMAX,MAG =fT

2√

RS+RG+RGSRDS

+ π fTCGD (RGS + RS + 2RG), (4.2)

fMAX,U =fT

2√

RS+RG+RGSRDS

+ 2π fTCGDRG

. (4.3)


Small-Signal Modeling 51

Barrier

2DEG

dh LG

LH

CfCh Ch

Gate

CGD

CGS

Drain

d

(a)5 10 15 20

0

20

40

60

80

100

120 Cf

Cf,q

2Ch

Cap

acita

nce

(fF)

d (nm)

(b)

Figure 4.3: (a) Schematic of the main geometrical contribution to CGS andCGD. (b) Comparison of geometrical estimation for the gate capacitance CGS

where the contribution from the foot was based on a purely geometricalapproximation (solid line) or quantum mechanical calculation (dash-dottedline). The total CGS is obtained by adding the contribution from the head(2Ch) calculated geometrically (dotted line).

imperative to achieve low contact resistance while simultaneously mini-mizing RG by means of wide gate cross-sections. However, this may comeat the expense of fT because physically enlarging the gate head increasesthe head-related contribution (Ch) contribution to CGS (see Fig. 4.3a).The geometrical origin of CGS and CGD is shown in Fig. 4.3a. In a firstapproximation, we can assume that CGS = Cf + 2Ch. Where Cf and Ch

are calculated with a parallel-plate capacitor approximation, where theplates area is that of the 2DEG-facing surfaces of the gate foot and head,and the plates of each virtual capacitor are located one at the 2DEG andthe other at the foot or head surfaces. The plates distance is taken equalto the barrier thickness (d) and head-to-channel distance (dh) for Cf andCh, respectively. The foot capacitance was alternatively derived by meansof energy balance equation in the heterostructure [72]. This derivation ismore accurate because it takes into account the physical parameters of theheterostructure, such as the widely-varying electron density ns. Calling


this capacitance Cf,q, for an epilayer structure similar to those used in thiswork, we can write:

ACf,q

=dε+

πh2

q2mGaN+

( √3πh

8qεGaN√

mGaN

)2/3

n−1/3s , (4.4)

where A is the gate foot contact area, ε, εGaN are the dielectric constantsof the barrier and of GaN, respectively, q is the electron charge, h is thereduced Planck constant, and mGaN is conduction band electron effectivemass in GaN. This formula provides a physically-sound estimation of thefoot capacitance, minus fringing effects [73]. The difference between thisestimation and a purely geometrical one is shown in Fig. 4.3b. The plotshows the gate foot capacitance calculated with a parallel-plate capacitorapproximation (Cf) and that calculated with Eq. 4.4 (Cf,q), for a gate lengthLG = 75 nm and a width W = 100 µm. An AlInN barrier with varyingthickness, and accordingly varying ns [74] is also assumed. The headcontribution, estimated geometrically for LH = 400 nm and dh = 200nm, is also plotted (dotted line). The data show that, neglecting fringeeffects, a parallel-plate capacitor approximation causes an overestimationof the foot of 5% for d = 20 nm and up to 30% for thin d = 5 nm barrier.With respect to the total capacitance, the head extension contribution is25% and 10% in 20 and 5 nm-thick barriers, respectively. These values areuseful for a practical estimation of CGS during the design and analysis ofhigh-speed HEMTs.

4.2 AlGaN-on-silicon1

This Section presents data for HEMTs fabricated on AlGaN/GaN layersgrown on high resistivity silicon substrates. The inherent limitations ofthin-barrier AlGaN/GaN HEMT structures will then justify our interestin the AlInN/GaN system. Because of their affordability, ample sup-ply and good thermal conductivity at operating junction temperatures,high-resistivity silicon (HR-Si) substrates provide a low-cost solution for

1Parts of this Section were adapted from [75] ©2010 IEEE



ACf,q

=dε+

πh2

q2mGaN+

( √3πh

8qεGaN√

mGaN

)2/3

n−1/3s , (4.4)







ACf,q

=dε+

πh2

q2mGaN+

( √3πh

8qεGaN√

mGaN

)2/3

n−1/3s , (4.4)





AlGaN-on-silicon 53

the fabrication of GaN-based power transistors in the lower microwavefrequency domain [11, 14, 43, 76]. The devices presented in this Sectiondemonstrated the highest fT ever achieved on silicon substrates at thetime of publication [75], and improved maximum oscillation frequenciesfMAX in comparison to devices previously built by our group.

T-gate HEMTs were fabricated on (Al,Ga)N/GaN HEMT layers fromNitronex Corporation. The epitaxial layers were deposited on a 100 mmfloat-zone refined HR-Si (111) substrate (10 kΩ·cm). The layer sequenceconsists of a nucleation/transition layer, a 1.7 µm GaN buffer, and a17.5 nm thick Al0.26Ga0.74N barrier followed by a 2 nm GaN cap. Thematerial showed improved mobilities (≈1500 cm2/V·s) and surface mor-phology with respect to the material previously used by our group [77, 78].Ohmic contacts were formed by a thin Ti/Al/Au ohmic metal stack of28/47/50 nm annealed at 850C. The isolation between devices wasachieved by mesa etching, as described in Sec. 2.1. Linear TLM datarevealed an ohmic contact resistance of 0.55 Ω·mm and a channel sheetresistance Rsh = 600 Ω/. Gate electrodes were defined as described inSec. 2.1 with T-head sizes of 200 and 400 nm, and footprints of 75 and100 nm. The gates were centered in source-drain spacings LSD of 1 and2 µm, respectively. The gate Schottky contact metallization consisted of a25/375 nm Ni/Au metal stack. A 100 nm-thick PECVD SiN passivationlayer was then deposited at 300C. A cross-section of the device gateregion is shown in Fig. 4.7a.

Figure 4.4 shows representative I-V characteristics for (a) 75 nm and(b) 100 nm gate transistors, respectively. The maximum drain current ID

and the measured (extrinsic) transconductance gm (at VDS = 3 V) were:705 and 750 mA/mm, and 285 and 310 mS/mm for LG = 75 and 100 nm,respectively. The lower values for the 75 nm gate are attributed to higherresistance values due to the wider source-drain spacing used (LSD = 2 µm)compared to that of the 100 nm gate (LSD = 1 µm). Complete channelpinch-off occurs at VGS = −3.5 V (75 nm) and −3.3 V (100 nm), with gatediode reverse leakage currents in the order of 0.2 µA/mm at VGD = 10 Vfor both device configurations. The increased output conductance athigher VDS in Fig. 4.4b is attributed to enhanced short-channel effects


0 1 2 3 4 5 6 70 1 2 3 4 5 60.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

-3

-2.5

-2

-1.5

-1

-0.5I D(A/mm)

VDS (V)

VGS(V) =

0

(b)(a)

Figure 4.4: I-V characteristics of AlGaN-on-silicon HEMTs on with (a) LG =

75 nm and LSD = 2 µm, and (b) LG = 100 nm and LSD = 1 µm.

associated with the smaller source-drain separation used for the 100nm gate. The off-state breakdown voltage BVGD was measured witha 1 mA/mm gate current threshold according to the current injectionmethod of [79], and is equal to 58 V and 30 V for the 75 and 100 nmHEMTs, respectively, with a reduction proportional to the reduced LSD

spacing of the latter. Additionally, 100 nm gate devices fabricated on thesame substrate but with a 4 µm source-drain distance showed off-statebreakdown voltages BVGD = 110 V with fT = 78 GHz, amounting toan fT × BVGD product of 8.58 THz-V, only marginally lower than thepreviously published 12.9 THz-V reported by Onojima et al. on SiC [80].Figure 4.5 shows the cutoff frequency extraction at the peak fT (Figs. 4.5aand 4.5b). At higher VDS voltages (Figs. 4.5c and 4.5d), the reduction ofCGD allows reaching higher fMAX = 150 GHz with a marginal drop in fT

caused by the diminishing gm at higher VDS bias.

The results of small-signal equivalent circuit extraction are shown inFig. 4.6. The values of the gate capacitances CGS and CGD are shown inFig. 4.6a-b and Fig. 4.6e-f as a function of both VGS and VDS. A compari-son of Figs. 4.6a and 4.6e, reveals a lower CGS value for the shorter gate,and a lower CGD (Figs. 4.6b and 4.6f) for the wider LSD. CGD drops for


0 1 2 3 4 5 6 70 1 2 3 4 5 60.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

-3

-2.5

-2

-1.5

-1

-0.5

I D(A/mm)

VDS (V)

VGS(V) =

0

(b)(a)








0 1 2 3 4 5 6 70 1 2 3 4 5 60.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

-3

-2.5

-2

-1.5

-1

-0.5

I D(A/mm)

VDS (V)

VGS(V) =

0

(b)(a)







AlGaN-on-silicon 55

10

20

30

40

1 10 100

10

20

30

40

LG= 100 nm L

SD= 1 µm

VDS= 2.5 V

VGS= -2 V

Gain(dB)

VDS= 3 V

VGS= -2.6 V

fT= 101 GHz

fMAX(U)

= 128 GHzfMAX(MSG)

= 128 GHz

fT= 107 GHz

fMAX(U)

= 112 GHzfMAX(MSG)

= 128 GHz

LG= 75 nm L

SD= 2 µm

(a) (b)

|h21|2

MSG

U

VDS= 6.5 V

VGS= -2.2 V

(d)

Gain(dB)

Frequency (GHz)

(c)VDS= 5 V

VGS= -2.5 V

fT= 100 GHz

fMAX(U)

= 128 GHzfMAX(MSG)

= 148 GHz fMAX(MSG)

= 150 GHzfMAX(U)

= 150 GHz

fT= 90 GHz

1 10 100

Figure 4.5: Small-signal measurement and cutoff frequency extraction ofHEMTs with LG = 75 nm, LSD = 2 µm and LG = 100 nm, LSD = 1 µm, forpanels (a,c) and (b,d), respectively. Panel (c) and (d) show data at higher VDS

bias, corresponding to the peak fMAX.

increasing VDS bias, and displays vertical level curves, due to a weak de-pendence on VGS. An inspection of RDS gives insights about the channelcontrol capabilities of the two HEMTs. A comparison of Figs. 4.6d and4.6h shows that the smaller LSD spacing of the second device leads togenerally lower values of RDS, an indication of SCEs, presumably due toelectrons tailing in the deeper region of the GaN buffer (see Sec. 3.2.4).For VGS = 0.8VTH RDS reaches much higher values due to the improvedchannel control achieved with the longer gate length. Finally, CDS is foundto have a weak bias dependence, with only minor differences betweenthe two geometries, indicating that it is mainly dependent on materialcharacteristics or pad layout. The fMAX/ fT ratio reported in this Section


LG = 75 nm and LSD = 2 µm


Figure 4.6: Equivalent circuit elements extracted at different bias points. VGS

was normalized to the threshold voltage VTH = −3.3 and −3.5 V, for thedevice with LG = 75(a-d) and 100 nm(e-h), respectively.











AlGaN-on-silicon 57

superseded previous records achieved on HR-Si substrates by our group[77]. Maintaining a high fMAX/ fT ratio while increasing fT is difficult be-cause fMAX ≈ ( fT/RGCGD)

1/2 (see Eq. 4.3), thus implying that fMAX/ fT

should scale as ≈ f−1/2T . The peak fT = 107 GHz with the LG = 75 nm

gate HEMT was the highest cutoff frequency value reported at the timeof publication for fully-passivated AlGaN/GaN or AlInN/GaN HEMTson HR-Si. These results strengthened the notion that HR-Si substratessuffer little or no small-signal performance shortcomings compared tosemi-insulating substrates, as demonstrated in [81]. The performance wasfurther ameliorated by improving channel control through a gate recess,as shown in the next Section.

4.2.1 Recessed AlGaN Devices

According to Eq. 3.4, reducing the barrier thickness of a GaN-based HEMTlayer is an effective way to improve the transconductance of a transistor.However, reducing the barrier thickness causes a drop in electron density(Eq. 3.2), which leads to a diminished extrinsic transconductance (Eq. 3.5)because of higher access region resistance. It is therefore beneficial toreduce the barrier thickness only under the gate. This was achieved byimplementing a gate recess process by means of a time-controlled dryetching. The lack of selective wet-etchants for GaN-based layers makes atime-controlled dry-etching the only viable way to achieve a controlledand morphologically smooth recess on GaN HEMTs. A highly accuraterecess technique was developed, the details of which are presented inSec. 2.2.

This Section presents data for AlGaN/GaN-on-Si HEMTs based onthe same epilayer structure descibed in Sec. 4.2. Further processing refine-ments allowed achieving a lower post-process Rsh = 380 Ω/ with thesame contact resistance RC = 0.5 Ω/mm. The HEMTs presented in thisSection have LG = 75 nm, LH = 400 nm, LSD = 2 µm, W = 100 µm. A100 nm-wide recess was patterned with an additional e-beam step priorto gate deposition and etched to a depth of 8 nm, thus leaving a barrierthickness d ≈ 12 nm. The gate-to-recess alignment was performed in the


(a)

100

200

300

400

500

-4 -3 -2 -1 00

150

300

450

600

750

gm

g m (m

S/m

m)

VDS

= 3 V

(c)

(b)

VTH

Non-Recessed Recessed

I D (m

A/m

m)

VGS (V)

Figure 4.7: (a) Cross-sectional scanning electron micrographs of a LG =

75 nm non-recessed device (top) and a recessed one (bottom). The recesswidth was 200 nm. Comparison of (b)gm and (b)ID for devices with identicalgeometries (LSD = 2 µm).

e-beam lithography step, and was found to be accurate within ±25 nm.Cross-sectional micrographs of both non-recessed and recessed HEMTsare shown in Fig. 4.7a. Figure 4.7b shows the effect of the recess on thetransconductance and drain current of the transistor. gm increased from320 to 490 mS/mm, while the threshold voltage became more negativeby about 1 V. The slight discrepancy in IDS,MAX was attributed to minordifferences in the sheet densities of the two devices. In addition to the ben-eficial increase in transconductance, the turn-on characteristic of Fig. 4.7cshow that gm peaked at corresponding ID = 180 and 300 mA/mm, inthe non-recessed and recessed device, respectively. The recessed device istherefore better apt to deliver high powers at its maximum gain, thanksto a higher average ID around the peak gm. Figure 4.8a shows the I-Vcharacteristics of the recessed device. The low-damage etch process did


(a)

100

200

300

400

500

-4 -3 -2 -1 00

150

300

450

600

750

gm

g m (m

S/m

m)

VDS

= 3 V

(c)

(b)

VTH


I D (m

A/m

m)

VGS (V)





(a)

100

200

300

400

500

-4 -3 -2 -1 00

150

300

450

600

750

gm

g m (m

S/m

m)

VDS

= 3 V

(c)

(b)

VTH


I D (m

A/m

m)

VGS (V)




AlGaN-on-silicon 59

0 1 2 3 4 5 6 7 80.0

0.2

0.4

0.6

0.8

1.0

1 10 100

5101520253035404550

1 10 100

(a)

-2 V

-1 V

VGS

= 0 V

I D (A

/mm

)

VDS (V)

Gai

n (d

B)

U

MSG

|h21

|2fMAX(MSG)

= 130 GHz

fMAX(U)

= 140 GHz

fT = 110 GHz

VDS

= 1.5 VVGS

(c)(b)

Frequency (GHz)

fMAX(MSG)

= 170 GHz

fMAX(U)

= 170 GHz

fT = 83 GHz

VDS

= 9.5 VVGS

Figure 4.8: I-V Characteristics for VGS = 0 to −3 V in 1 V steps (a). Small-signal extraction for two different bias points, corresponding to the highestfT (b) and fMAX (c), respectively. The device had LG = 75 nm, LH = 400 nm,LSD = 2 µm, W = 100 µm d = 12 nm (8 nm recess).

not cause a permanent reduction of nS, therefore no drop of IDS,MAX of anon-recessed device was reached at VGS = 0 V (see Fig. 4.4). Figures 4.8band 4.8c show the highest fT and fMAX, respectively, measured on re-cessed HEMTs. Process improvements led to a marginal increase of themaximum fT compared to non-recessed devices, while fMAX improvedby a wider margin at high VDS bias. Figure 4.9 shows the extracted fMAX


2 4 6

−2.6

−2.4

−2.2

−2

−1.8

−1.6

VDS (V)

V GS (V

)

90

100

100

110

110

120

120120130

130

130

140

140

2 4 6 8 10 12−2

−1.5

−1

−0.5

0

VDS (V)10

30

30

30 30

50

50

50

50

50 5070

70

70

70

7070 70

909090

90

90

90

9090

110110110

110

110

110110

130130130

130

130

130 130

140140140

140

140140

150150

150

150150

160160

160160

170

(a) (b)

Figure 4.9: fMAX extracted from U at different bias for HEMTs: (a) non-recessed LG = 100 nm, (b) recessed (depth: 8 nm) LG = 75 nm.

in a wide bias range for a non-recessed and recessed device, respectively.The non-recessed device (Fig. 4.9a) shows lower fMAX values peaked atVDS = 6 V then rapidly decreasing at higher drain bias. The recessed de-vice (Fig. 4.9b) shows improved fMAX values, increasing up to VDS ≈ 10 V.

Additional insight can be obtained comparing the small-signal param-eters extraction of identical devices with (Fig. 4.10) and without recess(Figs. 4.6a-d). CGS and CGD scale with d and LSD, respectively, as ex-plained in Sec. 4.1. The beneficial effect of recessing is mostly apparent inthe RDS values. Thanks to the more favorable LG/d ratio, the pinch-off issharper and the residual current has a weaker dependance on VDS. Thisleads to higher RDS values with respect to the non-recessed device (seeFigs. 4.6a and 4.10). An higher RDS is beneficial to fMAX (Eq. 4.3) and to alimited extent also to fT.

In conclusion, gate recessing in AlGaN-on-silicon HEMTs was provento provide ample benefits to the HEMT performance. However, the pro-cess involves some drawbacks. Because the dry-etching process of therecess is time controlled, achieving an accuracy of 1 nm in the etch-


2 4 6

−2.6

−2.4

−2.2

−2

−1.8

−1.6

VDS (V)

V GS (V

)

90

100

100

110

110

120

120120130

130

130

140

140

2 4 6 8 10 12−2

−1.5

−1

−0.5

0

VDS (V)10

30

30

30 30

50

50

50

50

50 5070

70

70

70

7070 70

909090

90

90

90

9090

110110110

110

110

110110

130130130

130

130

130 130

140140140

140

140140

150150

150

150150

160160

160160

170

(a) (b)






2 4 6

−2.6

−2.4

−2.2

−2

−1.8

−1.6

VDS (V)

V GS (V

)

90

100

100

110

110

120

120120130

130

130

140

140

2 4 6 8 10 12−2

−1.5

−1

−0.5

0

VDS (V)10

30

30

30 30

50

50

50

50

50 5070

70

70

70

7070 70

909090

90

90

90

9090

110110110

110

110

110110

130130130

130

130

130 130

140140140

140

140140

150150

150

150150

160160

160160

170

(a) (b)





AlGaN-on-silicon 61

Figure 4.10: A subset of small-signal equivalent circuit elements of a recessedAlGaN/GaN HEMT, extracted at different bias points. VGS was normalizedto the threshold voltage VTH = −2 V.

ing depth requires an extremely accurate calibration and control of theetching conditions. This is challenging in both research laboratories andlarge-scale production facilities. In addition, SCEs are diminished butnot completely eliminated by the recess. Therefore, ultra-small gates(LG < 75 nm) are still non practical. A good channel control at thosegate lengths would require a recess deeper than 8 nm, with a subsequentdegradation of the channel resistance (see Sec. 2.2). This is where theAlGaN-based technology finds some of its most serious shortcomings.The need of thinner barriers motivates exploring heterostructures withstronger polarization fields like AlInN, presented in the next Section.


Layer A

2 nm GaN (cap)8 nm Al13In87N (barrier)1 nm AlN (spacer)2 µm GaN (buffer)

70 nm AlN (transition)

Table 4.1: Heterostructure of Layer A, from top to bottom. The structuredisplayed as-grown nS = 2.3 · 1013 cm−2 and µ = 1430 cm2/V·s from Hallmeasurements. The layers were grown on semi-insulating SiC.

4.3 AlInN-on-SiC2

Since Kuzmik’s original proposal a decade ago [19], AlInN barrier layersevolved as a promising alternative for the implementation of thin-barrierGaN HEMTs. AlInN/GaN HEMTs have been demonstrated with barriersas thin as 3 nm [83], opening the possibility to maintain favorable gateaspect ratios LG/d down to extremely short gate lengths without the needof a gate recess. The predominance of spontaneous over piezoelectric po-larization in AlInN/GaN HEMTs (see Fig. 3.4) makes them less sensitiveto potential reliability limitations involving stress-related mechanisms[44, 84]. Our group previously demonstrated AlInN/GaN HEMTs withfT = 205 GHz [85], a benchmark achieved by selectively removing theSiN passivation film around the gate electrode to minimize parasitics.While the characterization of such unpassivated transistors may wellbe of interest for demonstrations of the ultimate transistor performancewith a reduced total gate capacitance CGS + CGD, it remains that practicaltransistors must however be passivated for reliability reasons [86], aswell as to control the effects of surface states [87]. The HEMTs reportedin this Section were fabricated on a AlInN-based heterostructure witha total surface-to-channel distance d = 11 nm (Layer A). The completeepilayer structure is listed in Table 4.1. Ohmic contacts were formed by



Layer A




4.3 AlInN-on-SiC2




Layer A




4.3 AlInN-on-SiC2



AlInN-on-SiC 63

0 1 2 3 4 5 6 7 8 9 10

0.4

0.8

1.2

1.6

2.0

2.4I D(A/mm)

VDS (V)

VGS= 0 V to -8 V

in -1 Vsteps

(a)

-7 -6 -5 -4 -3 -2 -1 00.0

0.5

1.0

1.5

2.0

2.5

VGS (V)

VDS= 4 V

0

100

200

300

400

500

g m(m

S/mm)

I DS(A/mm)

(b)

(c)

Figure 4.11: (a) I-V characteristics of a HEMT fabricated on Layer A with:LG = 30 nm, LH = 400 nm, LSD = 1 µm, W = 100 µm. (b) Transconductanceand ID vs. VGS plot. (c) FIB cross-section micrograph of the active region.

Ti/Al/Mo/Au (16/64/30/50 nm) evaporation and rapid thermal anneal-ing at 860C. Linear TLM post-process data revealed a contact resistanceof 0.3 Ω·mm and a sheet resistance Rsh = 180 Ω/. Device isolationwas achieved by ion implantation of P/He as described in Sec. 2.1. Thegate contact was fabricated with an improved e-beam lithography processallowing the liftoff of a wide cross-section gate with a 30 nm footprintand a high gate stem-to-gate length aspect ratio (Fig. 4.11c). The Schottkymetal stack consisted of Ni/Pt/Au (5/30/350 nm). Figure 4.11a showsrepresentative I-V characteristics for the device, revealing an on-resistanceRON = 1.1 Ω/mm, two thirds of which arise from the Ohmic contacts.


0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

-6 V

-3 V

I D (A

/mm

)

VDS (V)

ID,(0,0)

- ID,(-8,8)

VGS

= 0 V

(a)

2 4 6 80

20

40

60

80

100

0 V -3 V -6 V

I (0,0

)- I(-

8,8)

( % o

f I(0

,0) )

VDS (V)

VGS

=

(b)

Figure 4.12: (a) Pulsed I-V characteristics for the same device of Fig. 4.11,where VGS = 0, 3 and −6 V, respectively, with a quiescent point of(VGS, VDS) = (0, 0) V (solid line) and (−8, 8) V (dashed line), respectively. (b)Relative dispersion calculated as a percentage of ID lost between the sametwo quiescent points.

The drain current density peaks at 2.18 A/mm at VGS = 0 V, with almosta three-fold increase with respect to the AlGaN HEMTs presented inSec. 4.2. The I-V characteristics also do not present the marked drop inID for increasing VDS, as opposed to the AlGaN-on-Si HEMTs of Figs. 4.4and 4.8a. The ID drop seen in the latter is attributed to heating andtrapping-effects, which seem to be less pronounced in AlInN-on-SiCHEMTs, owing to the higher thermal conductivity of the substrate andsmaller lattice mismatch which may lead to less dislocations/trap in theepilayer. The DC extrinsic gm and ID vs. VGS curve are shown in Fig. 4.11bfor VDS = 4 V, and reveal a peak gm = 462 mS/mm at VGS = 5.4 V.From the ID curve, one can define a threshold voltage VTH ≈ −7 V.However, channel pinch-off remains incomplete at higher drain biases:at (VGS, VDS) = (−8, 10) V, a residual drain current ID = 175 mA/mm ismeasured, while a much smaller current IG = 45 µA/mm flows throughthe gate, indicating that the lack of pinch-off arises due to SCEs associatedwith high VDS values in a device with a gate aspect ratio LG/d = 2.7.


0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

-6 V

-3 V

I D (A

/mm

)

VDS (V)

ID,(0,0)

- ID,(-8,8)

VGS

= 0 V

(a)

2 4 6 80

20

40

60

80

100

0 V -3 V -6 V

I (0,0

)- I(-

8,8)

( % o

f I(0

,0) )

VDS (V)

VGS

=

(b)




0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

-6 V

-3 V

I D (A

/mm

)

VDS (V)

ID,(0,0)

- ID,(-8,8)

VGS

= 0 V

(a)

2 4 6 80

20

40

60

80

100

0 V -3 V -6 V

I (0,0

)- I(-

8,8)

( % o

f I(0

,0) )

VDS (V)

VGS

=

(b)



AlInN-on-SiC 65

1 10 100

5101520253035404550

1 10 100

VDS= 6 V

VGS

Gain(dB)

VDS= 5 V

VGS

fT= 205 GHz

fMAX(U)

= 220 GHz fMAX(U)

= 230 GHz

fT= 198 GHz

U

MSG

H21

Frequency (GHz)(a) (b)

Figure 4.13: Small-signal RF characterization and cutoff frequency extractionfor a HEMT fabricated on Layer A, with LG = 30 nm, LH = 400 nm,LSD = 1 µm, W = 100 µm. The two measurements were performed at the(VDS, VGS) bias yielding the highest fT.

A reduction of the barrier thickness, as well as an improvement of thebuffer-side confinement of the 2DEG, would help reduce SCEs. Fig. 4.12ashows pulsed I-V characteristics measured with pulse widths of 500 nsfrom two different quiescent points. The stressed curves are measuredwith a quiescent point (VGS, VDS) = (−8, 8) V (dashed lines), to be com-pared with the non-stressed (VGS, VDS) = (0, 0) V (solid lines). To quantifythe amount of current lost by dispersion, Fig. 4.12b shows the percent-age of drain current lost by pulsing, i.e. ID,(0,0) − ID,(-8,8). The amountof current lost lies between 20% and 40% at both VGS = 0 and −3 V.At −6 V the lost percentage appears higher not because of increaseddispersion but due to the vanishing ID in the stressed condition. Thanksto the full passivation, dispersion was reduced with respect to other high-performance partially-passivated devices fabricated by our group [85].A potential optimization of the passivation could be expected to furtherreduce dispersion. Figure 4.13a characterizes the resulting transistor mi-crowave performance at the peak transconductance bias of VDS = 5 V andVGS = −5.4 V, yielding fT = 205 GHz and fMAX,U = 220 GHz. Biasingthe device at higher VDS allows fMAX to increase even further, peaking


at 230 GHz for VDS = 6 V and VGS = 5.6 V (Fig. 4.13b). fT and fMAX donot drop significantly for a broad range of drain biases, both remainingabove 200 GHz for 2.5 < VDS < 10 V, at VGS around −5.5 V. An estimateaccording to a parallel plate approximation yields CGS = 22 fF. In compar-ison, the intrinsic small-signal capacitances extracted using the equivalentcircuit of Fig. 4.1 are (CGS +CGD) = (26+ 10) = 36 fF (at the peak fT biascondition detailed in Fig. 4.13a), confirming the low parasitic character ofour gate technology. Comparison to the fT/ fMAX = 260/390 GHz resultsachieved with ultralow resistance regrown contacts at HRL [34] suggeststhat a limited gm due the higher gate-to-channel distance in our HEMTsrepresents our major bandwidth limitation.

4.3.1 Thin-barrier HEMTs3

In order to reduce SCEs, Layers B and C were designed to achieve areduced gate-to-channel distance of 6 nm. The difference between thetwo structures lies in the cap layer: 2 nm GaN cap and 1.5 nm AlNcap, for Layers B and C, respectively (see Table 4.2). The introductionof an AlN cap was motivated by promising results in terms of currentcollapse and breakdown voltages [89, 90]. Higher 2DEG densities wereachieved in the the AlN-capped Layer C with respect to Layer B. This isbecause in the GaN-capped heterostructure, negative polarization chargesare present at the AlInN/GaN cap interface, causing partial depletionof the 2DEG. On the contrary, in the AlN-capped heterostructure, thepositive polarization charges at the AlInN/AlN cap interface mitigate thesurface related depletion effects, reinforcing the 2DEG density. Despitethe lower electron density and higher sheet resistivity, the GaN-cappedheterostructure presents higher electron mobility, which can be explainedby considering the effect of electron density on the pertinent scatteringmechanisms. At room temperature, the principal mobility limiting mech-anisms are phonon-related scattering and interface roughness scattering,both becoming more important as the electron density increases [46].Dislocation and background impurity related scattering are also density












AlInN-on-SiC 67

Layer B



Layer C

1.5 nm AlN (cap)3.5 µm Al13In87N (barrier)

1 nm AlN (spacer)2 µm GaN (buffer)


Table 4.2: Heterostructure Layers B and C, from top to bottom. The layersdisplayed as-grown nS = 1.6·1013 cm−3 and µ = 1470 cm2/V·s (Layer B) andnS = 2·1013 cm−3 and µ = 1320 cm2/V·s (Layer C) from Hall measurments.Both layers were grown on semi-insulating SiC substrates.

dependent but play a minor role in the mobility balance.

In addition to thinning down the barrier, SCEs were addressed byimplementing marginally longer gates. For LG = 75 nm HEMTs onLayers B and C, an increased LG/d ratio of 12.5 is achieved, comparedto LG/d = 6.81 on Layer A. The effect of the improved LG/d ratio ongm and ID is shown in Fig. 4.14. Figure 4.14a shows that in HEMTswith LG = 75 nm the maximum gm increases from 512 mS/mm to612 mS/mm with the reduction of the barrier thickness from 11 (LayerA) down to 6 nm (Layers B and C). The introduction of a GaN capprovides further improvement on Layer B with respect to Layer C, withgm increasing from 612 to 665 mS/mm. The difference may be explainedas follows. A more accurate estimate for the transconductance for it can begm ≈ vsat/deff, where deff is an effective gate-to-channel distance, whichtakes into account the electron distribution. A possible explanation for thedifference in gm between Layers B and C can then be found by analyzingin detail the charge distribution inside the layers. While the geometricalbarrier thickness remains the same, the AlN cap of Layer C introducespositive polarization charges which lead to a higher 2DEG density. Itcan be shown [88] that in Layer C the electrons tail deeper into the GaNbuffer. Therefore deff would be higher for Layer C with respect to Layer B,explaining its lower gm.


-7 -6 -5 -4 -3 -2 -1 00

100

200

300

400

500

600

700d =

6 nm, AlN cap6 nm, GaN cap

g m (m

S/m

m)

VDS (V)

11 nm, GaN cap

(a)

-7 -6 -5 -4 -3 -2 -1 010-2

10-1

100

101

I D (A

/mm

)VGS (V)

VDS

= 6 V

d = 11 nm, GaN cap

d = 6 nm, AlN cap

d = 6 nm, GaN cap

(b)

Figure 4.14: Transconductance (a) and drain current (b) vs. VGS measured atVDS = 6 V for HEMTs with LG = 75 nm fabricated on Layers A (green), B(blue) and C (red).

Because gm and CGS both scale as 1/d, the ratio gm/CGS remainsapproximately constant with decreasing d. Therefore, the first-order ap-proximation fT ≈ gm/(2πCGS) is unsuitable to quantify how the barrierthickness impacts the cutoff frequency. A more detailed analysis of thedelay contributions leading to the fT expression of Eq. 4.1 is required.Such analysis must also take into account fringing effects, which have anon-negligible influence on the total delay for deep sub-µm gate lengths.[73]. To take them into account in a straight-forward way, an empiricalrelation between the metallurgical gate length (LG) and the effective gatelength (LG,eff) was adopted, by analogy to Ref. [91]:

LG,eff = LG + C · d (4.5)

where C is an empirical parameter which depends on the dielectricconstant and field distribution around the gate. For AlGaN C = 5.1was found in good agreement with the data [91]. For the AlInN-basedstructures used in this work, a comparison of the performance of HEMTsfabricated on Layers A (d = 11 nm) and B (d = 6 nm) suggests C = 4. Ahigher dielectric constant reduces the spreading of the field lines under


-7 -6 -5 -4 -3 -2 -1 00

100

200

300

400

500

600

700d =


g m (m

S/m

m)

VDS (V)

11 nm, GaN cap

(a)

-7 -6 -5 -4 -3 -2 -1 010-2

10-1

100

101

I D (A

/mm

)

VGS (V)

VDS

= 6 V

d = 11 nm, GaN cap

d = 6 nm, AlN cap

d = 6 nm, GaN cap

(b)



LG,eff = LG + C · d (4.5)



-7 -6 -5 -4 -3 -2 -1 00

100

200

300

400

500

600

700d =


g m (m

S/m

m)

VDS (V)

11 nm, GaN cap

(a)

-7 -6 -5 -4 -3 -2 -1 010-2

10-1

100

101

I D (A

/mm

)

VGS (V)

VDS

= 6 V

d = 11 nm, GaN cap

d = 6 nm, AlN cap

d = 6 nm, GaN cap

(b)



LG,eff = LG + C · d (4.5)


AlInN-on-SiC 69

6 9 12 15 18 21 2450

100

150

200

250

300 400 200 100 50 25

f T,ex

t (GHz)

d (nm)

LG = 35 nm

LG,eff

= LG + 4d

RDS

(Ω) =

(a)

6 9 12 15 18 21 2450

100

150

200

250

300 400 200 100 50 25

f T,ex

t (GHz)

d (nm)

LG = 75 nm

LG,eff

= LG + 4d

RDS

(Ω) =

(b)

Figure 4.15: Extrinsic cutoff frequency calculated using Eq. 4.1. For bothplots, the following values have been used: nS = 1.7·1013 cm−2 (at d =

6 nm), CGD = 14 fF, µ = 1500 cm2/V·s, LSD = 1 µm, W = 100 µm,vsat = 1.9·107 cm/s, gm,int = ε·vsat/d. Gate lengths were LG = 35 nm andLG = 75 nm for (a) and (b), respectively. A contact and gate resistance of0.35 Ω/mm and 3.5 Ω, respectively, were assumed.

the gate, reducing the fringe capacitance. The reduction of the coefficientC is thus physically consistent with the higher dielectric constant ofAlInN with respect to AlGaN. fT was then calculated assuming gm,int =

ε·vsat/d and a nS vs. d relation in accordance to the data of Ref. [92]. Lg,eff

obtained from Eq. 4.5 was also used to calculate CGS with a parallel plateapproximation. The other values needed to calculate fT from Eq. 4.1 wereassumed to be d-independent (see Fig. 4.15, caption). The resulting fT vs.d relation is shown in Fig. 4.15.

An inspection of Figs. 4.15a and 4.15b shows that ultra-thin barrier aremore beneficial with shorter gates. Additionally, Fig. 4.15 shows that lowvalues of RDS have a major impact on the fT of a HEMT, leveling off forRDS > 200 Ω, at which the RDS term in Eq. 4.1 becomes negligible withrespect to the others.

The small-signal microwave performance of HEMTs fabricated on


1 10 100

10

20

30

40

50

1 10 100

MSG

VDS= 4 V

VGS

Layer C - AlN cap

Gain(dB)

VDS= 4 V

VGS

fT= 180 GHz

fMAX(U)

= 180 GHz fMAX(U)

= 170 GHz

fT= 170 GHz

(a) (b)

Layer B - GaN capH

21

U

Frequency (GHz)

Figure 4.16: Small-signal RF measurements and extraction for HEMTs fab-ricated on Layers B and C with LG = 75 nm, LH = 400 nm, W = 100 µm,LSD = 1 µm.

the thin-barrier Layers B and C is shown in Fig. 4.16. The devices werefabricated with the same process as for Layer A, detailed in Sec. 4.3. Thepost-process sheet resistance was 230 and 216 Ω/ for Layers B andC, respectively, with typical contact resistance of 0.35 Ω/mm. The fT

and fMAX values are lower than those shown in Fig. 4.13 (LG = 30 nm),but achieve a higher fT·LG product in both devices, showing a markedimprovement attributed to the scaled-down barrier thickness. The thinnerbarrier also helps reduce RDS at a given LSD. RDS values of 168 and 129 Ωwere extracted for Layers B and C, respectively, with a 100 Ω improvementwith respect to the thicker-barrier Layer A at peak fT (Fig. 4.13). Theresults are in qualitative agreement with the trends shown in Fig. 4.15.

To complete the characterization, pulsed measurements were per-formed on identical devices fabricated on Layers B and C, and areshown in Fig. 4.17. Both devices displayed dispersion lower than 20% atVGS = 0 V, and AlN-capped devices (Layer C) showed less dispersionthan GaN-capped ones (Layer B) with identical geometry at the same VGS

bias. The physical origin of the reduced dispersion of the AlN-cappedstructure is not completely understood, we assume that positive interface


1 10 100

10

20

30

40

50

1 10 100

MSG

VDS= 4 V

VGS

Layer C - AlN cap

Gain(dB)

VDS= 4 V

VGS

fT= 180 GHz

fMAX(U)

= 180 GHz fMAX(U)

= 170 GHz

fT= 170 GHz

(a) (b)

Layer B - GaN capH

21

U

Frequency (GHz)







1 10 100

10

20

30

40

50

1 10 100

MSG

VDS= 4 V

VGS

Layer C - AlN cap

Gain(dB)

VDS= 4 V

VGS

fT= 180 GHz

fMAX(U)

= 180 GHz fMAX(U)

= 170 GHz

fT= 170 GHz

(a) (b)

Layer B - GaN capH

21

U

Frequency (GHz)






AlInN-on-SiC 71

1 2 3 4 5 6 7 80

20

40

60

80

100

Layer BLayer C

I (0,0)-I (V

gs,10)(%

ofI (0

,0))

VDS (V)

VGS=0 V-1 V-2 V

Figure 4.17: Compared dispersion of HEMTs fabricated on Layers B and Chaving LG = 200 nm, LH = 600 nm, W = 100 µm, LSD = 4 µm.

charges present in this layer are able to compensate the surface traps,as shown for AlGaN-based HEMTs [89]. Another hypothesis is that theAlN-cap may act as an in-situ passivation, by formation of a native AlOlayer, known to form during the high-temperature annealing of the ohmiccontacts [72].

In conclusion, Layers B and C were shown to be good candidatefor large-signal measurements. However, short-channel effects were stillpresent even on 75 nm-long gates. This demands that SCEs should betackled not only by implementing a more favorable the LG/d ratio, butalso through an improvement of the buffer-side confinement of the 2DEG.

4.3.2 Reduction of Short-Channel Effects

The data presented so far in this work suggest that SCEs in GaN-basedlayers arise mostly due to lack of buffer-side 2DEG confinement. ThisSection reports on two approaches undertaken to reduce SCEs. The firstis using a light-atom ion implant to create defects predominantly in thebuffer to reinforce its insulation and improve the 2DEG confinement. Thesecond approach is to use an improved epilayer where the buffer is a


(a) (b)

Figure 4.18: Simulation of ion implant, showing the following ion-induceddamages: N-vacancies, Ga-vacacies, which sum up to the target vacancies,and target displacements which include also replacement collisions. (a)shows the effect of a H+ ion beam with energy of 50 kV on layer C, while(b) shows the effect of two 50 kV and 100 kV subsequent implants.

wide-bandgap material, in our case Al0.04Ga0.96N (AlGaN back-barrier).In this case only a thin, 20 nm GaN layer is grown on top of the AlGaNbuffer to host the formation of the 2DEG.

H+ Ion Implantation

In Sec. 3.2.4 we have shown that SCE arise from a reduced EC − EF sepa-ration in the buffer region adjacent to the 2DEG. Therefore, implementinga shift of EC − EF to bring EF close to the middle of the bandgap shouldreduce SCEs. This can be achieved with an appropriately engineeredp-doped buffer or a heterostructure back-barrier. However changes in thebuffer layer may come at the expense of mobility or 2DEG density. Thetechnique presented here has the major advantage of being easily appliedto any thin-barrier heterostructure, and even on fully-processed HEMTdevices.

The idea is the following: when a high-energy H+ ion beam is irradi-ated on a transistor, the light H+ ions travel a few nanometer inside the


(a) (b)



H+ Ion Implantation




(a) (b)



H+ Ion Implantation



AlInN-on-SiC 73

Barrier

Buffer

Gate

H+ ions

Buffer

2DEG

Ion Damage

Ion Damage

Drain

Figure 4.19: Scheme of H+ ion implant experiment, performed after process-ing. The shaded areas represent ion-induced damage, either by replacementcollisions or vacancies creation.

material before actually inducing a defect in the form of a Ga or N vacancy.With an appropriate choice of the beam energy, it is possible to calibratethe penetration depth so that most of the vacancies are induced below thethin 6 nm barrier layer, thus preventing degradation of the 2DEG. To selectthe optimal implant energy, ion-collision simulations were performed us-ing SRIM software4. The simulations show that a dose of 50 keV achievesthe expected result of a damage profile with its peak ≈ 400 nm belowthe surface, with a vacancy density nv = 1.4·105 (cm·ion)−1 (Fig. 4.18a),and that the damage in the barrier layer is lower by about an order ofmagnitude. A second implant strategy was also simulated, consistingof two subsequent irradiations at 50 and 100 keV, respectively. This ex-pands the damage-induced region, creating a second damage-densitypeak ≈ 550 nm below the surface (Fig. 4.18b). The simulations show thata 400 nm-thick gold layer deposited on top of the heterostructure is ableto stop all the ions from reaching the surface, both at 50 and 100 keV.When the process is applied to a HEMT, the gate head protects the activeregion from ion-induced damage. The process can thus be applied toa processed HEMT, as schematically depicted in Fig. 4.19. The active

4Available at http://www.srim.org/. Free for non-commercial use.


-6 -5 -4 -3 -2 -1 0

10-1

100

H+ ions dose, energy: 2.5·1013 cm-2, 50 & 100 kV 5·1013 cm-2, 50 kV 5·1012 cm-2, 50 kV

I D (A

/mm

)

VGS (V)

VDS = 6 V

(a)

-5 -4 -3 -2 -1 00

100

200

300

400

500

600

700

800

VDS = 6 V

gm

(mS

/mm

)VGS (V)

2.5·1013 cm-2, 50 & 100 kV 5·1013 cm-2, 50 kV 5·1012 cm-2, 50 kV

H+ ions dose, energy:

(b)

Figure 4.20: Effect of different ion implant doses and energies in HEMTswith LG = 100 nm LSD = 2 µm, W = 100 µm, on ID (a) and on gm (b),respectively.

region is protected from the top, but some damage spreads under thegate laterally due to the straggle of the implant, estimated as ≈ 150 nmfrom the simulation. The induced defect concentration per volume can beexpressed as:

Ndef = D·ni, (4.6)

where D is the irradiation dose in ions·cm−2 and ni is the number ofdefects expressed in (cm·ion)−1. To determine the optimal implant dose,we assumed EC − EF ≈ 0.25 eV, in accordance to the value found 150 nmbelow the surface by the simulation (Fig. 3.13). In bulk, n-doped GaN,this value corresponds to a donor density ND,eff = 1.4·1014 cm−3. For a50 kV H+ implant, the dose required to achieve the same concentrationof Ga-vacancies (ND,eff = Ndef) around the peak of Fig. 4.18a is DTH =

9·108 ions/cm2. Therefore, to produce a relevant shift in EC − EF, theimplant dose must be DTH. The dislocation density reported on LayersB and C is Ndisl ≤ 109 cm−3, much lower than the defect density inducedby an implant with a dose DTH. Such a high dose means that the damagein the barrier, although one order of magnitude lower with respect to


-6 -5 -4 -3 -2 -1 0

10-1

100


I D (A

/mm

)

VGS (V)

VDS = 6 V

(a)

-5 -4 -3 -2 -1 00

100

200

300

400

500

600

700

800

VDS = 6 V

gm

(mS

/mm

)

VGS (V)

2.5·1013 cm-2, 50 & 100 kV 5·1013 cm-2, 50 kV 5·1012 cm-2, 50 kV


(b)



Ndef = D·ni, (4.6)




-6 -5 -4 -3 -2 -1 0

10-1

100


I D (A

/mm

)

VGS (V)

VDS = 6 V

(a)

-5 -4 -3 -2 -1 00

100

200

300

400

500

600

700

800

VDS = 6 V

gm

(mS

/mm

)

VGS (V)

2.5·1013 cm-2, 50 & 100 kV 5·1013 cm-2, 50 kV 5·1012 cm-2, 50 kV


(b)



Ndef = D·ni, (4.6)



AlInN-on-SiC 75

0 1 2 3 4 5 6

0.20.40.60.81.01.21.41.61.82.0

(a)

no implant H+ implant

I D (A

/mm

)

VDS (V)-5 -4 -3 -2 -1 00

200

400

600

10-2

10-1

100

101

VGS (V)

(c)

(b)

gm

(mS

/mm

)

VDS

= 6 V

I D (A

/mm

)Figure 4.21: DC characteristics before (dashed lines) and after post-procession implant (solid lines) of 5·1012 cm−2 H+ ions. The device fabricatedon Layer C had LG = 75 nm LSD = 1 µm, W = 150 µm. (a) ID vs. VDS

characteristics, where VGS is varied from 0 to -5 V in steps of 1 V. (b) ID vs.VGS and (b) gm at VDS = 6 V.

the peak, begins also to be non-negligible. It is therefore desirable to usethe lowest possible implant dose. In a preliminary set of experiments,we found that a dose of Dopt = 5·1012 ions/cm2 was the lowest dosenecessary to produce measurable effects on the DC characteristics. A dose10x higher and a dual dose at 50 and 100 kV were attempted, whoseresults are shown in Fig. 4.20. The off-current (IOFF) at VGS = −6 Vremains unchanged for the three implant doses, showing no additionalbenefit for increasing the implant dose above Dopt = 5·1012 ions/cm2,or for dual-energy implant (Fig. 4.20a). However, gm begins to degradefor higher doses at 50 keV or when the implant is performed at 100 keV.We therefore conclude that a dose Dopt is sufficient to fully harness thebenefits of this process, and higher doses introduce an excessive amountof damage in the layer. The performance of HEMTs implanted with adose Dopt was then further investigated.

Figure 4.21 shows the I-V characteristics of a HEMT with LG = 75 nmfabricated on Layer C before and after implanting H+ ions at 50 kV witha dose Dopt. With respect to the non-implanted HEMT, the I-V characteris-


Parameter Before implant After implant

CGS 64.3 fF 83 fFCDS 40.2 fF 40.5 fFCGD 20 fF 20.43 fFgm,int 116 mS 124 mSRDS 38.6 Ω 55 ΩRGS 1.6 Ω 1.8 Ω

fT (meas) 155 GHz 160 GHzfMAX,U (meas) 175 GHz 160 GHz

Table 4.3: Equivalent circuit elements of a device fabricated on Layer C, withLG = 75 nm LSD = 1 µm, W = 150 µm. fT (ext) and fMAX,U (ext) representthe extrinsic, de-embedded values extracted at (VGS, VDS) = (−2.5, 5) V. Theimplant dose of H+ ions was 5·1012 cm−2.

tics show 100 mA/mm drop ID,MAX, but reduction of IOFF by 200 mA/mmat VGS = −5 V. Figure 4.21b reveals that beside a marginal decrease inthe ID,MAX, the thresholds shifts toward more positive values, generatinga much reduced ID at negative VGS bias. An additional benefit of theimproved channel control is an increase in gm of 100 mS/mm (+21%)with respect to the pre-implant value (Figure 4.21c). Improvements of theION/IOFF ratio and gm are beneficial to the large-signal performance.

The small-signal RF performance of the device is summarized in Ta-ble 4.3, which lists the equivalent circuit elements as well as the extractedvalues of fT and fMAX before and after the H+ implantation. Besidethe already mentioned increase in gm, which corresponds to the mod-est increase in the extracted gm,int, the only affected elements are CGS

and RDS. CGS shows a 19 fF increase, which can be attributed to theimproved 2DEG-confinement which brings the electrons closer to the gatefoot, thus increasing its capacitance. RDS also follows the same trend,increasing thanks to the better channel control and the shift of VTH tomore positive values. These changes combined produce a 5 GHz increasein fT. The modest degradation in fMAX,U from 175 down to 160 GHzcan be attributed to the increase in the access resistances due to the

















AlInN-on-SiC 77

0 1 2 3 4 5 6 7 8 9 100.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4(V

GS,V

DS) =

-2 V

0 V

(0,0) V(-4.5,10) VDC

I D(A/mm)

VDS (V)

VGS= +2 V

Figure 4.22: DC (solid lines) and pulsed I-V characteristics for of a HEMTfabricated on Layer B, with LG = 200 nm LSD = 4 µm, W = 150 µm. WhereVGS = 2, 0 and −2 V, respectively, with a quiescent point of (VDS, VGS) =

(0, 0) V (dotted line) and (−4.5, 10) V (dashed line), respectively. The DCcurves are also shown (solid line).

ion-damage tail in the barrier layer. The damage induced by ion implantdoes not impact current collapse significantly. No increase in dispersionis measured on HEMTs after H+ ion implantation. Pulsed measurementperformed on a ion-implanted HEMT fabricated on Layer B are shownin Fig. 4.22. The device had a gate length of LG = 200 nm, suitable forlarge-signal operation at 40 GHz. The amount of current lost by pulsingwith a quiescent point of (VGS, VDS) = (−4.5, 10) with respect to (0, 0) Vis ≤ 20%, comparable with the dispersion measured on non-implantedHEMTs (Fig. 4.17).

In conclusion, the ion-implant process demonstrated in this Sectionproved to be advantageous as long as a H+ dose Dopt = 5·1012 ions/cm2

is used. However, while the DC characteristics are improved, the residualchannel currents at VGS = −5 V are still non-negligible, and the intro-duction of a back-barrier in the heterostructure is next shown to providemore significant benefits than H+ ion implantation.


Layer D

1 nm AlN (cap)8 nm Al0.13In0.87N (barrier)1 nm AlN (spacer)

20 nm GaN (channel)2 µm Al0.04Ga0.96N (back-barrier)


Table 4.4: Layer D, from top to bottom. The layer displayed as-grown nS =

2.75 cm−3 and µ = 880 cm2/V·s from Hall measurements, for a total Rsh =

258 Ω/.

AlGaN Back-Barrier

A new heterostructure was designed and grown to test the effectivenessof an AlGaN back-barrier in reducing SCEs in GaN HEMTs. The het-erostructure design is shown in Table 4.4 and is denoted as Layer D inthis work. As opposed to the other layers previously presented in thiswork, the 2DEG is formed inside a 20 nm GaN channel, while the buffer iscomposed of the wider bandgap Al0.04Ga0.96N. At the Al0.04Ga0.96N/GaNinterface, the conduction band offset ∆EC provides buffer-side confine-ment to the 2DEG (see Fig. 3.13). At the same time, the low aluminumcontent of the back-barrier limits its lattice mismatch to GaN. In Layer D,however, Hall measurements revealed a much reduced electron mobilityof µ = 880 cm2/V·s with respect to the GaN buffers used so far. Tosustain a sheet resistance similar to Layers B and C, the barrier thicknesswas increased up to a total gate-to-channel distance of 10 nm, whichenabled a 2DEG density nS = 2.75·1013 cm−3. A HEMT fabricated onLayer D, compared to a H +-implanted one fabricated on Layer C, showslower ID at VGS < −4.5 V, with the expected reduction of IOFF (Fig. 4.23a).Compared to HEMTs fabricated on Layer A (d = 11 nm), those fabricatedon Layer D (d = 10 nm) show reduced values of ID,MAX and gm. The dropin gm is caused by the degraded transport properties of the layer, substan-tiated by the lower µ. The low gm impacts negatively the small-signal RF


Layer D






258 Ω/.

AlGaN Back-Barrier



Layer D






258 Ω/.

AlGaN Back-Barrier


AlInN-on-SiC 79

-6 -5 -4 -3 -2 -1 010-2

10-1

100

Back-barrier 5·1012 cm-2 H+ implant

I D (A

/mm

)

VGS (V)

VDS

= 6 V

(a)

-6 -5 -4 -3 -2 -1 00

50

100

150

200

250

300

350

400

1 V 3.5 V 6 V

gm

(mS

/mm

)

VGS (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

I D (A

/mm

)

VDS

=

(b)

1 10 100

5101520253035

Gain(dB)

Frequency (GHz)

fMAX(U)

= 100 GHzfMAX(MSG)

= 100 GHz

fT= 60 GHz

MSG

U

H21

(c)

Figure 4.23: (a) Comparison of drain current ID of a HEMTs fabricated onLayer C (LG = 75 nm LSD = 1 µm, W = 150 µm) with an ion implant doseof 5·1012 cm−2 H+ ions (blue) and and identical one fabricated on the back-barrier Layer D (red). For the HEMT fabricated on Layer D (b) shows gm

(solid line) and ID (dashed line), measured at VDS =1, 4 and 7 V (color coded)and (c) shows the small-signal RF measurements at (VGS, VDS) = (−2.5, 6) V.

performance, and the highest fT and fMAX measured are 60 and 100 GHz,respectively (Fig. 4.23c).

Recovery of gm for HEMTs fabricated on Layer D was attempted byreducing d (Eq. 3.4) through a gate recess. Figures 4.24a and 4.24b showID and gm, respectively, for three different d values: 10 nm (no recess),


-6 -5 -4 -3 -2 -1 0 1 2 310-3

10-2

10-1

100

101

none ~1 nm 8 nm

I D (A

/mm

)

VGS (V)

VDS

= 6 V

Recess depth:

(a)

-6 -5 -4 -3 -2 -1 0 1 2 30

50100150200250300350400450

VDS

= 6 V

g m (m

S/m

m)

VGS (V)

none ~1 nm 8 nm

Recess depth:

(b)

Figure 4.24: (a) ID of devices with different recess depths, of HEMTs (LG =

75 nm LSD = 1 µm, W = 150 µm). (c) gm for the same devices.

8 nm (1 nm recess) and 2 nm (8 nm recess). The motivation for the shallow,1 nm recess was to etch away only the AlN cap of Layer D. The recessdepth was characterized by AFM, however, the shallow 1 nm recess depthis comparable to the epilayer roughness and affected by a significantmeasurement uncertainty. Figure 4.24a shows a threshold voltage shiftwhich scales with the recess depth, with VTH = −5.5, −3.5 and −0.5 Vfor 0, 1 and 8 nm recesses, respectively. ID,MAX is preserved for the 1 nm-recess HEMT (red curve in Fig. 4.24a), but drops by 600 mA/mm with arecess of 8 nm. While IOFF is reduced with increasing recess depths, gm isonly slightly increased for the 1 nm-recess HEMTs (red curve in Fig. 4.24b)and drops for the 8 nm recess HEMT. The reduction of gm and IDMAX

demonstrates that a deep 8 nm recess degrades the transport properties ofthe 2DEG, presumably because of a damage-induced decrease of electronmobility in the recessed areas. The degradation of transport propertiesis also confirmed by the small-signal measurements, whose results aresummarized in Table 4.5. For HEMTs with LG = 75 nm and 1 nm-recess, fT increased by 5 GHz with respect to a non-recessed HEMT withthe same gate length. fMAX,U was unchanged, while fMAX,MSG shaveda marginal improvement. For HEMTs with LG = 35 nm, fT goes from


-6 -5 -4 -3 -2 -1 0 1 2 310-3

10-2

10-1

100

101

none ~1 nm 8 nm

I D (A

/mm

)

VGS (V)

VDS

= 6 V

Recess depth:

(a)

-6 -5 -4 -3 -2 -1 0 1 2 30

50100150200250300350400450

VDS

= 6 V

g m (m

S/m

m)

VGS (V)

none ~1 nm 8 nm

Recess depth:

(b)






-6 -5 -4 -3 -2 -1 0 1 2 310-3

10-2

10-1

100

101

none ~1 nm 8 nm

I D (A

/mm

)

VGS (V)

VDS

= 6 V

Recess depth:

(a)

-6 -5 -4 -3 -2 -1 0 1 2 30

50100150200250300350400450

VDS

= 6 V

g m (m

S/m

m)

VGS (V)

none ~1 nm 8 nm

Recess depth:

(b)





AlInN-on-SiC 81

Recess depth fT fMAX,U( fMAX,MAG) LG

0 nm 75 GHz 85 (100) GHz 75 nm1 nm 80 GHz 85 (110) GHz 75 nm

1 nm 100 GHz 130 (100) GHz 35 nm8 nm 80 GHz 85 (80) GHz 35 nm

Table 4.5: fT and fMAX of recessed devices fabricated on Layer D. The totalbarrier thickness before recess was d = 10 nm.

100 down to 80 GHz, with recesses of 1 and 8 nm, respectively, andfMAX shows an even steeper drop, exacerbated by the increase of theaccess resistances. Gate-recess in AlInN-based HEMTs seems thus morechallenging that in AlGaN, and beside a reduction of IOFF, produces toomany drawbacks to be productively implemented.

From the results presented in this Section we can conclude that anAlGaN back-barrier is effective in reducing SCEs and can improve theIOFF/ION ratio with respect to devices with standard GaN buffers orion-implanted HEMTs. However, the sub-optimal mobility of the 2DEG inLayer D degraded the HEMT small-signal performance, which was furtherdegraded in gate-recessed devices. Good performance with back-barrierepilayer can be thus obtained only with an improvement of the epitaxialprocess. New back-barrier layers have been already fabricated with anincreased GaN channel thickness of 50 nm, showing nS = 1.6·1013 cm−3

and an improved µ = 1500 cm2/V·s (Rsh = 260 Ω/). These improvedlayers also have a thinner barrier of 6 nm, identical to that of Layers Band C, eliminating the need of a gate recess. HEMTs fabricated on thisimproved epilayer are currently under test.

4.3.3 Regrown Contacts Devices

The importance of reduced contact resistance in HEMTs cannot be under-stated. The contact resistance in wide bandgap HEMTs can make up for agood portion of the access resistances RS and RD (see Sec. 3.2.2) and thus


0 2 4 6 8 10 12 14 16 180.00.20.40.60.81.01.21.41.61.8

0 2 4 6 8 10 12 14 16 18

VGS

= -2 to +2 V in 1 V steps

I D (A

/mm

)

VDS (V)

RON

= 2.0 Ω mm

(b)

RON,HV

= 2.8 Ω mm

RON,LV

= 4.0 Ω mm

VDS (V)

(a)

Figure 4.25: I-V characteristics of HEMTs fabricated on Layer B with LG =

200 nm LSD = 4 µm, W = 100 µm and (a) regrown or (b) annealed ohmics,respectively. The dashed lines show the ON-resistance.

has an influence on the extrinsic gm (Eq. 3.5), on fT and fMAX. Annealedohmic contacts with low contact resistance have been achieved in thiswork with Ti/Al/Au (RC = 0.5 Ω/mm, Sec. 4.2.1) and Ti/Al/Mo/Au(RC = 0.35 Ω/mm, Sec. 4.3) annealed at ≈ 850 C, and by other groupswith different metallization schemes and annealing temperatures [93, 94].However, annealed ohmic contacts usually come at the expense of repro-ducibility, because the optimal annealing temperature lies in a narrow pro-cessing window which may depend on sample size, substrate thermal con-ductivity, and equipment characteristics. Additionally, high-temperatureannealing creates morphological and electrical inhomogeneities. For thisreason, modern GaN-based transistors with ultra-high cutoff frequenciesmake use of regrown ohmic contacts [33, 95].

In the rest of this Section, we compare the DC and RF results of identi-cal devices, with the only difference of either regrown or annealed ohmiccontacts. A side-by-side comparison allows to highlight the advantagesof regrown ohmic contacts over the annealed ones. It will be shown,that the introduction of regrown ohmic contacts allowed a significantimprovement in fMAX.


0 2 4 6 8 10 12 14 16 180.00.20.40.60.81.01.21.41.61.8

0 2 4 6 8 10 12 14 16 18

VGS


I D (A

/mm

)

VDS (V)

RON

= 2.0 Ω mm

(b)

RON,HV

= 2.8 Ω mm

RON,LV

= 4.0 Ω mm

VDS (V)

(a)






0 2 4 6 8 10 12 14 16 180.00.20.40.60.81.01.21.41.61.8

0 2 4 6 8 10 12 14 16 18

VGS


I D (A

/mm

)

VDS (V)

RON

= 2.0 Ω mm

(b)

RON,HV

= 2.8 Ω mm

RON,LV

= 4.0 Ω mm

VDS (V)

(a)





AlInN-on-SiC 83

0 2 4 6 8 10 12 14 16 180.00.20.40.60.81.01.21.41.61.8

0 2 4 6 8 10 12 14 16 18

(0, 0) V (-4,15) V

(VGS

,VDS

) =VGS


I D (A

/mm

)

VDS (V)

(a) (b)

VDS (V)

Figure 4.26: Pulsed I-V characteristics of a HEMTs with LG = 200 nm,LSD = 4 µm, W = 100 µm and (a) regrown or (b) annealed ohmics. Thequiescent point was (VGS, VDS) = (0, 0) and (−4, 15) V, for the dotted anddashed lines, respectively.

Regrown ohmic contacts were implemented on Layer B with the pro-cess explained in Sec. 2.3. Figures 4.25a and 4.25b show I-V characteristicsof LG = 200 nm HEMTs fabricated with regrown and annealed ohmiccontacts, respectively. TLM measurements revealed contact resistancesRC = 0.35 and 0.9 Ω/mm for the regrown and annealed ohmics, re-spectively. The extracted RON for each device is shown in Fig. 4.25. Inthe annealed-ohmic contacts HEMT, two ON-resistance values can beextracted: a higher value for VDS < 2 V (RON,LV), and a lower one forVDS > 2 V (RON,HV).

A possible explanation for the existence of two values lies in theinhomogeneity of the annealed ohmic contacts. The chemical reactionshappening during the high-temperature annealing create ohmic regionswith low-resistance, and others where the contact preserves a Schottky-like behavior. For VDS > 2 V bias the Schottky-regions become stronglyforward-biased, lowering the resistance of the whole contact and givingrise to the lower RON,HV. Because the transconductance peak is usuallylocated at VDS > 2 V, where the ON-resistance attains its lower value,


good RF performance is achieved even with apparently bad contactresistances (see Fig. 4.28). However, the partial Schottky nature of thecontacts may introduce undesired parasitic capacitances which may stillimpact negatively the RF performance.

Pulsed I-V characteristics for a regrown and annealed-contacts HEMTare shown in Fig. 4.26. While the dispersion is limited around VDS > 18 V,both devices show a significant knee-walkout around VDS ≈ 3 V, with acurrent drop between 30 and 40% at all VGS biases. This is attributed todefects present in both devices. In the regrown-contact HEMT, however,dispersion is about 5% lower. This may be due to an improved Schottkyinterface, because the regrown-contact HEMT did not undergo high-temperature annealing during its process. This was shown to degradeSchottky-barrier quality even when the contact is formed after annealing[96].

A clear difference between regrown and annealed contacts lies in thedrain current vs. time behavior. Figure 4.27a) shows ID vs. time, aftera bias of VDS = 5 V was applied. The plotted ID is normalized to itsvalue at t = 0. In the annealed-contacts HEMT, ID drops quickly to97.5% of its initial value and kept decreasing over time. In the regrown-contacts HEMT, ID recovered its initial value after the initial transient.It was also observed that the regrown-contacts HEMTs were able tomaintain the same output current level in time, while the annealed-contacts HEMTs showed decreasing ID. The current drop observed in theannealed-contacts HEMT could be caused by long-time trapping inducedby the high-temperature annealing, or degradation of aforementionedSchottky-like contacts regions. The origin of the transient is still unclearand would require further investigation, including testing for reversibilityin the annealed-contacts HEMT.

The transfer characteristics of regrown and annealed-contacts HEMTare shown in Fig. 4.27b. The ID vs. VGS plot shows an increase of theION/IOFF ratio by an order of magnitude with regrown versus annealedohmics, possibly as consequence of the degraded Schottky interfaceafter high-temperature annealing [96]. The reduction in RS produced











AlInN-on-SiC 85

0 5 10 15 20 25 30 35 4097.0

97.5

98.0

98.5

99.0

99.5

100.0

(a)

regrowthannealed

%I D(t)/I D

(0)

Time (s)-5 -4 -3 -2 -1 0 1 20

200

400

600

10-410-310-210-1100101

VDS

= 10 V V

DS = 1 V

annealed

gm

(mS

/mm

)

VGS (V)

(c)

regrown

annealedregrown

(b)

I D (A

/mm

)

Figure 4.27: (a) Time dependence of ID, normalized to its t = 0 value, forHEMTs with LSD = 4 µm, W = 100 µm LG = 75 nm (regrown) LG = 50 nm(annealed), measured after applying VDS = 5 V, at the same ID(t = 0) ≈ 70mA, achieved with VGS = −0.5 and −1.1 V in the regrown and annealedcontacts device, respectively. (b) Transconductance at VGS = 1 and 10 V forHEMTs (LG = 200 nm LSD = 4 µm, W = 100 µm) fabricated on Layer B withregrown and annealed contacts.

increases in gm,ext of 140 and 75 mS/mm at VDS = 6 and 10 V, respectively(Fig. 4.27c). Because of the Schottky-like component of the annealedcontacts, the difference was less pronounced at the high drain bias ofVDS = 10 V.

The reduction of the RS-related delay terms and the improved gm ledto an improvement of the cutoff frequencies. Small-signal measurementsfor HEMTs fabricated with regrown and annealed ohmic contacts for threeincreasing LSD spacings and identical gate lengths of 50 nm are shown inFig. 4.28. The fT increase of regrown versus annealed contacts was higherin the smallest spacing LSD = 1 µm. With respect to annealed-contactHEMTs fT and fMAX were 42 and 20 GHz higher, respectively (Figs. 4.28aand 4.28b). As LSD widened, the advantage of a reduced contact resistancewas diminished by the increased share of RS contributed by the accessregions. The reduced difference in RS with the two contact technologies


0

10

20

30

40

50

0

10

20

30

40

50

1 10 1000

10

20

30

40

50

1 10 100

(c)

(b)

(d)

(e) (f)

Annealed

VDS

= 9 VVGS

= -1.1 V

W = 50 m LSD = 1 m H21

MSG

VDS

= 10 VVGS

= -1 V

fMAX(U)

= 250 GHz

fT= 170 GHzU

Regrown

(a)

fMAX(U)

= 230 GHz

fT= 128 GHz

W = 50 m LSD = 2 m

Gai

n (d

B)

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 250 GHz

fT= 135 GHz

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 230 GHz

fT= 125 GHz

W = 25 m LSD = 4 m

Frequency (GHz)

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 220 GHz

fT= 130 GHz

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 215 GHz

fT= 120 GHz

Figure 4.28: Small-signal measurements of HEMTs with regrown ohmics(a, c, e) or annealed (b, d, f), fabricated on Layer B with LG = 50 nm anddifferent W and LSD (see inset).


0

10

20

30

40

50

0

10

20

30

40

50

1 10 1000

10

20

30

40

50

1 10 100

(c)

(b)

(d)

(e) (f)

Annealed

VDS

= 9 VVGS

= -1.1 V

W = 50 m LSD = 1 m H21

MSG

VDS

= 10 VVGS

= -1 V

fMAX(U)

= 250 GHz

fT= 170 GHzU

Regrown

(a)

fMAX(U)

= 230 GHz

fT= 128 GHz

W = 50 m LSD = 2 m

Gai

n (d

B)

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 250 GHz

fT= 135 GHz

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 230 GHz

fT= 125 GHz

W = 25 m LSD = 4 m

Frequency (GHz)

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 220 GHz

fT= 130 GHz

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 215 GHz

fT= 120 GHz



0

10

20

30

40

50

0

10

20

30

40

50

1 10 1000

10

20

30

40

50

1 10 100

(c)

(b)

(d)

(e) (f)

Annealed

VDS

= 9 VVGS

= -1.1 V

W = 50 m LSD = 1 m H21

MSG

VDS

= 10 VVGS

= -1 V

fMAX(U)

= 250 GHz

fT= 170 GHzU

Regrown

(a)

fMAX(U)

= 230 GHz

fT= 128 GHz

W = 50 m LSD = 2 m

Gai

n (d

B)

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 250 GHz

fT= 135 GHz

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 230 GHz

fT= 125 GHz

W = 25 m LSD = 4 m

Frequency (GHz)

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 220 GHz

fT= 130 GHz

VDS

= 10 VVGS

= -0.75 V

fMAX(U)

= 215 GHz

fT= 120 GHz


AlInN-on-SiC 87

1 10 100

10

20

30

40W = 25 µm L

G= 50 nm

LSD= 1 µm

H21

MSGGain(dB)

Frequency (GHz)

VDS= 10 V

VGS= -0.7 V

fMAX(U)

= 300 GHz

fT= 145 GHz

U

Figure 4.29: Small-signal measurements of a HEMT with regrown ohmicswith LG = 50 nm LSD = 1 µm, W = 50 µm. The fMAX was the highestmeasured on any AlInN-based HEMT fabricated in this work.

brings the fT closer for LSD = 2 µm, with a difference of only 10 GHz infavor of the regrown-contacts (Figs. 4.28c and 4.28d). For HEMTs withLSD = 4 µm, the difference in fMAX is reduced, and the two contacttechnologies achieve very similar performance (Figs. 4.28e and 4.28f).

The data presented so far demonstrate that only for HEMTs with smallLSD separation the regrown-contacts provide ample benefits to the small-signal performance. However, the reliability and homogeneity of regrowncontacts makes them still preferable to the annealed. In addition, thanks tothe homogeneously ohmic character of the contacts, shorter gate-widthscan be reliably implemented. The short fingers are more susceptibleto local inhomogeneities, otherwise averaged-out in longer gate-widthdevices. Regrown contacts enable better performance of multi-fingerdevices with short individual gate-widths. Because the gate resistanceRG has a prominent influence on fMAX, short gate-width devices withregrown contacts can easily outperform the annealed-contact devices. OnLayer B, HEMTs with short LSD = 1 µm and W = 2 × 25 µm, have beenfabricated, showing a high fMAX = 300 GHz (Fig. 4.29), which establisheda record for AlInN-based HEMTs fabricated in our laboratory.


Barrier2DEG (I = 0)

GateSource Drain

metal pad metal padohmiccontact

ohmiccontact

VDS > 0 VGS < VTH

Substrate

Buffer

cond

uctiv

e di

sloc

atio

n

cond

uctiv

e di

sloc

atio

n

ISCE

IG,leak

Ibuffer

to gate contact/padthrough dislocation

IG = IG,leak + I’buffer

ID,OFF = IG,leak + ISCE+ Ibuffer

I’buffer

Figure 4.30: Schematic representation of the conductive paths (dashed lines)which carry current to the drain contact (ID,OFF), when the gate is biasedbelow pinch-off (VGS < VTH), and the drain is positively biased VDS > 0 V.I′buffer denotes the share of current reaching the gate contact pad (not shown)through dislocations.

4.4 Leakage in AlInN-based layers

Reducing leakage current in GaN-based layers has been identified as achallenge of AlInN/GaN heterostructures where high leakage currentwere detected [97]. Excessively high gate leakage and off-state currents aredetrimental to the operation of GaN-based transistors, because they causeadditional power losses in the off-state of power supplies [98], and theycan be a source of premature breakdown and other reliability concerns[99]. Therefore, reducing leakage is of primary importance. To determinethe source of excessive gate leakage and off-state currents one must firstdetermine the physical origin of the contributions which, in the off-state,add up to ID and IG, respectively (see Fig. 4.30).

Deep sub-µm gate length GaN HEMTs often display finite outputconductance below pinch-off, with ID,OFF as high as 5-10% of ID,MAX athigh VDS bias (e.g., see Fig. 4.11). The residual drain current arises fromseveral leakage paths through the transistor structure. In the followingdiscussion, three contributions to ID,OFF are identified and schematically


Barrier2DEG (I = 0)

GateSource Drain


ohmiccontact

VDS > 0 VGS < VTH

Substrate

Buffer

cond

uctiv

e di

sloc

atio

n

cond

uctiv

e di

sloc

atio

n

ISCE

IG,leak

Ibuffer




I’buffer






Barrier2DEG (I = 0)

GateSource Drain


ohmiccontact

VDS > 0 VGS < VTH

Substrate

Buffer

cond

uctiv

e di

sloc

atio

n

cond

uctiv

e di

sloc

atio

n

ISCE

IG,leak

Ibuffer




I’buffer





Leakage in AlInN-based layers 89

-6 -5 -4 -3 -2 -1 010-9

10-8

10-7

10-6

10-5

10-4

10-3

LG=75 nm

Open

I G (A

/mm

)

VGS (V)

Layer A

Mesa

Implant Isolation

(a)

-6 -5 -4 -3 -2 -1 010-5

10-4

10-3

10-2

10-1

Normal pads

Insulated pads

Layer B Layer C

I G (A

/mm

)

VGS (V)

(b)

Figure 4.31: (a) Reverse-bias gate current of HEMTs fabricated on Layer Awith LG = 75 nm (solid lines) and Open test structures (dashed lines). Theinter-device isolation was performed by either mesa (thick lines) or (P+,H+, He+) ion implant isolation (thin lines). (b) Reverse-bias gate current (atVDS = 0 V) in HEMTs with LG = 75 nm fabricated on Layers B and C (blueand red lines, respectively), before and after implementing insulated contactpads.

presented in Fig. 4.30. The first contribution is reverse-bias gate leakage(IG,leak). This current flows between the gate and the drain contacts, thuscontributing to both ID and IG, and is a function of the gate-drain voltage,i.e., VGS − VDS. The second contribution (ISCE) comes from short-channeleffects, and is high with poor 2DEG confinement or low LG/d ratios(see Sec. 3.2.4). ISCE flows between the source and the drain contacts andcontributes to ID but not to IG. The third contribution (Ibuffer) is the currentflowing through undesired conduction paths in the buffer, resultingfrom unintentional doping or defects introduced in the epitaxial growth.Alternatively, Ibuffer may flow through a conductive layer between thesubstrate and the buffer, electrically connected to the pads via conductivedislocations. Because the dislocations are uniformly distributed in theepilayer, Ibuffer can contribute to both IG and ID.

A direct measurement of the buffer leakage due to contacts through the


pads was obtained by measuring Open test structures. These structureshave an identical morphology to a standard HEMT, except for the activeregion, where metal is not present and the 2DEG was removed by thedevice isolation process. For these measurements, two different types ofisolation were implemented: mesa isolation etching and ion-implantationisolation, performed through high-energy implant of P+, H+ and He+

ions (see Sec. 2.1). Figure 4.31a shows a measurement of IG on an Openstructure, compared to that on a working HEMT with LG = 75 nm. TheIG measurements on Open and HEMT structures with mesa isolationshowed very similar currents (Fig. 4.31a, thick lines). Because the Openstructure had neither gate nor active region, the measured current couldflow from the source to the gate pads only through the buffer. Thisallowed to estimate Ibuffer ≈ 10−3 A/mm. In the case of ion-implantisolation, the ions penetrate deep in the buffer, enhancing its insulatingcharacter. As a consequence, the current flow through the buffer waseffectively diminished and IG measured on the Open resulted two ordersof magnitude lower than with respect to that on the HEMT (Fig. 4.31a,thin lines). IG,leak was completely masked by the high Ibuffer in the mesaisolation devices. Its reduction by ion-implant isolation allowed us toestimate that a current IG,leak ≈ 10−5 A/mm was flowing through theHEMT Schottky contact.

Because a layer with fully insulating buffer was not readily available,an additional insulating SiN layer was deposited between the epilayerand the pads in order to reduce the Ibuffer component in the measuredIG. The drain, gate and source contact pads were thus fully insulatedfrom the epilayer except for the small openings that allowed electricalcontact with the ohmic regions. The purpose of insulating the pads was tolimit the contact area of the large measurement pads with the buffer andthe dislocations therein. A comparison of IG with and without insulatedpads was carried out in HEMTs with LG = 75 nm, fabricated on Layers Band C (Fig. 4.31b). With non-insulated pads, HEMTs on Layer B showedhigher IG with respect to those on Layer C. Because a higher occurrence ofhexagonal pits was detected on Layer B by electronic and optical imaging,the higher IG is attributed to denser defects with respect to Layer C










-6 -5 -4 -3 -2 -1 0 1 2 310-2

10-1

100

101

102

Insulated pads Normal pads

VGS (V)

I D (A

/mm

)

buffer leakage

Layer B

(a)

-6 -5 -4 -3 -2 -1 010-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

Insulated pads

Layer A11 nm barrier

Layer D10 nm barrier, back-barrier

Layer B6 nm barrier

I G (A

/mm

)

VGS (V)

(b)

Figure 4.32: (a) Drain current (ID) of a HEMT (LG = 75 nm LSD = 2 µm,W = 100 µm) before and after implementation of insulated contact pads. (b)Reverse-bias gate current (IG) for HEMTs with LG = 200 nm fabricated ondifferent layers.

(Fig. 4.31b, thick lines). With insulated pads, IG became very similaron the two layers, (Fig. 4.31b, thin lines) having removed a contributionIbuffer ≈ 1 and 4 mA/mm, for Layers B and C, respectively. With insulatedpads, we can thus estimate a IG,leak ≈ 0.2 mA/mm at VGS = −6 V inboth layers. Insulated pads also caused a reduction of the off-state ID

of ∆ID ≈ 20 mA/mm (Fig. 4.32a), compatible with the values of Ibuffer.Finally, the residual ID measured at VGS = −6 V, was therefore due toSCEs, i.e. ISCE ≈ 2·10−2 A/mm.

These measurements show that the “true” gate leakage (IG,leak), canbe effectively estimated only after decoupling it from the other undesiredcontributions to IG. After the introduction of the insulated pads, andeffective comparison of IG,leak of HEMTs fabricated on different epilayerscan be carried out. Figure 4.32b shows a comparison of the leakage currentof gates (LG = 200 nm) fabricated on different layers. HEMTs fabricatedon Layer D, with 10 nm-thick barrier and a Al0.04Ga0.96N back-barriershowed a very low IG,leak = 0.2 µA/mm at VGS = −6 V. The higher IG


-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1-100

-50

0

50

100

-8-6-4-20

LG =

35 nm 50 nm 75 nm 200 nm

I G (µ

A)

VGS (V)

10 µm 30 µm 60 µm

LG =

Figure 4.33: Reverse and forward gate current in linear scale for HEMTsfabricated on Layer C, with the following W = 75 µm, LSD = 4 µm, anddifferent gate lengths. The inset shows a magnification of the plot betweenVGS = −9 and −3 V.

values detected on Layers A and B, may still be caused by a lower Ibuffer

component, flowing through the buffer and pads via the ohmic contactareas. This component may be more effectively suppressed in Layer D,whose Al0.04Ga0.96N back-barrier improved the buffer insulation.

The physical origin of IG,leak, was then further investigated on HEMTswith gate lengths ranging from 35 nm to 60 µm, fabricated on Layer C. Aplatinum metallization was used for the gate contacts, which producedleakage currents one order of magnitude lower with respect to one withnickel. Figure 4.33 shows IG measurements on a linear scale, and displaystwo peculiar features.

The first peculiarity is that the pinch-off-related current step at VGS =

VTH ≈ −3 V ceases to be visible for LG < 10 µm. This can be understoodwith reference to the curve of simulated vertical electric field (Ey) underthe gate as a function of VGS (Fig. 3.9). The absolute value of the electricfield under the gate increases linearly with VGS until the 2DEG is depleted,then remains constant for VGS < VTH. This abrupt slope change in the Ey

vs. VGS curve at (VGS = VTH) gives rise to the step in IG. The slope change


-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1-100

-50

0

50

100

-8-6-4-20

LG =

35 nm 50 nm 75 nm 200 nm

I G (µ

A)

VGS (V)

10 µm 30 µm 60 µm

LG =









-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1-100

-50

0

50

100

-8-6-4-20

LG =

35 nm 50 nm 75 nm 200 nm

I G (µ

A)

VGS (V)

10 µm 30 µm 60 µm

LG =









-10 -8 -6 -4 -2 010-4

10-3

10-2

10-1

100

101

102

103

10 µm 30 µm 60 µm

I G (A

/cm

2 )

VGS (V)

LG =

35 nm 50 nm 75 nm 200 nm

Figure 4.34: Reverse gate leakage for different gate lengths normalized tothe Schottky contact area, measured on HEMTs fabricated on Layer C.

in Ey at the edge of the gate is much smoother (Fig. 3.9). In smaller gates,the field at the gate edge has a stronger influence, smoothing out thetransition and explaining the lack of a noticeable step in IG at VGS = VTH.

The second peculiarity of Fig. 4.33 is that while for LG > 10 µm, IG

scales proportionally with LG, for LG < 10 µm, IG (at VGS VTH) scalesinversely with LG (see inset of Fig. 3.9), i.e., the proportionality of IG withthe gate area is direct for long gates and inverse for the short ones. Thisbehavior is caused by the increased relevance of the field spikes at thegate edges (Fig. 3.10) which produces an increased average field underthe gate as LG shrinks. Additional insight can be obtained by plottingthe leakage current per unit area, shown in Fig. 4.34. The gate leakagecurrent per unit area scales inversely with LG for increasing gate lengthsup to LG = 10 µm, then remains approximately constant for LG > 10 µm.

The strong increase in IG as the field spikes become higher is consistentwith the exponential relation between IG and electric field of the proposedmechanisms of gate leakage, i.e. Frenkel-Poole [51, 52, 53, 54] and direct(Fowler-Nordheim) or trap-assisted tunneling [56, 57]. An expression forFrenkel-Poole leakage current as a function of the electric field was given


in Eq. 3.6, and is replicated here:

JFP = CEy exp

[−

q(φFP −

√qEy/πε0εS

)

kBT

]. (4.7)

For the Fowler-Nordheim tunneling in AlInN-based barriers the followingexpression was found [57]:

JFN = C·E2y· exp− D

Ey, (4.8)

where C and D are constants which depend on the Schottky barrierheight and the effective masses in AlInN. Both Eqs. 4.8 and 3.6 have anexponential dependence with either

√Ey or −1/Ey, and can be reworked

as:

ln(

JFP

Ey

)= −C1

√Ey + B1, (4.9)

andln (JFN) = −C2

Ey+ B2 (4.10)

for Frenkel-Poole and Fowler-Nordheim, respectively. Based on Eq. 4.9some authors [52, 54] suggested that in the range where Ey and VGS arelinearly proportional, a plot of ln (IG/VGS) vs.

√VGS should exhibit a

linear trend when Frenkel-Poole is the main leakage mechanisms. Byanalogy, a plot of ln (IG) vs. (1 − VGS)

−1 should appear linear in thecase of Fowler-Nordheim tunneling. These quantities for a HEMT withLG = 10 µm fabricated on Layer B, are plotted in Fig. 4.35. Note that in theFowler-Nordheim case for the x-coordinate we used (1 − VGS)

−1 insteadof 1/VGS to avoid divergence at VGS ≈ 0 V, a physically sound assumptionclarified by the following discussion. IG measured on a HEMT withLG = 10 µm was used to ensure that edge effects were negligible. Bothplots in Fig. 4.35 exhibit deviations from the linear trend, and no definiteconclusion can be drawn from them, for the following reasons. First,the relationship between Ey and VGS is linear only for VTH < VGS < 0,thus, in thin-barrier material plots such as those in Fig. 4.35 only a verylimited voltage range can be investigated with this strategy, leaving oneunable to identify a clear trend. Second, the Ey ≈ VGS is only a crude



JFP = CEy exp

[−

q(φFP −

√qEy/πε0εS

)

kBT

]. (4.7)



Ey, (4.8)



as:

ln(

JFP

Ey

)= −C1

√Ey + B1, (4.9)

andln (JFN) = −C2

Ey+ B2 (4.10)








JFP = CEy exp

[−

q(φFP −

√qEy/πε0εS

)

kBT

]. (4.7)



Ey, (4.8)



as:

ln(

JFP

Ey

)= −C1

√Ey + B1, (4.9)

andln (JFN) = −C2

Ey+ B2 (4.10)







-2 -1

-8

-7

-6

-5log|I G/V

GS|

V1/2GS (V)

(a)

-2 -1

-9

-8

-7

-6

-5

-4

log(I G)

(1-VGS)-1(V)

(b)

Figure 4.35: Plots of (a) log(IG/VGS) vs. V1/2GS and (b) log(IG) vs. (1−VGS)

−1.The values on the x-axis labels are those of VGS, the values of sqrtVGS and(1−VGS)

−1 are not shown. A linear behavior of the plots in the shown rangemay considered to be signature of (a) Frenkel-Poole or (b) Fowler Nordheim,respectively.

approximation, which neglects the field present below the gate already atVGS = 0 V. A more physical approximation of the voltage-field relationcan be computed assuming a donor doping ND in the barrier [72]:

Ey =ΦB/q − VGS

w, (4.11)

where ΦB is the Schottky barrier height and w =√

2εΦBNDq2 is the depletion

region width under the gate contact. Equation 4.11 also provides a justi-fication for using (1 − VGS)

−1 instead of 1/VGS for Fig. 4.35. Because Ey

and VGS are not simply proportional, the plots of Fig. 4.35 are in generalnot describable by Eqs. 4.9 and 4.10. The linearity plots are therefore anineffective tool to assess the conduction mechanism of the reverse-biasgate leakage.

A more insightful investigation strategy is to analyze the behavior ofreverse-bias gate leakage versus temperature. This was carried out in thiswork by means of simulations and cryogenic measurements of HEMTs.The simulated curves of Fig. 4.36a were obtained in the following way.


-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 010-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

150 K 100 K 50 K

300 K 250 K 200 K

I G (A

/cm

2 )

VGS

(V)

T=

(a)

-8 -6 -4 -210-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

-8 -6 -4 -2

T= 300 K 250 K 200 K 150 K 100 K 50 K

abs

(I G) (

A/c

m2 )

VGS

(V)

LG = 30 µm

0

LG = 35 nm

VGS

(V)

(b)

Figure 4.36: (a) Simulated Frenkel-Poole leakage characteristics as a functionof temperature (solid curves), compared to a HEMT with LG = 10 µmfabricated on Layer B (dotted curve). For calculating the current, ε = 5.3[56]and φFP = 1.1 eV were used in Eq. 3.6. (b) Measurements of HEMT withLG = 10 µm and 35 nm fabricated on Layer B as a function of temperature.

A simulation of a HEMT with LG = 10 µm fabricated on Layer B wascarried out in Silvaco ATLAS with qualitative agreement to the experi-mental data. Then, the corresponding Ey vs. VGS curves were extractedfrom the simulation. Their values were substituted in Eq. 4.7, and φFP

was varied until good agreement between the calculation and data atT = 300 K was achieved. The temperature in Eq. 3.6 was then changed,and the curves plotted in Fig. 4.36a were computed for each temperature.The calculated Frenkel-Poole leakage curves show a strong temperaturedependence at all VGS bias. Between 300 and 100 K, IG drops by an or-der of magnitude. This strong temperature dependence is not found inthe measured data. IG measured at temperatures T = 300 down to 50 Kshows almost no change with temperature for the long-gate length HEMT,and only small change for LG = 35 nm (Fig. 4.36b). This behavior is incontrast with the thermally-activated Frenkel-Poole leakage mechanism.Instead, it is compatible with Fowler-Nordheim and trap-assisted tunnel-ing mechanisms, where the electron transport is not thermally-activated


-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 010-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

150 K 100 K 50 K

300 K 250 K 200 K

I G (A

/cm

2 )

VGS

(V)

T=

(a)

-8 -6 -4 -210-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

-8 -6 -4 -2

T= 300 K 250 K 200 K 150 K 100 K 50 K

abs

(I G) (

A/c

m2 )

VGS

(V)

LG = 30 µm

0

LG = 35 nm

VGS

(V)

(b)





-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 010-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

150 K 100 K 50 K

300 K 250 K 200 K

I G (A

/cm

2 )

VGS

(V)

T=

(a)

-8 -6 -4 -210-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

-8 -6 -4 -2

T= 300 K 250 K 200 K 150 K 100 K 50 K

abs

(I G) (

A/c

m2 )

VGS

(V)

LG = 30 µm

0

LG = 35 nm

VGS

(V)

(b)





and has a weak temperature-dependence. We therefore conclude thatthe reverse-bias leakage current in our HEMTs originates from one ofthese two mechanisms. In Ref. [72], it was proved that in large Schottkycontacts on AlInN-barrier, these two mechanism are able to achieve goodagreement with the measured data. A physically consistent simulation ofFowler-Nordheim and trap-assisted tunneling currents in deep sub-µmgates requires a full Schrödinger-Poisson simulation, together with theknowledge of the microscopic shape of gate edges; a task that lies beyondthe scope of this work.


98 IV. GaN HEMTs in Small-Signal Operation98 IV. GaN HEMTs in Small-Signal Operation

5GaN HEMTs in Large-Signal Operation

This Chapter characterizes the performance of AlInN-on-GaN HEMTsoperated in large-signal RF operation. Section 5.1 describes the large-signal (“load-pull”) measurement setup and gives an overview of theamplifier classes and their limitations. The following Sections describelarge-signal RF measurements at 10, 40 and 94 GHz, with special attentiondevoted to the load-line analysis at 10 GHz.

5.1 Measurement Setup

The measurement setup used for load-pull measurements is schematicallyrepresented in Fig. 5.1a. On the source-side of the device under test (DUT),an input reference signal at the fundamental frequency of measurement( f0) is fed to the variable attenuator (ATT1) and amplified through AMP1.Directional couplers (CP1) measure the input forward (a1) and backward(b1) partial waves before the measurement probes. At the drain contactof the DUT, directional couplers (CP2) measure the output forward (b2)and backward (a2) partial waves. The output is then terminated by avariable impedance, which enables output matching with two differentstrategies. At f0 = 10 and 40 GHz, matching is provided by mechanical

100 V. GaN HEMTs in Large-Signal Operation

(a)

(b) (c)

CP1 CP2

CP2 CP2 CP3

Figure 5.1: Schematic of the measurement setup used for load-pull measure-ment. Panel (a): Generic setup showing input stage, directional couplers andvariable impedance load. The variable impedance load was implementedwith: (b) Mechanical multi-harmonic tuners by Focus Microwave, Inc (10-40GHz) or (c) Active closed-loop (94 GHz).

multi-harmonic tuners (Fig. 5.1b), which control the impedance of twohigher frequency harmonics. For f0 = 40 GHz, multi-harmonic matchingwas not possible because of the frequency limits of the setup components.At f0 = 94 GHz, the variable output impedance is implemented usinga real-time active loop (Fig. 5.1c). In this case, the wave coming fromthe output of the transistor is partially injected in the loop through anadditional coupler (CP3). In the loop, the signal is amplified and tunedin phase and amplitude by means of a remotely-controlled phase shifterand variable attenuator. The modified wave in the loop is sent back tothe output of the transistor as a backward wave (a2). Because the loadreflection coefficient is ΓL = a2/b2, changing a2 corresponds to changing


(a)

(b) (c)

CP1 CP2

CP2 CP2 CP3




(a)

(b) (c)

CP1 CP2

CP2 CP2 CP3



Measurement Setup 101

Figure 5.2: Load-pull map at f0 = 94 GHz for a GaN HEMTs. The POUT

levels are traced for 1 dB of gain compression. Adapted from [100].

the output load, thus achieving the desired matching.

Each matching strategy sets a limit on the maximum ΓL which canbe achieved at the output. The maximum |ΓL| = 1 is reached when|a2| = |b2|. If matching is implemented with mechanical tuners, the limitis determined by the losses between the DUT and the drain tuner, whichare detrimental to a2. In the case of active-loop matching, the maximumpower of the loop amplifier is usually the bottleneck for the maximum a2.To achieve |ΓL| = 1, the output power of the loop has to be comparableto that of the transistor (|a|2 ≈ |b2|) which is challenging for GaN HEMTswith high POUT. At f0 = 94 GHz, active-loop matching was implementedwith an innovative load-pull setup based on down-conversion [100].

The quantities used in the rest of this chapter are summarized below,along with their definitions as a function of the partial waves measured


at the fundamental frequency f0:

ΓIN = b1/a1, ΓL = a2/b2, PIN = |a1|2 − |b1|2 ,

PAV = |a1|2 , POUT = |b2|2 − |a2|2 , GP = POUT/PIN,

PDC = VDS·ID + VGS·IG, PAE = (POUT − PIN)/PDC.

(5.1)

In a load-pull measurement, ΓL is swept over the Smith chart untilPOUT is maximized. In this procedure POUT is measured at f0 and for agiven gain compression value. In Class A, GP is initially constant thendecreases monotonically with increasing PIN. In Class B, GP is initiallyvery low, then as PIN increases, it reaches a maximum value, then de-creases again. The gain drop from its maximum value identifies the gaincompression level. An example of such measurements for 1 dB of gaincompression is shown in Fig. 5.2. The plot does not represent to themaximum POUT which, as the DUT is driven further into compression,increases up to a plateau level PSAT.

5.1.1 Amplifier Classes

In a load-pull measurement, the quiescent bias point of the transistor ischosen according to the desired class of operation. Class A operation isachieved for VGS ≈ VTH/2, usually close to the peak gm of the transistor,while Class B is achieved for VGS = VTH. As shown later, various classesoffer different efficiency/linearity tradeoffs.

Additional insight on the operation classes comes from the the inves-tigation of the loadline of the transistor. The loadline is the I-V curve ateither the gate or drain of the transistor with an active large RF signal. Theloadlines of an ideal transistor in Class A and Class B are schematicallyshown in Fig. 5.3 for maximum POUT (PSAT). The operation class is deter-mined by the quiescent bias with the RF signal off (VGS, VDS) resultingin a drain current Ibias. In the following discussion, we clarify how theoperation classes influence PSAT and PAE achieved at the fundamentalfrequency f0. For clarity, the time-dependent current and voltages will be



ΓIN = b1/a1, ΓL = a2/b2, PIN = |a1|2 − |b1|2 ,



(5.1)







ΓIN = b1/a1, ΓL = a2/b2, PIN = |a1|2 − |b1|2 ,



(5.1)






Ibias,B

Class AClass B I

D,MAX

I D

VDS

VKnee

Ibias,A

=IDC,A

BVOFF

IDC,B

Figure 5.3: Loadlines for operation Class A (dashed line) and B (dottedline), superimposed to ideal I-V characteristics of a transistor. Ibias,A andIbias,B represent the drain current with the RF input signal turned off forClass A and B, respectively. When the RF signal is turned on, the DC-current measured at the drain is equal to IDC,A and IDC,B for Class A and B,respectively.

indicated as I and V through the rest of the chapter.

With the RF signal on we find the time-dependent voltage and currentVDS(t) and ID(t) at the drain of the transistor. In general, VDS(t) and ID(t)also carry energy at frequencies higher than the fundamental ( f0). Thehigher harmonics have frequencies:

fi = (i + 1) · f0. (5.2)

The voltage and current measured at the drain of the transistor, includingall harmonics are thus expressed as:

VDS(t) = VDS +12

N

∑i=0

Vi e j(2π fi t) (5.3)

where j is the imaginary unit and Vi is the peak-to-peak amplitude of thevoltage at the i-th harmonic. The sum is carried out over the N harmonicswhich carry a non-negligible signal. An analogous expression for the


0.0

0.5

1.0

0.0

0.5

1.0

0° 60° 120° 180° 240° 300° 360° 420°0.0

0.5

1.0 f0

f0

Class B

Class A

Ibias

Iself

Class AB

Iself

Ibias

= 0

IDC= I

bias

IDC= I

self

Ibias

I D/I D

,MAX

IDC=I

self+I

bias

α

θ

α

(a)

0° 60° 120° 180°0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

∆PSAT(dB)o

r(I s

elf/I

D,MAX)

Iself

Class AB

Class B

Clipping (α)

Class A

(b)

Figure 5.4: (a) Time-domain waveform of the drain current in Class A, ABand B, respectively. The ID(t) curve (solid line) including all harmonics isplotted versus θ = 2π f0t. The dotted line represents fundamental frequency( f0) component, which in Class A coincides with ID(θ). The plots also showthe ID value when the RF signal is off (Ibias, dash-dotted line) and the self-bias component with RF signal on (Iself), which added together produce theaverage value of ID(θ), called IDC (dashed line). (b) Self-bias current (Ibias)(dash-dotted line) and increase of POUT with respect to the PSAT of Class A,as a function of the clipping angle α which determines the operation class.

current can be found:

ID(t) = ID +12

N

∑i=0

Ii e j(2π fi t−Φi), (5.4)

where Φi is the phase difference with respect to the voltage, determinedby the load impedance. From the definitions above, it follows that thetotal root mean square (RMS) power found at the output is:

PTOT,OUT = Re(

1T

∫ T

0VDS(t) I∗D(t) dt

)= PDC +

18

N

∑i=0

Vi Ii cos(Φi), (5.5)

where PDC is the DC power, and the second term is the total RF power,including all the N harmonics. An ideal load matching achieves Φi = 0,


0.0

0.5

1.0

0.0

0.5

1.0

0° 60° 120° 180° 240° 300° 360° 420°0.0

0.5

1.0 f0

f0

Class B

Class A

Ibias

Iself

Class AB

Iself

Ibias

= 0

IDC= I

bias

IDC= I

self

Ibias

I D/I D

,MAX

IDC=I

self+I

bias

α

θ

α

(a)

0° 60° 120° 180°0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

∆PSAT(dB)o

r(I s

elf/I

D,MAX)

Iself

Class AB

Class B

Clipping (α)

Class A

(b)



ID(t) = ID +12

N

∑i=0



PTOT,OUT = Re(

1T

∫ T

0VDS(t) I∗D(t) dt

)= PDC +

18

N

∑i=0




0.0

0.5

1.0

0.0

0.5

1.0

0° 60° 120° 180° 240° 300° 360° 420°0.0

0.5

1.0 f0

f0

Class B

Class A

Ibias

Iself

Class AB

Iself

Ibias

= 0

IDC= I

bias

IDC= I

self

Ibias

I D/I D

,MAX

IDC=I

self+I

bias

α

θ

α

(a)

0° 60° 120° 180°0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

∆PSAT(dB)o

r(I s

elf/I

D,MAX)

Iself

Class AB

Class B

Clipping (α)

Class A

(b)



ID(t) = ID +12

N

∑i=0



PTOT,OUT = Re(

1T

∫ T

0VDS(t) I∗D(t) dt

)= PDC +

18

N

∑i=0




thus maximizing the output power. In Class A, for an ideal transistor,no signal is carried at frequencies higher than the fundamental. Theloadline is linear and the maximum RF output power reduces to PSAT =

(BVOFF − VKnee)ID,MAX/8 (see Fig. 5.3).

To achieve Class A, the quiescent point is chosen so that Ibias is equalto ID,MAX/2. When VGS of the quiescent point is brought closer to VTH,additional harmonics are generated. This modifies the maximum PAEand PSAT, as shown in the following. For Class B (VGS ≈ VTH) the ID(t)curve is clipped (ID = 0) whenever VGS(t) < VTH. To quantify thisclipping we define the angle α, and write Eqs. 5.3 and 5.4 as a functionof the phase θ = 2π f0t. The angle α is defined so that ID(θ) is clippedfor 180 − α/2 < θ < 180 + α/2 (see Fig. 5.4a). VDS(θ) instead, is notclipped and retains its sinusoidal shape. The magnitude of α, as well asPSAT and PAE, are determined by the choice of VGS. In Class A, we haveα = 0. ID(θ) is sinusoidal, thus its RF-part has a null average. Neglectingthe gate contribution to the DC-power we get PDC = Ibias·VDS. BecauseIbias = ID,MAX/2 and PSAT = (2VDS − VKnee)·ID,MAX/8, it follows that themaximum PAE which can be achieved in Class A is 50% (for VKnee = 0).

To achieve Class B, the quiescent point is chosen so that VGS = VTH.When the RF signal is off, at the output we find Ibias = 0. When the RFsignal is turned on PSAT is reached for the maximum current, i.e., whenID(θ) ranges between ID,MAX and 0. The output signal is a cosinusoidclipped off for half its period (α = 180), with amplitude ID,MAX (see Fig.5.4a). Because of the clipping, ID(θ) carries a non-zero signal at harmonicshigher than f0. It can be proven that the f0-component of ID(θ) has thesame magnitude as that of Class A (Fig. 5.4a, dotted line), the maximumRF output power at f0 is therefore the same. Because of the clipping,however, the RF part of ID(θ) has a non-zero average and influences theDC power and the PAE. The non-vanishing average of ID(θ) is calledself-bias current and is equal to Iself = IDC = ID,MAX/π. Because IDC islower than Class A, the maximum PAE in Class B is 78.5%. The idealloadline of Class B, for a transistor with a linear transfer curve, is shownin Fig. 5.3.


In the intermediate Class AB ID(θ) is clipped off in a smaller rangewith respect to Class B, i.e., 0 < α < 180 (see Fig. 5.4a). The clippingangle impacts te amount of signal at the fundamental frequency f0, andthus PSAT. By Fourier analysis it can be proven that the f0 componentof ID(θ) is higher than both Classes A and B, and reaches a maximumfor α ≈ 115. The maximum output power in this condition is 0.3 dBhigher than Classes A and B. In Class AB, the RF part of ID(θ) also hasa non-zero DC-component Iself which adds to the bias current Ibias. Themaximum PAE of Class AB is thus determined by the value Ibias + Iself

when α = 115. The value of Ibias in this condition depends on theparticular ID vs. VGS curve of the transistor. Finally, to summarize thedifferences between classes of operation, a plot of PSAT and Iself as afunction of the clipping angle α is shown in Fig. 5.4b.

5.2 Large-Signal Measurements at 10 GHz1

In this Section, we present large-signal measurements of HEMTs fabri-cated with two AlInN/GaN epilayer structures. The two structures hadthe same barrier thickness, and were identical except for a different caplayer, i.e., an AlN (Layer C) or GaN cap (Layer B). The full layer structures,as well as DC and small-signal measurements of devices fabricated onthem, are presented in Sec. 4.3.1. The HEMTs presented in this Sectionhad the following geometry: LSD = 4 µm, LG = 200 nm, LH = 600 nm,W = 150 µm. In order to reduce RS, the gates were offset toward thesource, achieving a source-gate spacing of 0.75 µm.

5.2.1 Load-Line Analysis

Load-pull measurements at 10 GHz were performed in a multi-harmonicsetup which enabled the detection of the 20, 30 and 40 GHz harmonics.The detection of the higher frequency components permit a more accurate

1Parts of this Section were adapted from [88] ©2013 IEEE.

















Large-Signal Measurements at 10 GHz 107

0 10 20 30 40 50 60 70 80

-0.4

0.0

0.4

0.8

1.2

1.6

-15 -12 -9 -6 -3 0 3 6-1.5

-1.0

-0.5

0.0

0.5

1.0

20.2 15.6 5.0 1.3

I D (A

/mm

)

VDS (V)

VMIN

(b)(a)

VMAX

PIN

(dBm)= CCW

I G (A

/mm

)VGS (V)

r(t)

T(t)

CW

Figure 5.5: Loadlines for different PIN values (see legend) for drain (a) andgate (b) measured at f0 = 10 GHz, plus the higher harmonics f1,2,3 =

20, 30, 40 GHz. The figure shows the loadlines both embedded (dotted lines)and de-embedded (solid lines) from the pad parasitics. The load ΓL =

0.812 < 23.4 was selected to maximize PSAT. The corresponding powersweep is shown in Fig. 5.6. The arrows (dotted grey) indicate the clockwise(CW) and counterclockwise (CCW) rotation along the gate loadline.

representation of the loadline of the transistor, giving insights on thebehavior of the device [101].

Loadlines of an AlN-capped HEMT at 10 GHz for different inputpowers are shown in Figs. 5.5a and 5.5b for drain and gate, respectively.The loadlines were de-embedded from the the pad parasitics in thefollowing way. A 4x4 de-embedding matrix was computed with thehypothesis of a standard Open-Short de-embedding [102, 103]. The I-Vvalues at the drain and gate contacts were computed from the measureda1,2 and b1,2 partial waves, measured with the measurement planes at theprobes tip. Through the 4x4 de-embedding matrix, the reference planeswere shifted to the ohmic contacts/pad interface. The measurement padparasitics are thus removed, while the effect of the ohmic contacts is still


included. Figure 5.5 shows the load-lines before (solid lines) and after(dotted lines) de-embedding. The de-embedding reduces the loadlineswidth, consistently with the reduction of the reactive part of the outputimpedance.

An inspection of the gate loadline of Fig. 5.5b provides insights onthe gate conduction mechanism. For PIN > 15.6 dBm, the gate loadlineexhibits a loop ring around VGS ≈ 3 V. The loop may be attributed toa change in the reactive nature of the gate impedance. To support thisexplanation, we define the vectors

r(t) =(VGS(t), IG(t)

)and T(t) =

(∂VGS(t)

∂t,

∂ IG(t)∂t

), (5.6)

where T(t) is the tangent vector to the (VGS(t), IG(t)) curve. The twovectors of Eq. 5.6 thus represent the position and “velocity” of a pointmoving on the loadline, respectively. The loadline of Fig. 5.5b and itstangent vector are described by the real parts of r(t) and T(t). A looplike the one visible at VGS ≈ 3 V corresponds to a change in the rotationdirection along the loadline from clockwise to counterclockwise (seearrows in Fig. 5.5b), or the opposite. The rotation direction along theloadline is determined by the direction of the vector

M(t) = Re r(t)× Re T(t), (5.7)

i.e., by the sign of its component Mz along the z axis. With the z axisdefined as perpendicular to the I-V plane and pointing toward the reader,Mz > 0 and Mz < 0 represent a clockwise and counterclockwise rota-tion along the loadline, respectively. Now let’s assume that, for a smallsection of the loadline, we can write VGS(t) = ZG IG(t), where only theRF-components of VGS(t) and IG(t) are considered. Additionally, let’sconsider a small section of the loadline so that ZG is time-independent.Under these assumptions, making use of the definitions of Eqs. 5.6 and5.7 we find:

Mz = − Im ZG

Re Z2G· Im

(VGS(t)∗

∂VGS(t)∂t

)= − Im ZG

Re Z2G·

N

∑i=0

(2π fi)Re V2i ,

(5.8)





)and T(t) =

(∂VGS(t)

∂t,

∂ IG(t)∂t

), (5.6)


M(t) = Re r(t)× Re T(t), (5.7)


Mz = − Im ZG

Re Z2G· Im

(VGS(t)∗

∂VGS(t)∂t

)= − Im ZG

Re Z2G·

N

∑i=0

(2π fi)Re V2i ,

(5.8)





)and T(t) =

(∂VGS(t)

∂t,

∂ IG(t)∂t

), (5.6)


M(t) = Re r(t)× Re T(t), (5.7)


Mz = − Im ZG

Re Z2G· Im

(VGS(t)∗

∂VGS(t)∂t

)= − Im ZG

Re Z2G·

N

∑i=0

(2π fi)Re V2i ,

(5.8)


0 4 8 12 16 20

5

10

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25

30P

OU

T (dB

m),

PA

E (%

)

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PAE

PIN,DEL (dBm)

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(b) Layer B

GP

GP

(dB

)

6.6 W/mm

(a) Layer C

Figure 5.6: Large-signal measurements at 10 GHz for HEMTs having LSD =

4 µm and LG = 200 nm fabricated on Layers C (a) and B (b) epilayers ΓL was0.812 < 23.4 and 0.71 < 17.1 and the bias conditions were (VGS, VDS) =

(−3.9, 40) and (−4.2, 45) V, respectively. The loadlines corresponding to theblack dots in (a) are shown in Fig. 5.5.

using for VGS(t) an expression analogous to Eq. 5.3. An inspection ofEq. 5.8 shows that the only non-positive term is Im ZG. The change ofthe reactance of ZG from capacitive (Im ZG = −1/(2π fi)C) to induc-tive (Im ZG = (2π fi)L) produces a change in the sign of Mz, thus achange in the turning direction of the loadline. If ZG is related to the gateimpedance, this change may caused by the gate entering the forward-bias region. In reverse-bias, the Schottky contact reactance has mostlya capacitive-character, but when it enters forward-bias it assumes aninductive-character. The loop observed for VGS ≈ 3 could be associatedwith the gate losing its blocking character for high enough PIN values.

5.2.2 Large-Signal Measurements at 10 GHz

Figures 5.6a and 5.6b show large-signal power sweeps performed at10 GHz on Layer C (AlN cap) and Layer B (GaN cap), respectively. The


quiescent points of Figs. 5.6a and 5.6b were (VGS, VDS) = (−3.9, 40)and (−4.2, 45) V, respectively. The bias was chosen in order to achievemaximum output power, taking into account the restriction imposed bybreakdown voltage and channel control of each device. At their quiescentpoint, the devices had a drain current equal to about 10%ID,MAX, thusachieving Class AB operation. With the load optimized for maximumoutput power (ΓL = 0.812 < 23.4), saturated output power was achievedfor PIN = 20 and 24 dBm, with a gain compression of 10 dB and 4 dB,respectively. The AlN-capped device presented a higher maximum gainGP = 17.6 versus 13 dB for the GaN-capped device. However, due to morepronounced compression of the AlN-capped HEMTs, the gains becamesimilar around PIN = 20 dBm, where the maximum PAE = 22%, wasachieved for both devices. With the device geometries detailed above, thetypical maximum output powers were 3.5-5.4 W/mm, and 3.5-6.6 W/mmfor AlN- and GaN-capped HEMTs, respectively.

An inspection of the two broadest loadlines in Fig. 5.5a, correspondingto PIN = 15.6 and 20.2 dBm, shows that they are superimposed to eachother around VDS = 20 V. This suggests that deeper traps can be activatedby the high electric fields achieved in this regime, producing an additionalincrease of the on-resistance and knee walkout in RF operation. This limitsthe expansion of the load-line at the lower voltage end, and is probablyresponsible of the sub-optimal PAE. Additionally, sustained operationwith the strong gain compression attained at PIN = 20.2 dBm leads todevice degradation. One possible cause for this degradation could be theforward-biasing the Schottky junction, indicated by the loopiness of theloadlines, as explained in the previous Section. It has been shown thatDC forward bias of the gate junction causes degradation of AlGaN-baseddevices [104]. Loadline analysis suggests that strong forward conductioncould be one of the degradation mechanisms for GaN-devices operatedin conditions of significant gain compression, also when the forward biasis caused by the RF signal.

Because the devices were optimized for operation at 40 GHz, thepower values are not representative of the maximum potential of theAlInN-GaN material system at 10 GHz [105]. HEMTs can be differently










optimized for large-signal performance at 10 GHz implementing longergate lengths, as well as field plates. Because ultra-short gates are notnecessary for large-signal operation at 10 GHz, the performance of AlInN-HEMTs would be enhanced by a thicker barrier epilayer ([106]) whichwould allow higher currents while maintaining good channel control inHEMTs with longer gate lengths.

5.3 Large-Signal Measurements at 40 GHz

This Section presents results from load-pull measurements at 40 GHz. Inthe first part, AlN-capped (Layer C) HEMTs with different LSD spacingsand a constant gate length of 200 nm are compared. In the second part,the best results achieved at 40 GHz, with the optimized LSD spacing arepresented. The performance achieved in terms of PSAT exceeds the bestresults published in literature for AlInN-based HEMTs at 40 GHz [107].

5.3.1 AlN-capped HEMTs Geometry Optimization2

This Section presents large-signal measurements for HEMTs simultane-ously fabricated on Layer C, with different source-drain spacing. Theload-pull measurements were carried out with our passive load-pullsetup, and ΓL was chosen to to maximize PSAT.

The devices were fabricated as follows. Ohmic contacts were formedby Ti/Al/Mo/Au, and linear TLM data revealed a contact resistanceof 0.3 Ω·mm. Source-drain spacings ranging from 0.5 to 4 µm wereimplemented on the same chip. For devices with LSD = 4 µm the gateswere offset toward the source, achieving source-gate spacings of 0.75 µm,otherwise, for devices with LSD = 0.5 and 2 µm, the gates were equallyspaced from the source and the drain. The two-finger gate electrodes hada total width of 100 µm and gate head lengths of 200 and 600 nm forLSD = 0.5 and 2 or 4 µm, respectively, while a gate length of 200 nm was

2Parts of this Section were adapted from [108] ©2013 The Japan Society of AppliedPhysics.


2 4 6 8 10 12 14 16 18

-5 -4 -3 -2 -1 010-5

10-4

10-3

0 2 4 6 80.0

0.5

1.0

1.5

2.0

LSD

= 0.5 µm-3 V

-1 V

0 V

VGS= 1 V

-2 V

VDS (V)

-4 V

(a) (b)

4 µm 0.5 µm

I G (A

/mm

)

VGS

(V)

0.01

0.1

1

10

I D (A

/mm

)

I D (A

/mm

)

VDS (V)

VGS

= 0 V

-1 V

-2 V

-3 V

Figure 5.7: (a) DC (solid line) and pulsed I-V characteristics of a 200 nmgate length device with LSD = 0.5 µm, where VGS is varied from 0 to −3 Vin steps of 1 V. Dotted line: pulsed from (VGS, VDS) = (0, 0) V; dashed line:pulsed from (VGS, VDS) = (−4, 8) V. Pulse width= 500 ns, period= 10 µs.(b) DC (solid line) and pulsed I-V characteristics of a 200 nm gate lengthdevice with LSD = 4 µm VGS is varied from 1 to −4 V in steps of 1 V.Dotted line: pulsed from (VGS, VDS) = (0, 0) V; dashed line: pulsed from(VGS, VDS) = (−5, 10) V. Pulse width= 500 ns, period= 10 µs. Inset: reverse-bias gate leakage current (at VDS = 0) and drain current (at VDS = 8) versusgate voltage, for the same gate length and for LSD = 4 µm (solid line) andLSD = 0.5 µm (dash-dotted line).

patterned for all geometries. The gate metal stack consisted of electron-beam evaporated Ni/Au (35/350 nm) forming the gate Schottky contact,subsequently encapsulated in a 70 nm-thick PECVD SiN passivation.

For both LSD = 0.5 and 4 µm, the HEMTs exhibited limited currentdispersion (see Figs. 5.7a and 5.7b). A reduced knee walk-out compared toother devices fabricated on Layer B was observed (see Fig. 4.17). Therefore,we attribute the reduced dispersion to the introduction of the AlN cap.Figure 5.7b(inset) shows the gate leakage current in reverse-bias, and thedrain current for the same two device topologies (see legend). The reverse


2 4 6 8 10 12 14 16 18

-5 -4 -3 -2 -1 010-5

10-4

10-3

0 2 4 6 80.0

0.5

1.0

1.5

2.0

LSD

= 0.5 µm-3 V

-1 V

0 V

VGS= 1 V

-2 V

VDS (V)

-4 V

(a) (b)

4 µm 0.5 µm

I G (A

/mm

)

VGS

(V)

0.01

0.1

1

10

I D (A

/mm

)

I D (A

/mm

)

VDS (V)

VGS

= 0 V

-1 V

-2 V

-3 V





2 4 6 8 10 12 14 16 18

-5 -4 -3 -2 -1 010-5

10-4

10-3

0 2 4 6 80.0

0.5

1.0

1.5

2.0

LSD

= 0.5 µm-3 V

-1 V

0 V

VGS= 1 V

-2 V

VDS (V)

-4 V

(a) (b)

4 µm 0.5 µm

I G (A

/mm

)

VGS

(V)

0.01

0.1

1

10

I D (A

/mm

)

I D (A

/mm

)

VDS (V)

VGS

= 0 V

-1 V

-2 V

-3 V





12 15 18 21 240369

12151821242730

GP

POUT

LSD

= 4 µm L

SD= 2 µm

LSD

= 0.5 µm

PO

UT (d

Bm

) , P

AE

(%)

PIN (dBm)

PAE

0

5

10

15

20

GP

(dB

)

Figure 5.8: POUT (solid line), GP (dotted line), and PAE (dashed line) charac-teristics at 40 GHz versus PIN for Class B biased 2 × (0.1 × 50) µm HEMTs,having different source-drain spacings (color coded, see legend). VGS waschosen to achieve Class AB amplifier operation, VDS was (15, 25, 20) V, forLSD = (0.5, 2, 4) µm, respectively.

leakage was of the order of 10−4 A/mm in all measured devices. Thelogarithmic plot of ID at VDS = 8 V (Fig. 5.7b, inset) shows the pinch-offimprovement achieved with a wider source-drain spacing and the sameLG = 200 nm. At this drain bias, the peak extrinsic transconductance forLSD = 0.5 and 4 µm was of 650 and 470 mS/mm, respectively. Small-signal measurements at peak gm resulted in ( fT, fMAX) = (80, 135) and(70, 125) GHz, for devices with LSD = 0.5 and 4 µm, respectively. Thesebenchmarks are only marginally better in the 0.5 µm-device, because theimprovement in the transconductance due to the reduction of the sourceand drain resistances is compensated by an increased gate resistance,caused by the smaller 200 nm gate head.

Figure 5.8 compares the large-signal performance at 40 GHz for thethree different device geometries. The devices were biased in deep ABClass, with a quiescent point corresponding to 7% ID,MAX. The deviceimplemented with LSD = 0.5 µm (blue curves in Fig. 5.8) was biased atVDS = 15 V, and achieved PSAT = 3.5 W/mm, with a maximum GP =


5.6 dB and PAE = 19%. The device implemented with LSD = 2 µm (redcurves in Fig. 5.8) was biased at VDS = 25 V and achieved 4.1 W/mm. Thehighest PSAT was achieved in devices with LSD = 4 µm (solid green curvein Fig. 5.8) which reached 4.58 W/mm, and also the highest PAE of 24%,when biased at VDS = 20 V. Other devices on the same chip reached powerlevels between 3.8 W/mm and 4.5 W/mm, confirming the homogeneityof the results. Referring to the formula PSAT = (BVOFF − VKnee)ID,MAX/8(Eq. 5.5), it is worth noting that a reduced dispersion has a 2-fold impacton the maximum output power, keeping both the knee voltage (VKnee)and the saturated current (ID,MAX) values under stressed RF operationclose to their DC values. We therefore conclude that a major contributionto the achievement the high power densities reported in this work camefrom the reduced dispersion of the HEMTs.

The higher PSAT in HEMTs with LSD = 4 µm was achieved at 2 dB ofgain compression, as opposed to 3.5 dB compression of the LSD = 0.5 µmdevice. This led to the higher PAE. The higher electric field in the smallsource-drain spacings leads to an increased dispersion, especially visiblea VGS = 0 V, and to higher off-currents (see Fig. 5.7). Both effects aredetrimental to large-signal application and ultimately produce excessivedrawbacks for the smaller source-drain spacings. In conclusion, HEMTswith source-drain spacing of LSD = 4 µm proved to achieve the optimalgeometry for large-signal operation at 40 GHz.

5.3.2 Record Performance at 40 GHz3

Large-signal measurements at 40 GHz were carried out on HEMTs withoptimized geometry, fabricated on Layer B. These HEMTs were subjectedto H+-ion implantation process described in Sec. 4.3.2. The I-V charac-teristics have been shown in Fig. 4.22. Devices on Layer B featured lessnegative pinch-off voltage and a maximum gm = 530 mS/mm, with animprovement over Layer C. The H+-ion implant reduced the magnitudeof ID,OFF, further enhancing the performance.

3Parts of this Section were adapted from [88] ©2013 IEEE and [108] ©2013 The JapanSociety of Applied Physics, respectively.














8 12 16 20 240

5

10

15

20

25

30

POUT

PAE

POUT(dBm),PAE(%

)

PIN (dBm)

5.85 W/mm

2

3

4

5

6

7

GP

GP(dB)

Figure 5.9: Large-signal measurements at 40 GHz for a GaN-capped HEMTs(Layer B) with LG = 200 nm and LSD = 4 µm, biased at (VGS, VDS) =

(−2.6, 35) V, with ΓL = 0.681 < 45.6, optimized for maximum POUT.

Finally, Fig. 5.9 shows large-signal measurement at 40 GHz of aGaN-capped HEMT with the optimized geometry LSD = 4 µm andLG = 200 nm. Because of the better pinchoff achieved with this epi-layer structure, it was possible to obtain good channel control up tohigh VDS with better power gains than the devices fabricated on LayerC. The power sweep shown in Fig. 5.9 was carried out at a quiescentbias of (VGS, VDS) = (−2.6, 35) V, and yielded PSAT = 5.85 W/mm, witha peak GP and PAE of 6 dB and 15.6%, respectively. It is worth notingthat because of the limitations of our load-pull setup, the chosen loadΓ = 0.681 < 45.6, was lying at the very edge of the accessible range.Better matching with an integrated MMIC process, or an improved mea-surement setup with reduced output losses may yield to higher PSAT.Inspection of the single-frequency loadline at PIN = 23.4 dBm, revealedminimum a maximum VDS voltage of 18 and 51 V, respectively. The highvalue of the minimum indicates that some undesired effect, such as apronounced knee walkout may take place when the device is driveninto deep compression and strong gate-drain electric fields are attained.This suggests that the PSAT = 5.85 W/mm may be improved by further


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0.6 W/mm

POUT

PAE

POUT(dBm),PAE(%

)

PIN,DEL (dBm)

0.6 W/mm

10.2%

fMAX(U)

= 250 GHzfT= 130 GHz

1

2

3

4

5

6

7

8

GP

PIN,DEL (dBm)

6.4%

(a) (VGS, VDS) = ( 0.5, 5) V (b) (VGS, VDS) = ( 1, 11) V

2

3

4

5

6

7

8

GP(dB)

fMAX(U)


Figure 5.10: Large-signal measurements at 94 GHz for a GaN-capped HEMTs(Layer B) with LG = 100 nm, LSD = 1 µm, W = 2× 25 µm biased at differentbias points.

optimization both of the epilayer and device to eliminate the residualdispersion.

In conclusion, HEMTs fabricated with both Layers C and B (see Ta-ble 4.2, P. 67) achieved high power densities in excess of 4.5 W/mm at40 GHz. These results reinforce the suitability of AlInN-based devices forhigh power application in the Ka-band and beyond, with 5.85 W/mmbeing the highest power density reported for AlInN-based devices at40 GHz at the time of the publication of the results [88].


Load-pull measurements at 94 GHz were performed in an active closed-loop load-pull setup developed in our laboratory [100]. HEMTs fabricatedon Layer B (GaN cap) were selected and characterized at 94 GHz. Large-signal operation in the W-band with non-vanishing gain required fT >

100 GHz and fMAX > 200 GHz were selected. Gates with LG = 100 nmwere found to provide the optimal tradeoff, providing high cutoff fre-


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POUT

PAE

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10.2%

fMAX(U)


1

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PIN,DEL (dBm)

6.4%


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GP(dB)

fMAX(U)









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0.6 W/mm

10.2%

fMAX(U)


1

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GP

PIN,DEL (dBm)

6.4%


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GP(dB)

fMAX(U)









quency while maintaining a good channel control. The devices werefabricated on Layer B with regrown contacts (see Sec. 2.3). TLM datarevealed post-process ohmic contacts with RC = 0.35 Ω·mm, and a sheetresistance of 250 Ω/. At VGS = 2 V, ID ≈ 1.8 A/mm was achieved, whilea maximum gm of 650 mS/mm was achieved at (VGS, VDS) = (−0.5, 5) V,decreasing to 550 mS/mm for VDS > 5 V. Pinch-off was achieved forVGS ≈ −1.8 V, with an off-state current similar to other HEMTs fabricatedon Layer B presented in Sec. 4.3.1.

Large-signal measurements of HEMTs with LSD = 1 µm and W = 2 ×25 µm are shown in Fig. 5.10. The advantages of homogeneous and low-resistance contacts were more apparent in the smaller-width devices. fMAX

values as high as 275 GHz with LG = 100 nm (see Fig. 5.10, annotation)were achieved thanks to the reduced RG. Fig. 5.10a shows a large-signalmeasurement at (VGS, VDS) = (−0.5, 5) V. The device was operated inClass A and the load was optimized to achieve maximum POUT. At thisquiescent point, the maximum output power was 0.6 W/mm with 10.2%maximum PAE (Fig. 5.10a). Larger output powers were achieved at ahigher VDS = 11 V. At this bias, a more negative VGS = −1 V was applied,but the increased off-current caused by the higher VDS bias made the PAEdrop to 6.4%. This PAE degradation is attributed to SCEs, exacerbatedbecause of the small LSD spacing.

In order to reduce SCEs, a different geometry was tested, with LSD =

2 µm and W = 2 × 50 µm and the same LG = 100 µm. The deviceshad a maximum gm = 590 mS/mm for VDS = 10 V, and fT and fMAX

values of 130 and 220 GHz, respectively. Large-signal measurements per-formed with quiescent points of (VGS, VDS) = (−1.2, 11) and (−1.3, 15) Vare shown in Figs. 5.11a and 5.11b, respectively. The measurements atVDS =11 V provides the best trade-off between high power density andPAE. Simultaneous POUT and PAE of 1 W/mm and 8.5%, respectively,were achieved, with a PSAT = 1.5 W/mm. PSAT could be further improvedup to a record 1.69 W/mm at VDS = 15 V, albeit with a drop in PAE(Fig. 5.11b). These power densities represent a record for large-signalRF operation at 94 GHz for on-wafer measurements of any GaN-baseddiscrete device, as opposed to pre-matched ones [17]. In terms of PSAT,


6 8 10 12 14 16 18 20 220

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3

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POUT(dBm),PAE(%

)

PIN,DEL (dBm)

(a) (VGS, VDS) = ( 1.2, 11) V (b) (VGS, VDS) = ( 1.3, 15) V

0

1

2

3

4

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6

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1.2 W/mm, 5%

1 W/mm, 8.5%

1.51 W/mm

POUT

PAE

PIN,DEL (dBm)

0

1

2

3

4

5

6

7

8

GP

GP(dB)

1.69 W/mm


one single device fabricated at our laboratory outperforms full MMICamplifiers presented in Ref. [15, 16] and [109], matching the best AlGaN-based MMIC [17]. However, PAE is still lower, which is attributed toSCEs and residual dispersion, which is still non-negligible on HEMTsfabricated on Layer B.

5.5 Summary of Large-Signal Results

In conclusion, we offer a comparison of the performance of out HEMTsin large-signal to some of the best results available in the literature. Fig-ure 5.12 shows how this work compares to other results obtained on bothAlInN- and AlGaN-on-GaN HEMTs. While the power density appearsto decrease at higher frequency, it must be noted that the measurementsreported were carried out on different devices and at different VDS bias.For our HEMTs, load-pull measurements for the device of Fig. 5.10a, atthe same bias conditions, led to consistent power densities of 0.84 and0.96 W/mm at 10 and 40 GHz, respectively. The VDS bias for the otherresults is reported in the caption of Fig. 5.12. In terms of PSAT, our devices


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GP(dB)

1.69 W/mm






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POUT

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GP(dB)

1.69 W/mm





Summary of Large-Signal Results 119

0 20 40 60 80 1000

2

4

6

8

10

12

(f)Crespo, AlInN

IAF, AlGaN MMIC (e)

(a) Thales, AlInN

HRL, AlGaN MMIC (d)

This work, AlInN

IEMN, AlN on Si(b)

PSAT(W

/mm)

Frequency (GHz)

(c) UCSB, AlGaN

Figure 5.12: Summary of large-signal RF performance. The data are takenfrom Refs. [105] (VDS=30 V) (a), [110] (VDS=15 V) (b), [14] (VDS=30 V) (c),[15, 16, 17] (VDS=14 V) (d), [109] (VDS=30 V) (e), and [107] (VDS=20 V) (f)

compare well to the best large-signal data at 40 GHz published on AlInN-on-GaN HEMTs (see (f) in Fig. 5.12). Ref. [107] presents devices withd = 10 nm, while our thinner barrier (d = 6 nm) allows operation up toVDS = 35 V (Fig. 5.9) thanks to the better channel control. Reducing VDS

does not bring great advantages in terms of PAE and GP, which remainlower than Ref. [107]. A thicker barrier may otherwise be beneficial atlower frequencies. Refs. [105] and [14] (see (a) and (c) in Fig. 5.12) havelarger gate-to-channel distances of 11 and 25 nm, respectively, and out-perform our devices at 10 and 40 GHz. Our epilayer characteristics aretherefore ideal for operation at 94 GHz. In terms of PSAT at 94 GHz, oneof our devices alone outperforms the AlGaN-based MMICs reported inRef. [15, 16, 109] and matches Ref. [17]. A new benchmark for AlInN-on-GaN performance in the W-Band is thus established. An improvement inPAE is expected with further refinement of the process to remove residualdispersion and SCEs.


120 V. GaN HEMTs in Large-Signal Operation120 V. GaN HEMTs in Large-Signal Operation

6Summary and Conclusion

6.1 Summary of Results

In the course of this work, significant efforts have been devoted to thedevelopment of a manufacturable and versatile process on AlInN- aswell as AlGaN-based HEMTs. An accurate device characteristics analysisidentified some of the physical mechanisms that limit the performanceof GaN-based HEMTs. This enabled the demonstration of very highcutoff frequencies, establishing some performance records at the timeof publication of the results. The acquired know-how was carried overto large-signal RF measurements, where state-of-the-art results wereachieved, establishing a record for power density at 94 GHz.

The main achievements of this dissertation are summarized below:

• High fMAX and fT were demonstrated with AlGaN-on-silicon HEMTs,establishing a record at the time of the publication of the results. Alow-damage gate recess process was developed at our laboratoryand successfully applied to AlGaN-based HEMTs. This allowed tofuther improve fT and fMAX.

• AlInN-on-SiC HEMTs were fabricated and characterized. The insightgained allowed the design of optimized epilayers, grown by LASPE

122 VI. Summary and Conclusion

Laboratory (Ecole Polytechnique Fédérale de Lausanne). Record-high fT = 205 GHz and fMAX = 230 GHz for fully-passivatedAlInN-based HEMTs were demonstrated. Thin-barrier AlInN-basedHEMTs were developed and optimized, opening the way to excellentlarge-signal RF performance.

• Gate leakage on AlInN-based HEMTs was investigated. Insightson its physical origin, as well as some peculiarities pertaining toultra-small gate length devices were presented. The implementationof insulated pads reduced the impact of buffer leakage currents onthe measurements. The residual gate and buffer leakage currentsdid not impair the large-signal performance.

• A new ohmic contact process using regrown n++-GaN was estab-lished at ETH Zurich, which allowed achieving fMAX = 300 GHzwith practical, fully-passivated devices.

• Large-signal load-pull measurements were carried out at 10, 40,94 GHz on optimized AlInN-on-SiC HEMTs. The best results ob-tained at 40 GHz, POUT = 5.85 W/mm, are above the maximumpower density reported in the literature for AlInN-based HEMTs(5.8 W/mm at 35 GHz [107]).

• The large-signal results at 94 GHz established a new record interms of power density for AlInN-based HEMTs. A single HEMTfabricated during this work outperformed the PSAT of full GaN-based MMIC structures, with 1.69 W/mm at 95 GHz of our HEMTs,versus 1.4 W/mm at 88 GHz of Ref. [15], matching the best AlGaN-based MMIC ever reported [17].

6.2 Outlook

The development of a HEMT, from the epilayer to the large-signal mea-surements, is a lengthy process that requires the synergistic effort of manypeople. During the course of this work, the measurement capabilities of







6.2 Outlook








6.2 Outlook


Outlook 123

our laboratory increased and additional know-how on GaN-based HEMTswas acquired. Hence, the remaining bottlenecks to further performanceextensions were identified. Some of them, as well as possible strategies toaddress them, are reported below.

Short-Channel Effects

Even the best AlInN-on-SiC devices reported here still suffered fromprominent short-channel effects. This motivated the implementation ofthe buffer-side hydrogen implant (Sec. 4.3.2) and back-barrier. The latterapproach showed promising results, with a marked decrease of the OFF-current of the HEMTs. To fully harness the potential of back-barrier layers,additional effort was devoted to improving the epitaxial growth at LASPELaboratory. The main design improvement was an increase of the GaN-channel thickness from 20 nm to 50 nm. Further optimization of theepitaxial growth yielded epilayers improved the transport characteristicsof the epilayers, bringing them on-par with those of the non-back-barrierepilayers presented in this work. The characterization of HEMTs fabricatedon these new layers is ongoing, and an improvement in terms of large-signal performance is expected.

Power-Added Efficiency

While the results reported in Chap. 5 excel in terms of high-power atfrequencies higher than 40 GHz, the literature presents higher power-added efficiency (PAE) [15, 107]. Improvements of the PAE may alreadyfollow from the reduction of the short-channel effects outlined in theprevious paragraph. The devices fabricated on the improved epilayer arecurrently under test and may be able to operate closer to Class B, thusimproving PAE.

The other major impediment to a high PAE is the current collapse.Significant knee-voltage walkout was still observed on the devices withachieved the record POUT = 1.69 W/mm. It is still unclear whether the


traps causing the dispersion come from the processing or are alreadypresent in the as-grown layer. Because its investigation requires signifi-cant trial-and-error and currently requires a full device process, quickerdiagnostic tools should be developed. For example, the developmentof deep-level transient spectroscopy (DLTS) techniques may enable thedetection of deep traps without completing a full device process. Theprocess-induced dispersion may be assessed more efficiently by fabricat-ing structures aimed at measuring current collapse. For example, opticallyprocessed HEMTs may enable a quicker feedback on the processing out-come and allow testing of a wider range of processing conditions.

Process Improvements for a New Generation of AlInN-HEMTs

The introduction of the regrown ohmic contact process opens the wayto new processing developments. On of them is the downscaling of thesource-drain distance below 0.5 µm, for example by a self-aligned gate-first process. This may bring significant improvements in fT and fMAX,however, the breakdown voltage may become a bottleneck for the large-signal performance.In the devices currently under test, a contact resistance of 0.25 Ω/mm wasconsistently achieved on AlInN-based layers. Refinements of the interfacebetween the regrown n++-GaN and the GaN-buffer may enable contactresistances lower than 0.2 Ω/mm, further boosting fMAX.

The know-how and measurement capabilities attained during thiswork put our laboratory in a favorable position to deliver the highestpower densities at the high frequency of 94 GHz. Solving the issuesoutlined above would allow to harness the full potential of AlInN-basedHEMTs.











125

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[87] E. Arslan, S. Bütün, Y. Safak, and E. Ozbay, “Investigation oftrap states in AlInN/AlN/GaN heterostructures by frequency-dependent admittance analysis,” Journal of Electronic Materials,vol. 39, no. 12, pp. 2681–2686, 2010.

[88] S. Tirelli, L. Lugani, D. Marti, J.-F. Carlin, N. Grandjean, andC. Bolognesi, “AlInN-based HEMTs for large-signal operation at40 GHz,” Electron Devices, IEEE Transactions on, vol. 60, no. 10, pp.3091–3098, Oct 2013.

[89] H. Sen, J. Qimeng, Y. Shu, T. Zhikai, and K. J. Chen, “Mechanism ofPEALD-grown AlN passivation for AlGaN/GaN HEMTs: Compen-sation of interface traps by polarization charges,” Electron DeviceLetters, IEEE, vol. 34, no. 2, pp. 193–195, 2013.

[90] Q. Fareed, A. Tarakji, J. Dion, M. Islam, V. Adivarahan, and A. Khan,“High voltage operation of field-plated AlInN HEMTs,” Phys. StatusSolidi C, vol. 8, no. 7–8, pp. 2454–2456, 2011.

[91] G. H. Jessen, R. C. Fitch, J. K. Gillespie, G. Via, A. Crespo,D. Langley, D. J. Denninghoff, M. Trejo, and E. R. Heller,“Short-channel effect limitations on high-frequency operation ofAlGaN/GaN HEMTs for T-gate devices,” Electron Devices, IEEETransactions on, vol. 54, no. 10, pp. 2589–2597, 2007.

[92] M. Gonschorek, J.-F. Carlin, E. Feltin, M. Py, and N. Grandjean,“High electron mobility lattice-matched AlInN/GaN field-effect

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[93] A. Malmros, H. Blanck, and N. Rorsman, “Electrical properties,microstructure, and thermal stability of Ta-based ohmic contacts an-nealed at low temperature for GaN HEMTs,” Semiconductor Scienceand Technology, vol. 26, no. 7, p. 075006, 2011.

[94] C. Wang and N.-Y. Kim, “Electrical characterization and nanoscalesurface morphology of optimized Ti/Al/Ta/Au ohmic contact forAlGaN/GaN HEMT,” Nanoscale Research Letters, vol. 7, no. 1, pp.1–8, 2012.

[95] D. Brown, K. Shinohara, A. Williams, I. Milosavljevic, R. Grabar,P. Hashimoto, P. Willadsen, A. Schmitz, A. Corrion, S. Kimet al., “Monolithic integration of enhancement and depletion-modeAlN/GaN/AlGaN DHFETs by selective MBE regrowth,” ElectronDevices, IEEE Transactions on, vol. 58, no. 4, pp. 1063–1067, 2011.

[96] F. Iucolano, F. Roccaforte, F. Giannazzo, and V. Raineri, “Influenceof high-temperature GaN annealed surface on the electricalproperties of Ni/GaN Schottky contacts,” Journal of Applied Physics,vol. 104, no. 9, p. 093706, 2008.

[97] J. Kuzmik, A. Kostopoulos, G. Konstantinidis, J. F. Carlin,A. Georgakilas, and D. Pogany, “InAlN/GaN HEMTs: a firstinsight into technological optimization,” Electron Devices, IEEETransactions on, vol. 53, no. 3, pp. 422–426, 2006.

[98] W. Saito, M. Kuraguchi, Y. Takada, K. Tsuda, I. Omura, and T. Ogura,“High breakdown voltage undoped AlGaN-GaN power HEMT onsapphire substrate and its demonstration for DC-DC converterapplication,” Electron Devices, IEEE Transactions on, vol. 51, no. 11,pp. 1913–1917, 2004.

[99] V. Adivarahan, J. Yang, A. Koudymov, G. Simin, and M. A. Khan,“Stable CW operation of field-plated GaN-AlGaN MOSHFETs at 19

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[101] V. Kaper, V. Tilak, B. Green, R. Thompson, T. Prunty, L. F. Eastman,and J. R. Shealy, “Time-domain characterization of nonlinear opera-tion of an AlGaN/GaN HEMT,” in 61st ARFTG Conference Dig., pp.97–102, Philadelphia, PA, 2003.

[102] X. Wei, G. Niu, S. Sweeney, Q. Liang, X. Wang, and S. Taylor, “A gen-eral 4-port solution for 110 GHz on-wafer transistor measurementswith or without impedance standard substrate (ISS) calibration,”Electron Devices, IEEE Transactions on, vol. 54, no. 10, pp. 2706–2714,Oct 2007.

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[107] A. Crespo, M. M. Bellot, K. D. Chabak, J. K. Gillespie, G. H. Jessen,V. Miller, M. Trejo, G. D. Via, D. E. Walker, B. W. Winningham,H. E. Smith, T. A. Cooper, X. Gao, and S. Guo, “High-power Ka-band performance of AlInN/GaN HEMT with 9.8-nm-thin barrier,”Electron Device Letters, IEEE, vol. 31, no. 1, pp. 2–4, 2010.

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141

List of Figures

2.1 HEMT fabrication process flow. . . . . . . . . . . . . . . . . 10

2.2 (a) Etch rate versus time on an AlGaN-GaN epilayer withand without metal on the surface. (b) Etch rate versus timeon the AlInN-based Layer D. (c) Sheet resistance as-etched(black line) and after 5s rapid annealing at 500 (red line)of AlGaN-on-Si samples. The inset shows a micrograph ofa 15 nm-deep recess. . . . . . . . . . . . . . . . . . . . . . . 15

2.3 (a) 3D image generated from AFM scans of a 70 nm-wide,8 nm-deep recess in a LSD = 1 µm spacing. The roughannealed ohmic contact morphology is also visible on thesides. (b) Detailed scan of the recess area. . . . . . . . . . . 16

142 List of Figures

2.4 EDX measurements of an annealed Ti/Al/Mo/Au metalstack on AlInN-on-SiC layers. The leftmost micrographshows the rough surface morphology and the area wherethe FIB cross-section is performed. On the right side, theSEM image of the cross-section (grayscale) is shown, aswell as EDX-mappings of different elements (color-coded).A higher brightness of each image corresponds to a higherconcentration of the element. . . . . . . . . . . . . . . . . . 18

2.5 (a) Schematic drawing of a regrown contact cross-section,showing the electron conduction path from the metalliza-tion to the 2DEG. (b) Micrograph after etching the ohmiccontact areas (right side), recessed by 20 nm. The SiO2

mask is shown in dark grey (left side). (c) Micrograph ofthe ohmic contacts after regrowth. The n++-GaN is shownin light blue. The dark spots are pits in the regrown layer,probably originating from defects or impurities on thegrowth surface. The SiO2 mask is still visible on the left(dark grey). . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Lattice constant and bandgap of nitride compounds andsome other common semiconductors. Adapted from [39]. 24

3.2 Panel (a): Structure of GaN with relevant crystal planes.Panel (b): illustration of the Ga-face polarization. Adaptedfrom [40, 41]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3 Spontaneous and piezoelectric polarization in Al1−xInxNand AlxGa1−xN versus composition. The substrate latticeconstant is taken as that of relaxed GaN. . . . . . . . . . . 26

3.4 Panel (a): A basic GaN epilayer for HEMTs. Panel (b): Sur-face and interface charges and (c) conduction band edge(EC) profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.5 Mobility components in an AlGaN/GaN epilayer struc-ture, ∆ represents the RMS roughness and λ the lateralroughness correlation. Adapted from [46]. . . . . . . . . . 28

142 List of Figures









142 List of Figures









143

3.6 Model (solid lines) and typical DC (dotted lines) I-V char-acteristics of a HEMT. Most of the common non-idealitiesin GaN-based HEMTs are highlighted. . . . . . . . . . . . . 30

3.7 Panel (a): Scheme of the resistance network on the source-side of an HEMT from the metallic contact to the 2DEG.contact. Panel (b): schematic conduction band diagramof non-annealed ohmic contacts. Panel (c) cross-sectionalSEM micrograph of an annealed ohmic contact on anAlGaN/GaN epilayer. . . . . . . . . . . . . . . . . . . . . . 32

3.8 Schematic representation of the possible reverse conductionmechanisms through a Schottky contact. The circles rep-resent trap states. The gray quantities represents the bandprofile and the mechanism of conduction in the Frenkel-Poole case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.9 Panel (a): Scheme of a Schottky contact on a GaN-basedHEMT showing the regions of high field. Panel (b): Fieldunder the middle of the gate and at the edge, showing thedifferent behavior with different gate lengths. . . . . . . . 36

3.10 Vertical field (Ey) profile along the x direction, 0.5 nmbelow a Ni-on-AlInN Schottky contact, extracted from asimulation. The difference between short and long gateswidens as the bias becomes more negative. . . . . . . . . . 37

3.11 Panel (a): Simulated I-V characteristics of a HEMT withLG = 75 nm for VGS = 0 to −6 V in 2 V steps. Panel (b):current density in the region below the gate at (VGS, VDS) =

(−6, 8) V. The 2DEG is located at y = 0. The legend showsthe value of log[J/(A/cm)]. . . . . . . . . . . . . . . . . . . 38

3.12 Simulation of the electron concentration under a gate con-tact biased in different conditions. The legend shows thevalue of log(ns/cm−3). Panel (a): (VGS, VDS) = (−6, 8) V.Panel (b): (VGS, VDS) = (−6, 0) V. . . . . . . . . . . . . . . . 39

144 List of Figures

3.13 Panel (a): Effect of different buffers on the conduction band(EF = 0). Panel (b): Electron concentration. . . . . . . . . . 41

3.14 Simulated I-V characteristics for VGS=0 to −6 V in −2 Vsteps of a HEMT with (a) p-doping (NA = 0.5·1016 cm−3),(b) compensated buffer doping (NA = ND = 1018 cm−3),and (c) Al0.04Ga0.96N back-barrier. . . . . . . . . . . . . . . 42

3.15 Panel (a): Traps around the gate regions (circles) which cancause a “virtual gate” effect when they become negativelycharged. Panel (b): Model of a pulse measurements from aquiescent point Q1= (0, 0) V and Q2, in pinch-off and highVDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.16 Field simulation of the region around the gate for differentbias points, the legend shows the value of log(E), where Eis measured in V/cm. The simulated gate has Lg = 200 nm.Panel (a): (VGS, VDS) = (−6, 8) V. Panel (b): (VGS, VDS) =

(−6, 0) V. Panel (c): (VGS, VDS) = (0, 8) V. . . . . . . . . . . 45

4.1 Small-signal equivalent circuit of a HEMT. . . . . . . . . . 48

4.2 Main contributions to the equivalent circuit elements ofFig. 4.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.3 (a) Schematic of the main geometrical contribution to CGS

and CGD. (b) Comparison of geometrical estimation for thegate capacitance CGS where the contribution from the footwas based on a purely geometrical approximation (solidline) or quantum mechanical calculation (dash-dotted line).The total CGS is obtained by adding the contribution fromthe head (2Ch) calculated geometrically (dotted line). . . . 51

4.4 I-V characteristics of AlGaN-on-silicon HEMTs on with (a)LG = 75 nm and LSD = 2 µm, and (b) LG = 100 nm andLSD = 1 µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

144 List of Figures





(−6, 0) V. Panel (c): (VGS, VDS) = (0, 8) V. . . . . . . . . . . 45






144 List of Figures





(−6, 0) V. Panel (c): (VGS, VDS) = (0, 8) V. . . . . . . . . . . 45






145

4.5 Small-signal measurement and cutoff frequency extractionof HEMTs with LG = 75 nm, LSD = 2 µm and LG = 100 nm,LSD = 1 µm, for panels (a,c) and (b,d), respectively. Panel(c) and (d) show data at higher VDS bias, corresponding tothe peak fMAX. . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.6 Equivalent circuit elements extracted at different bias points.VGS was normalized to the threshold voltage VTH = −3.3and −3.5 V, for the device with LG = 75(a-d) and 100 nm(e-h), respectively. . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.7 (a) Cross-sectional scanning electron micrographs of aLG = 75 nm non-recessed device (top) and a recessedone (bottom). The recess width was 200 nm. Comparisonof (b)gm and (b)ID for devices with identical geometries(LSD = 2 µm). . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.8 I-V Characteristics for VGS = 0 to −3 V in 1 V steps (a).Small-signal extraction for two different bias points, corre-sponding to the highest fT (b) and fMAX (c), respectively.The device had LG = 75 nm, LH = 400 nm, LSD = 2 µm,W = 100 µm d = 12 nm (8 nm recess). . . . . . . . . . . . . 59

4.9 fMAX extracted from U at different bias for HEMTs: (a)non-recessed LG = 100 nm, (b) recessed (depth: 8 nm)LG = 75 nm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.10 A subset of small-signal equivalent circuit elements of arecessed AlGaN/GaN HEMT, extracted at different biaspoints. VGS was normalized to the threshold voltage VTH =

−2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.11 (a) I-V characteristics of a HEMT fabricated on Layer Awith: LG = 30 nm, LH = 400 nm, LSD = 1 µm, W = 100 µm.(b) Transconductance and ID vs. VGS plot. (c) FIB cross-section micrograph of the active region. . . . . . . . . . . . 63

146 List of Figures

4.12 (a) Pulsed I-V characteristics for the same device of Fig. 4.11,where VGS = 0, 3 and −6 V, respectively, with a quiescentpoint of (VGS, VDS) = (0, 0) V (solid line) and (−8, 8) V(dashed line), respectively. (b) Relative dispersion calcu-lated as a percentage of ID lost between the same twoquiescent points. . . . . . . . . . . . . . . . . . . . . . . . . 64

4.13 Small-signal RF characterization and cutoff frequency ex-traction for a HEMT fabricated on Layer A, with LG =

30 nm, LH = 400 nm, LSD = 1 µm, W = 100 µm. Thetwo measurements were performed at the (VDS, VGS) biasyielding the highest fT. . . . . . . . . . . . . . . . . . . . . . 65

4.14 Transconductance (a) and drain current (b) vs. VGS mea-sured at VDS = 6 V for HEMTs with LG = 75 nm fabricatedon Layers A (green), B (blue) and C (red). . . . . . . . . . . 68

4.15 Extrinsic cutoff frequency calculated using Eq. 4.1. Forboth plots, the following values have been used: nS =

1.7·1013 cm−2 (at d = 6 nm), CGD = 14 fF, µ = 1500 cm2/V·s,LSD = 1 µm, W = 100 µm, vsat = 1.9·107 cm/s, gm,int =

ε·vsat/d. Gate lengths were LG = 35 nm and LG = 75 nmfor (a) and (b), respectively. A contact and gate resistanceof 0.35 Ω/mm and 3.5 Ω, respectively, were assumed. . . 69

4.16 Small-signal RF measurements and extraction for HEMTsfabricated on Layers B and C with LG = 75 nm, LH =

400 nm, W = 100 µm, LSD = 1 µm. . . . . . . . . . . . . . . 70

4.17 Compared dispersion of HEMTs fabricated on Layers Band C having LG = 200 nm, LH = 600 nm, W = 100 µm,LSD = 4 µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

146 List of Figures









400 nm, W = 100 µm, LSD = 1 µm. . . . . . . . . . . . . . . 70


146 List of Figures









400 nm, W = 100 µm, LSD = 1 µm. . . . . . . . . . . . . . . 70


147

4.18 Simulation of ion implant, showing the following ion-induced damages: N-vacancies, Ga-vacacies, which sumup to the target vacancies, and target displacements whichinclude also replacement collisions. (a) shows the effect ofa H+ ion beam with energy of 50 kV on layer C, while(b) shows the effect of two 50 kV and 100 kV subsequentimplants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.19 Scheme of H+ ion implant experiment, performed afterprocessing. The shaded areas represent ion-induced dam-age, either by replacement collisions or vacancies creation. 73

4.20 Effect of different ion implant doses and energies in HEMTswith LG = 100 nm LSD = 2 µm, W = 100 µm, on ID (a)and on gm (b), respectively. . . . . . . . . . . . . . . . . . . 74

4.21 DC characteristics before (dashed lines) and after post-process ion implant (solid lines) of 5·1012 cm−2 H+ ions.The device fabricated on Layer C had LG = 75 nm LSD =

1 µm, W = 150 µm. (a) ID vs. VDS characteristics, whereVGS is varied from 0 to -5 V in steps of 1 V. (b) ID vs. VGS

and (b) gm at VDS = 6 V. . . . . . . . . . . . . . . . . . . . . 75

4.22 DC (solid lines) and pulsed I-V characteristics for of aHEMT fabricated on Layer B, with LG = 200 nm LSD =

4 µm, W = 150 µm. Where VGS = 2, 0 and −2 V, re-spectively, with a quiescent point of (VDS, VGS) = (0, 0) V(dotted line) and (−4.5, 10) V (dashed line), respectively.The DC curves are also shown (solid line). . . . . . . . . . 77

4.23 (a) Comparison of drain current ID of a HEMTs fabricatedon Layer C (LG = 75 nm LSD = 1 µm, W = 150 µm) withan ion implant dose of 5·1012 cm−2 H+ ions (blue) andand identical one fabricated on the back-barrier Layer D(red). For the HEMT fabricated on Layer D (b) shows gm

(solid line) and ID (dashed line), measured at VDS =1, 4and 7 V (color coded) and (c) shows the small-signal RFmeasurements at (VGS, VDS) = (−2.5, 6) V. . . . . . . . . . 79

148 List of Figures

4.24 (a) ID of devices with different recess depths, of HEMTs(LG = 75 nm LSD = 1 µm, W = 150 µm). (c) gm for thesame devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.25 I-V characteristics of HEMTs fabricated on Layer B withLG = 200 nm LSD = 4 µm, W = 100 µm and (a) regrown or(b) annealed ohmics, respectively. The dashed lines showthe ON-resistance. . . . . . . . . . . . . . . . . . . . . . . . 82

4.26 Pulsed I-V characteristics of a HEMTs with LG = 200 nm,LSD = 4 µm, W = 100 µm and (a) regrown or (b) annealedohmics. The quiescent point was (VGS, VDS) = (0, 0) and(−4, 15) V, for the dotted and dashed lines, respectively. . 83

4.27 (a) Time dependence of ID, normalized to its t = 0 value,for HEMTs with LSD = 4 µm, W = 100 µm LG = 75 nm(regrown) LG = 50 nm (annealed), measured after applyingVDS = 5 V, at the same ID(t = 0) ≈ 70 mA, achievedwith VGS = −0.5 and −1.1 V in the regrown and annealedcontacts device, respectively. (b) Transconductance at VGS =

1 and 10 V for HEMTs (LG = 200 nm LSD = 4 µm, W =

100 µm) fabricated on Layer B with regrown and annealedcontacts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.28 Small-signal measurements of HEMTs with regrown ohmics(a, c, e) or annealed (b, d, f), fabricated on Layer B withLG = 50 nm and different W and LSD (see inset). . . . . . . 86

4.29 Small-signal measurements of a HEMT with regrown ohmicswith LG = 50 nm LSD = 1 µm, W = 50 µm. The fMAX wasthe highest measured on any AlInN-based HEMT fabri-cated in this work. . . . . . . . . . . . . . . . . . . . . . . . 87

4.30 Schematic representation of the conductive paths (dashedlines) which carry current to the drain contact (ID,OFF),when the gate is biased below pinch-off (VGS < VTH), andthe drain is positively biased VDS > 0 V. I′buffer denotes theshare of current reaching the gate contact pad (not shown)through dislocations. . . . . . . . . . . . . . . . . . . . . . . 88

148 List of Figures










148 List of Figures










149

4.31 (a) Reverse-bias gate current of HEMTs fabricated on LayerA with LG = 75 nm (solid lines) and Open test structures(dashed lines). The inter-device isolation was performedby either mesa (thick lines) or (P+, H+, He+) ion implantisolation (thin lines). (b) Reverse-bias gate current (at VDS =

0 V) in HEMTs with LG = 75 nm fabricated on Layers Band C (blue and red lines, respectively), before and afterimplementing insulated contact pads. . . . . . . . . . . . . 89

4.32 (a) Drain current (ID) of a HEMT (LG = 75 nm LSD = 2 µm,W = 100 µm) before and after implementation of insulatedcontact pads. (b) Reverse-bias gate current (IG) for HEMTswith LG = 200 nm fabricated on different layers. . . . . . . 91

4.33 Reverse and forward gate current in linear scale for HEMTsfabricated on Layer C, with the following W = 75 µm,LSD = 4 µm, and different gate lengths. The inset shows amagnification of the plot between VGS = −9 and −3 V. . . 92

4.34 Reverse gate leakage for different gate lengths normalizedto the Schottky contact area, measured on HEMTs fabri-cated on Layer C. . . . . . . . . . . . . . . . . . . . . . . . . 93

4.35 Plots of (a) log(IG/VGS) vs. V1/2GS and (b) log(IG) vs. (1 −

VGS)−1. The values on the x-axis labels are those of VGS, the

values of sqrtVGS and (1 − VGS)−1 are not shown. A linear

behavior of the plots in the shown range may considered tobe signature of (a) Frenkel-Poole or (b) Fowler Nordheim,respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.36 (a) Simulated Frenkel-Poole leakage characteristics as afunction of temperature (solid curves), compared to aHEMT with LG = 10 µm fabricated on Layer B (dot-ted curve). For calculating the current, ε = 5.3[56] andφFP = 1.1 eV were used in Eq. 3.6. (b) Measurements ofHEMT with LG = 10 µm and 35 nm fabricated on Layer Bas a function of temperature. . . . . . . . . . . . . . . . . . 96

150 List of Figures

5.1 Schematic of the measurement setup used for load-pullmeasurement. Panel (a): Generic setup showing input stage,directional couplers and variable impedance load. The vari-able impedance load was implemented with: (b) Mechani-cal multi-harmonic tuners by Focus Microwave, Inc (10-40GHz) or (c) Active closed-loop (94 GHz). . . . . . . . . . . 100

5.2 Load-pull map at f0 = 94 GHz for a GaN HEMTs. The POUT

levels are traced for 1 dB of gain compression. Adaptedfrom [100]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.3 Loadlines for operation Class A (dashed line) and B (dottedline), superimposed to ideal I-V characteristics of a transis-tor. Ibias,A and Ibias,B represent the drain current with theRF input signal turned off for Class A and B, respectively.When the RF signal is turned on, the DC-current measuredat the drain is equal to IDC,A and IDC,B for Class A and B,respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.4 (a) Time-domain waveform of the drain current in ClassA, AB and B, respectively. The ID(t) curve (solid line) in-cluding all harmonics is plotted versus θ = 2π f0t. Thedotted line represents fundamental frequency ( f0) compo-nent, which in Class A coincides with ID(θ). The plots alsoshow the ID value when the RF signal is off (Ibias, dash-dotted line) and the self-bias component with RF signal on(Iself), which added together produce the average value ofID(θ), called IDC (dashed line). (b) Self-bias current (Ibias)(dash-dotted line) and increase of POUT with respect to thePSAT of Class A, as a function of the clipping angle α whichdetermines the operation class. . . . . . . . . . . . . . . . . 104

150 List of Figures






150 List of Figures






151

5.5 Loadlines for different PIN values (see legend) for drain(a) and gate (b) measured at f0 = 10 GHz, plus the higherharmonics f1,2,3 = 20, 30, 40 GHz. The figure shows theloadlines both embedded (dotted lines) and de-embedded(solid lines) from the pad parasitics. The load ΓL = 0.812 <

23.4 was selected to maximize PSAT. The correspondingpower sweep is shown in Fig. 5.6. The arrows (dotted grey)indicate the clockwise (CW) and counterclockwise (CCW)rotation along the gate loadline. . . . . . . . . . . . . . . . 107

5.6 Large-signal measurements at 10 GHz for HEMTs havingLSD = 4 µm and LG = 200 nm fabricated on Layers C (a)and B (b) epilayers ΓL was 0.812 < 23.4 and 0.71 < 17.1

and the bias conditions were (VGS, VDS) = (−3.9, 40) and(−4.2, 45) V, respectively. The loadlines corresponding tothe black dots in (a) are shown in Fig. 5.5. . . . . . . . . . . 109

5.7 (a) DC (solid line) and pulsed I-V characteristics of a200 nm gate length device with LSD = 0.5 µm, whereVGS is varied from 0 to −3 V in steps of 1 V. Dotted line:pulsed from (VGS, VDS) = (0, 0) V; dashed line: pulsed from(VGS, VDS) = (−4, 8) V. Pulse width= 500 ns, period=10 µs. (b) DC (solid line) and pulsed I-V characteristicsof a 200 nm gate length device with LSD = 4 µm VGS

is varied from 1 to −4 V in steps of 1 V. Dotted line:pulsed from (VGS, VDS) = (0, 0) V; dashed line: pulsed from(VGS, VDS) = (−5, 10) V. Pulse width= 500 ns, period=10 µs. Inset: reverse-bias gate leakage current (at VDS = 0)and drain current (at VDS = 8) versus gate voltage, forthe same gate length and for LSD = 4 µm (solid line) andLSD = 0.5 µm (dash-dotted line). . . . . . . . . . . . . . . . 112

152 List of Figures

5.8 POUT (solid line), GP (dotted line), and PAE (dashed line)characteristics at 40 GHz versus PIN for Class B biased2 × (0.1 × 50) µm HEMTs, having different source-drainspacings (color coded, see legend). VGS was chosen toachieve Class AB amplifier operation, VDS was (15, 25, 20)V, for LSD = (0.5, 2, 4) µm, respectively. . . . . . . . . . . . 113

5.9 Large-signal measurements at 40 GHz for a GaN-cappedHEMTs (Layer B) with LG = 200 nm and LSD = 4 µm,biased at (VGS, VDS) = (−2.6, 35) V, with ΓL = 0.681 <

45.6, optimized for maximum POUT. . . . . . . . . . . . . 115

5.10 Large-signal measurements at 94 GHz for a GaN-cappedHEMTs (Layer B) with LG = 100 nm, LSD = 1 µm, W =

2 × 25 µm biased at different bias points. . . . . . . . . . . 116



5.12 Summary of large-signal RF performance. The data aretaken from Refs. [105] (VDS=30 V) (a), [110] (VDS=15 V)(b), [14] (VDS=30 V) (c), [15, 16, 17] (VDS=14 V) (d), [109](VDS=30 V) (e), and [107] (VDS=20 V) (f) . . . . . . . . . . . 119

152 List of Figures









152 List of Figures









153

List of Tables

1.1 Fundamental parameters of the most widely used semi-conductors: bandgap (EG), electron mobility (µ), saturationvelocity (vsat), breakdown field (Ebr), thermal conductivity(κ) and static relative dielectric constant (εr). . . . . . . . . 6

3.1 Electron affinity and work function of some nitride semi-conductors and metals. χS of compounds were calculatedfrom [48] using Vegard’s law. . . . . . . . . . . . . . . . . . 31

4.1 Heterostructure of Layer A, from top to bottom. The struc-ture displayed as-grown nS = 2.3 · 1013 cm−2 and µ =

1430 cm2/V·s from Hall measurements. The layers weregrown on semi-insulating SiC. . . . . . . . . . . . . . . . . 62

4.2 Heterostructure Layers B and C, from top to bottom. Thelayers displayed as-grown nS = 1.6·1013 cm−3 and µ =

1470 cm2/V·s (Layer B) and nS = 2·1013 cm−3 and µ =

1320 cm2/V·s (Layer C) from Hall measurments. Both lay-ers were grown on semi-insulating SiC substrates. . . . . . 67

154 List of Tables

4.3 Equivalent circuit elements of a device fabricated on LayerC, with LG = 75 nm LSD = 1 µm, W = 150 µm. fT (ext) andfMAX,U (ext) represent the extrinsic, de-embedded valuesextracted at (VGS, VDS) = (−2.5, 5) V. The implant dose ofH+ ions was 5·1012 cm−2. . . . . . . . . . . . . . . . . . . . 76

4.4 Layer D, from top to bottom. The layer displayed as-grownnS = 2.75 cm−3 and µ = 880 cm2/V·s from Hall measure-ments, for a total Rsh = 258 Ω/. . . . . . . . . . . . . . . 78

4.5 fT and fMAX of recessed devices fabricated on Layer D. Thetotal barrier thickness before recess was d = 10 nm. . . . . 81

154 List of Tables




154 List of Tables




155

List of Publications During PhD Studies

Journal Papers

[1] V. Teppati, S. Tirelli, R. Lovblom, R. Fluckiger, M. Alexandrova,and C. Bolognesi, “Accuracy of microwave transistor fT and fMAX

extractions,” Electron Devices, IEEE Transactions on, vol. 61, no. 4, pp.984–990, April 2014.

[2] V. Teppati, H. Benedickter, D. Marti, M. Garelli, S. Tirelli, R. Lovblom,R. Fluckiger, M. Alexandrova, O. Ostinelli, and C. Bolognesi, “A W-band on-wafer active load -pull system based on down-conversiontechniques,” Microwave Theory and Techniques, IEEE Transactions on,vol. 62, no. 1, pp. 148–153, Jan 2014.

[3] S. Tirelli, D. Marti, L. Lugani, J.-F. Carlin, N. Grandjean, and C. R.Bolognesi, “AlN-capped AlInN/GaN high electron mobility transis-tors with 4.5 W/mm output power at 40 GHz,” Jpn. J. Appl. Phys.,vol. 52, no. 8, p. 08JN16, 2013.

[4] S. Tirelli, L. Lugani, D. Marti, J.-F. Carlin, N. Grandjean, andC. Bolognesi, “AlInN-based HEMTs for large-signal operation at

156 List of Publications

40 GHz,” Electron Devices, IEEE Transactions on, vol. 60, no. 10, pp.3091–3098, Oct 2013.

[5] D. Marti, S. Tirelli, A. R. Alt, J. Roberts, and C. R. Bolognesi, “150-GHz cutoff frequencies and 2-W/mm output power at 40 GHzin a millimeter-wave AlGaN/GaN HEMT technology on silicon,”Electron Device Letters, IEEE, vol. 33, no. 10, pp. 1372–1374, 2012.



[8] H. Sun, D. Marti, S. Tirelli, A. R. Alt, H. Benedickter, and C. Bolog-nesi, “Millimeter-wave GaN-based HEMT development at ETH-zurich,”, International Journal of Microwave and Wireless Technologies,vol. 1, pp. 1–6, April 2010.


Conference Papers

[1] S. Tirelli, C. Bolognesi, L. Lugani, J. F. Carlin, and N. Grandjean,“AlInN/GaN HEMTs with 5.8 W/mm power output at 40 GHz,”in 37th Workshop on Compound Semiconductor Devices and IntegratedCircuits held in Europe (WOCSDICE 2013), May 2013.

[2] S. Tirelli, D. Marti, L. Lugani, J.-F. Carlin, N. Grandjean, and C. R.Bolognesi, “AlN-capped AlInN/GaN HEMTs with 4.5 W/mm out-








Conference Papers










Conference Papers



157

put power at 40 GHz,” in International Workshop on Nitride Semicon-ductors 2012 (IWN), Sapporo, Japan, October 2012.

[3] S. Tirelli, D. Marti, H. Sun, A. Alt, J. F. Carlin, N. Grandjean,and C. R. Bolognesi, “Fully-passivated AlInN/GaN HEMTs withfT = fMAX > 180 GHz,” in 9th Int. Conf. On Nitride Semiconductors(ICNS2011), Glasgow, UK, July 2011.

[4] H. Sun, D. Marti, S. Tirelli, A. Alt, E. Piner, and C. Bolognesi,“Record bandwidth of AlGaN/GaN HEMTs on silicon substrateswith fT = 130 GHz,” in 9th International Conference on Nitride Semi-conductors (ICNS-9), July 2011.

[5] S. Tirelli, D. Marti, H. Sun, A. R. Alt, C. R. Bolognesi, J.-F. Carlin,M. Py, and N. Grandjean, “180 GHz fully-passivated AlInN/GaNHEMTs,” in 38th Int. Symp. On Compound Semiconductors (ISCS 2011),May 2011.

[6] S. Tirelli, D. Marti, H. Sun, A. R. Alt, H. Benedickter, E. Piner,and C. R. Bolognesi, “170 GHz fMAX recessed-gate AlGaN/GaN-on-silicon HEMT,” in 34th WOCSDICE Darmstadt/Seeheim Germany,May 2010.

[7] H. Sun, S. Tirelli, A. Alt, E. Piner, and C. Bolognesi, “A comparisonof mesa and ion isolation in AlGaN/GaN HEMTs,” in 38th Int.Symp. On Compound Semiconductors (ISCS 2011), May 2011.

[8] C. Bolognesi, H. Sun, S. Tirelli, A. Alt, J.-F. Carlin, E. Feltin, M. Gon-schorek, M. Py, and N. Grandjean, “High-speed AlInN/GaN HEMTson SiC and (111) HR-Silicon,” in International Conference on CompoundSemiconductor Manufacturing Technology (CSMANTECH 2011), May2011.

[9] H. Sun, D. Marti, S. Tirelli, A. Alt, E. Piner, and C. Bolognesi,“Record bandwidth of AlGaN/GaN HEMTs on silicon substrateswith fT = 130 GHz,” in 9th International Conference on Nitride Semi-conductors (ICNS-9), July 2011.


[10] N. Ronchi, M. Meneghini, A. Stocco, G. Meneghesso, E. Zanoni,S. Tirelli, and C. R. Bolognesi, “A study of trapping phenomenaon recessed-gate AlGaN/GaN-on-silicon HEMT,” in 19th EuropeanWorkshop on Heterostructure Technology (HETECH), Fodele, Greece,October 2010.

[11] C. Bolognesi, H. Sun, S. Tirelli, A. Alt, D. Marti, H. Benedickter, J.-F.Carlin, E. Feltin, M. Gonschorek, M. Py, and N. Grandjean, “High-speed AlInN/GaN HEMTs on SiC and (111) HR-Silicon,” in TheInternational Workshop on Nitride semiconductors (IWN2010), Tampa,Florida U.S.A, September 2010.

[12] C. Bolognesi, S. Tirelli, D. Marti, H. Sun, A. Alt, L. Liu, M. Vetter,H. Benedickter, and E. Piner, “Recent developments in high-speedGaN HEMTs on silicon substrates,” in 5th Space Agency - MODRound Table Workshop on GaN Component Technologies ESA-ESTEC,Noordwijk, Netherlands, September 2010.









Curriculum Vitae

Stefano Tirelli

Born July 2, 1979 in Reggio Emilia, Italy

2009 - 2014 PhD studies at the Millimeter-Wave Electronics Labora-tory, Department of Information Technology and Electri-cal Engineering, ETH Zurich, Zürich, Switzerland

2003 - 2008 Master in Physics, University of Pisa, Italy.Thesis: "Modulation of Josephson Current in Out-of-Equilibrium Superconductors"

2002 - 2003 Visiting Student, LIGO Laboratories, California Instituteof Technology, US

1998 - 2003 Bachelor Degree in Physics, University of Pisa, Italy.Thesis: "Stress/Strain Behavior of Molybdenum-Ruthenium-Boron-Based Metallic Amorphous Alloys"

1994 - 1998 High School Diploma, Liceo Scientifico A. Avogadro,Rome, Italy

Documents

In Copyright - Non-Commercial Use Permitted Rights ... · Stefano Tirelli MSc, University of Pisa born on 02.07.1979 citizen of Italy accepted on the recommendation of: Prof. Dr