512 IEEE ELECTRON DEVICE LETTERS, VOL 17, NO 1 I , NOVEMBER 1996

Improved BRT Structures Fabricated Using SIMOX Technology

S. Sridhar and B. J.

Abstract- The SIMBRT is a new power device in which SIMOX technology is used to isolate the P-channel turnoff MOS- FET resulting in improved cathode injection efficiencies and higher maximum controllable current densities when compared to the conventional BRT. In this paper, experimentally measured characteristics on four novel SIMBRT structures fabricated using a 9-mask SIMOX smart power process are presented, and their performance is compared with conventional BRT structures fah- ricated alongside. The lowest on-state voltage drop and highest maximum controllable current density are demonstrated to occur for the structure with the smallest cell pitch.

1. INTRODUCTION

EVERAL applications require vertical power semiconduc- S tor devices to be interfaced with logic and control circuitry [l]. From a cost and reliability point of view, it is preferable to integrate the low voltage elements alongside the vertical power device in a single chip to fabricate smart power discretes. However, it is essential to effectively isolate low-voltage devices from the power device. SIMOX is fast emerging as an attractive technique for achieving this isolation [2]-[4]. The SIMOX smart power discrete device process creates the opportunity to improve the performance of existing power devices by using the implanted buried oxide layer [5]. The SIMBRT is an improved BRT [6] structure, in which the P- channel turnoff MOSFET is isolated from the vertical thyristor by a buried oxide layer in order to achieve superior on-state and turnoff performance. In this paper, experimental results on novel SIMBRT structures with different hole extraction paths are presented for the first time, and their performance i s experimentally compared with that of the conventional BRT.

11. STRUCTURE AND OPERATION OF THE SIMBRT

Schematic cross sections of the SIMBRT are shown in Fig. 1. The SIMBRT is a vertical thyristor structure with a lateral P-channel MOSFET integrated in order to enable gate controlled turnoff. Forward blocking is achieved when a positive bias is applied to the anode with the gate shorted to the cathode. The blocking voltage is determined by the breakdown voltage of the open based p-n-p transistor as is the case for the BRT structure. Turn-on in the SIMBRT is achieved by an IGBT segment located in the dimension perpendicular to the cross section shown in Fig. 1 . When a positive bias is

Manuscript received May 6, 1996; revised July 20, 1996. This work was supported by the Power Semiconductor Research Center, North Carolina State University.

The authors are with the Power Semiconductor Research Center, North Carolina State University, Raleigh, NC 27695-7924 USA.

Publisher Item Identifier S 0741-3 106(96)08309-7.

Baliga, Fellow, IEEE

applied to the anode, with the gate biased above its threshold voltage, the device operates like an IGBT at low anode current densities. When the hole current collected in the P-base region of the thyristor segment is sufficiently large so as to forward bias the N+/P-base junction ( J l ) , the thyristor latches “on” and the SIMBRT operates like a thyristor. MOS-gate controlled turnoff in the SIMBRT is achieved by the application of a negative bias to the gate. This results in the formation of a hole inversion channel in the turnoff MOSFET. Holes are then shunted from the P-base region of the thyristor by the P-channel MOSFET. The shunting of holes from the base region of the thyristor results in interrupting the regenerative thyristor action and the thyristor turns off, as discussed in detail for the conventional BRT [7].

In the conventional BRT, there are two components to the cathode current during the on-state; the first is collected in the N+ cathode of the thyristor segment, and the second is collected by the P+ diverter region. The presence of the current component collected in the P+ diverter region results in a reduction in the injection efficiency of the cathode [8]. In the SIMBRT, the diverter is isolated from the drift region by the buried oxide layer. So, current flow into the diverter directly from the N-drift region is prevented, and the entire on-state current is collected in the N+ cathode. This results in an improved cathode injection efficiency in the SIMBRT when compared to the BRT which reduces the on-state voltage drop.

During the turnoff process in a conventional BRT, holes are not only extracted from the P-base region via the inversion channel, but are also collected directly in the channel region from the drift region. This increases the voltage drop along the hole current shunting path which reduces the maximum controllable current density in the conventional BRT. In a SIMBRT, the presence of the buried oxide layer ensures that the hole current flowing in P-MOSFET is exclusively due to holes extracted from the P-base region of the thyristor. Hence, the SIMBRT can be expected to have a higher maximum con- trollable current density when compared to the conventional BRT for the same base width.

111. SIMBRT STRUCTURES

It has been shown in the conventional BRT [6], [7] that in order to increase the maximum controllable current density, it is necessary to reduce the width of the P-base region in the thyristor segment and to increase the P-MOSFET channel density. This implies that the cell pitch must be reduced to a minimum. Two-dimensional numerical simulations indicate that the same conclusions hold true for the SIMBRT structure.

0741-3106/96$05.00 0 1996 IEEE

SRIDHAR AND BALIGA: IMPROVED BRT STRUCTURES FABRICATED USING SlMOX TECHNOLOGY

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In order to achieve this goal, novel SIMBRT structures, with different hole extraction paths were proposed and fabricated. The minimum feature size used during design was 3 pm with an alignment tolerance of 2 pm. A multiple floating field ring and field plate combination designed to support 700 V was used to terminate all the devices. The SIMBRT structures proposed and fabricated in this work were as follows.

Structure (a): A linear cell design shown in Fig. l(a) where lateral isolation was achieved by LOCOS oxidation and a metal strap was used to establish connectivity between the P-base region of the thyristor and the source of the P-channel MOSFET. This structure had a cell pitch of 28.5 pm.

Structure (b): A linear cell design shown in Fig. 1 (b) where the lateral LOCOS isolation was absent, allowing a reduction in cell pitch. In this case, the implanted oxide layer was expected to reach the surface of the wafer providing lateral isolation if a tapered masking oxide is used during the SIMOX oxygen implantation. In this structure, a metal strap must be included in order to establish connectivity between the P-base region and source of the P-channel MOSFET, a5 shown in Fig. l(b). This structure had a cell pitch of 24.5 pm.

Structure (c): A linear cell design shown in Fig. I(c) where the lateral LOCOS isolation or metal strap were not used, allowing a further reduction in cell pitch. In this structure, electrical connectivity between the P-base region and the P-channel MOSFET is provided directly through the silicon P+ regions. This structure had a cell pitch of 20.5 pm.

Structure (d): A circular cell design identical to structure (a) and rotated about the axis AA' of Fig. 1.

r - - - - - - - - - - - l ~ - - - - - - - - - - - i

1 - - -/- - - - - - - - I I I I

ET ' - 1

A Fig. 1 . Schematic cross section of SIMBRT structures. Structure (a), struc- ture (b), and structure (c) have a linear cell topology. Structure (d) is obtained by rotating structure (a) about the axis A.4'.

'TABLE I SUMMARY OF MEASURED PARAMETERS IN THE DIFFERENT SIMBRT

STRUCTURES COMPARED WITH THE CONVENTIONAL BRT

Jmcc (A cmP) Devlce (JtlOO A cm-')

0.87 V BRT

28.5 urn 0.83 V 490

24.5 um 0.80 v 530

Structure c I Linear Cell I 20.5 urn I 0.78 V I 0

Structured I Circular Cell I 28.5um I 0.85V I 425

IV. EXPERIMENTAL RESULTS

A 9-mask SIMOX smart power process was used to fab- ricate the four SIMBRT structures together with the conven- tional BRT structure for comparison. The starting material was a 50 pm, 1 x ~ m - ~ , N-type epitaxial material separated from a P+ substrate by a 15 pm, 1 x 10l6 cni-', N-buffer layer chosen for 700 V operation. The fabricated devices had a gate oxide thickness of 500 A, buried oxide layer thickness of 3500 A, and a silicon-on-insulator thickness of 2000 A. The localized buried oxide was obtained by means of a high-dose, high-energy oxygen implant and using a 1 .5 pm thick masking field oxide [9]. The junction depths of the P-base, and N+ cathode region were 3 pm and 1 pm, respectively, and their surface concentrations were 5 x 1017 cmP3 and 1 x 10'" cmp3, respectively. The threshold voltage of the N-channel turn-on MOSFET (IGBT section) was found to be 2.2 V and that of the P-channel turnoff MOSFET on the SIMOX layer was found to be -3 V. The P-channel MOSFET had a channel length of 1.2 pm.

In the fabricated SIMBRT devices, cross sectional SEM photographs showed that the implanted buried oxide reached the surface at the edge of the isolation layer indicating that the masking oxide layer during SIMOX oxygen implantation had a tapered sidewall. This results in the P-channel MOSFET being completely isolated from the thyristor in all the designs. This indicates that the LOCOS region is not required. However, it is essential to have a metal strap to provide a path between

the P-base region and the source of the P-channel MOSFET to extract holes during the turnoff process. Consequently it was found that thyristor turnoff could not be achieved in structure (c).

The on-state voltage drop for these devices was character- ized at a current density of 100 A/cm2 at a gate bias of 15 V. The forward voltage drops for the four SIMBRT structures and the conventional BRT are summarized in Table I. The on-state voltage drop of an IGBT fabricated alongside these devices was found to be 1.2 V. The maximum controllable current densities for these structures, measured under 100 V resistive load conditions with the gate voltage ramped from +15 V to -1.5 V, are also given in Table I. The improved performance in all the SIMBRT structures in relation to the conventional BRT is due to the isolation of the P+ diverter and the P-channel MOSFET by the buried oxide layer. The superior performance of structure (b), when compared to other SIMBRT structures, is because it has the smallest cell pitch among the SIMBRT structures. The areas of the fabricated devices were about 4.6 x cm'.

V. SUMMARY

In this paper, novel BRT structures fabricated using SIMOX technology are reported. Both SIMBRT and conventional BRT structures were fabricated using a 9-mask SIMOX smart power process. The SIMBRT structures were experimentally

5 14 IEEE ELECTRON DEVICE LETTERS, VOL. 17, NO. 11, NOVEMBER 1996

demonstrated to have a lower on-state voltage drop and a higher maximum controllable current density when compared to the conventional BRT. It was found that, although a LOCOS region was not required, a metal strap is necessary in all structures in order to establish electrical connectivity between the P-base region of the thyristor and the source of the P-channel MOSFET, because the buried oxide layer reaches the surface at the edge of the masking window. It has been shown that the SIMBRT structure with a minimum cell pitch exhibits the best performance.

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