IEEE TRANSACTIONS ON MAGNETICS, VOL. 41, NO. 10, OCTOBER 2005 2995

Imposing a k Constraint in Recording SystemsEmploying Post-Viterbi Error Correction

Jihoon Park, Student Member, IEEE, and Jaekyun Moon, Fellow, IEEE

Department of Electrical and Computer Engineering, Minneapolis, MN 55455 USA

A strategy for imposing a constraint without any rate penalty is proposed for recording systems that already employ a post-Viterbierror-correction processor. Although the method is general, we focus on the application to perpendicular magnetic recording. Thisscheme is based on deliberate insertion of a short pattern, which contains one or more transitions and can be detected by an innererror-detection code, in the prolonged absence of magnetic transitions in the data bit pattern. The post-Viterbi processor attempts anerror event correction by examining the likelihoods of a list of error events including the one due to the inserted pattern that forces the

constraint. The signal-to-noise ratio loss compared to the ideal system with = but perfect timing recovery is negligible at eithera fixed bit-error rate or a fixed sector-error rate.

Index Terms—Cyclic redundancy check code, constraint, perpendicular magnetic recording, post-Viterbi processor.

I. INTRODUCTION

RUN-LENGTH limited (RLL) codes used in today’srecording products limit runs of same nonreturn-to-zero

(NRZ) bits to intervals at a time. While this “ constraint”facilitates timing recovery and is essential, at issue is the ratepenalty associated with its application, which is costly in termsof loss of effective signal-to-noise ratio (SNR) and user density.To avoid this rate penalty, Vasic and Pedagani have proposeda bit-flipping scheme in [1], wherein bit errors are deliberatelyinserted whenever data contains a long string of same symbols,in lieu of conventional RLL coding. Attempts are then made tocorrect the forced errors relying on the outer error correctioncode (ECC). Although this method incurs no rate penalty, theerror correction capability of the ECC is compromised, due tothe additional burden of handling the deliberate bit errors.

In this paper, we propose an effective way to remedy thisproblem. Namely, we make use of the inner error detection codethat is already available in most post-Viterbi error-correctionsystems. The result is that the rate penalty of the constraint iscompletely eliminated while there is no visible loss of ECC per-formance at a given sector-error rate (SER) target. Also, sincewe utilize the existing inner error detection code, there is verylittle extra cost required to implement this scheme. To demon-strate the viability of the proposed approach, we apply the ideato perpendicular recording using an error detection code specif-ically designed for perpendicular recording.

II. CONSTRAINT STRATEGY COMBINED WITH POST-VITERBI

ERROR CORRECTION

The performance of a partial response maximum likelihood(PRML) system can be improved by employing a post-Viterbiprocessor that corrects dominant error events, which are de-tected by an error detection code, at the output of the detector[2]–[6]. The idea is that once the error is detected, then itcan be corrected with a good probability by correlating the

Digital Object Identifier 10.1109/TMAG.2005.854448

estimated error signal with each of the dominant error patternsand identifying the most likely error pattern and its positionwithin the codeword. The estimated error signal is constructedby taking the difference between the actual equalizer output andthe Viterbi detector output stream convolved with the equalizertarget response [3].

Dominant error events in perpendicular recording can be iden-tified from effective minimum distance analysis and/or computersimulation [2], [7], [8]. Major error events that we identifiedwith a specific combination of real perpendicular magneticrecording (PMR) head and disk include: 2 2 2 2 2

2 2 2 2 2 2 2 2 2 , and 2 2, 0, 2, 2 . Acyclic redundancy check (CRC) code has already been used todetect dominant errors in conjunction with a post-Viterbi pro-cessor for longitudinal recording [6], but this code cannot detectmost of the major error patterns observed in PMR environments.A new class of parity check codes and new CRC polynomialshave been identified in [2] and [8], respectively, that are gearedto these error events over a wide range of recording densitiesand different noise environments. For the presentation and per-formance evaluation of the proposed scheme, we will employ aCRC code for error detection purposes.

A block diagram of a CRC-based post-Viterbi processorcombined with the proposed -constraint scheme is depictedin Fig. 1. A pattern is inserted into the middle of long stringsof zeros [in the case of nonreturn-to-zero inverted (NRZI)] orstrings of like bits, in the case of NRZ, after CRC encodingis done to force a given constraint. The inserted patternneeds be detected by the CRC code, and any detectable patternthat contains one or more transitions can be chosen for thispurpose. The CRC decoder will be able to detect either theinserted pattern or any of the dominant error events within eachCRC codeword. As an illustrative example, for , a CRCencoded NRZ sequence, “ 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 ”violates the constraint because there are ten consecutive zerobits. In the proposed method, a pattern is inserted in the middleof these consecutive zero bits. In the present paper, we consider

as a generator polynomial of a CRC codeand choose 203 as the codeword length, balancing betweencode rate loss and error correction capability in a codeword [8].

0018-9464/$20.00 © 2005 IEEE

2996 IEEE TRANSACTIONS ON MAGNETICS, VOL. 41, NO. 10, OCTOBER 2005

Fig. 1. k-constraint strategy.

With this (203, 200) CRC error detection code, we choose “11” as the inserted pattern since it can be detected by the CRCcheck. Thus, the resulting sequence becomes “ 1 1 0 0 0 0 11 0 0 0 0 1 0 1 0 0 ,” which satisfies the constraint .

The error correlation filter bank includes a correlator matchedto the insertion pattern in addition to those matched to a list ofselect dominant error events. While it is easy to choose an inser-tion pattern that the CRC check can detect, it is not immediatelyclear how the error signal can be constructed that can drive thematching correlator to successfully indicate the presence of sucha pattern. We achieve this objective by first removing any inser-tion pattern whenever it appears at the Viterbi detector outputby using the pattern desertion block as seen in Fig. 1. Then,the error signal between the equalizer output and the signal thatresults from a convolution of the pattern-deserted detection bitstream and the target response is generated. In this way, whenthe error flag is raised due to the presence of a forced pattern, thecorrelator matched to this pattern will produce a high output.

Occasionally, local patterns in a correct bit stream will matchthe insertion pattern and will thus be erroneously removed by thepattern desertion block. However, if there are no other errors inthe codeword, this poses no problem because the error flag willnot be raised as the CRC check examines the Viterbi detectoroutput rather than the pattern-deserted bit stream. Like existingpost-Viterbi error correction systems, the proposed scheme isnot capable of handling more than one error event within a code-word. Our scheme will also fail to correct the received codewordin the presence of just one error event, if the insertion pattern hasbeen forced within the codeword; the scheme can only correcteither the error event or the inserted pattern.

A more interesting question is what happens if there is an errorevent that can normally be corrected, but there also exist one ormore erroneous desertions within the codeword. In this case, boththe correlator matched to the insertion pattern and that matchedto one of the error will generate a high signal. In our setup, weassume it is the dominant error event, not the forced pattern, thatraised the error flag if both types of correlators produce high out-puts. This strategy makes sense since, in this way, we can at leasthandle the case where there are both an error event and erroneousdesertions within the codeword. If the insertion pattern has beenforced and the detected codeword also contains a dominant errorevent, then the error correction scheme can only correct eitherthe error event or the inserted pattern.

III. PERFORMANCE EVALUATION

The bit-error rates (BERs) of the proposed scheme are simu-lated and compared to user densities 1.4 and 2.0 in Figs. 2 and3, respectively, for various constraints ( , and ).Channel density is given by , where is the

Fig. 2. BER versus SNR at user density D = 1:4.

Fig. 3. BER versus SNR at user density D = 2:0.

width of the transition response at 50% to 50% of the full satu-ration level, and user density is with being the rateof the CRC code. A hyperbolic tangent transition response is as-sumed, with equalizer target responses ofat [9] and at [2].The SNR has been defined as the energy of the first derivativeof the transition response to the noise spectral density. Thenoise parameter in the SNR definition signifies a mixture of50% additive white Gaussian noise (AWGN) and 50 jitter noise.As a reference, the BERs of the system without any coding,post-Viterbi processing, or constraint (i.e., ) but withideal timing are also shown. It is seen that when is about 14,the error floor due to the inserted patterns is substantially sup-pressed at .

Under the assumption of an outer -error correcting Reed–Solomon (RS) code, the SERs are also computed, based onthe multinomial distribution for the probabilities of the burstsymbol errors with different lengths [2], [4], [6]. For each length

symbol error, where , let and be the numberand the probability of occurrence, respectively. The probability

PARK AND MOON: IMPOSING CONSTRAINT IN RECORDING SYSTEMS EMPLOYING POST-VITERBI ERROR CORRECTION 2997

Fig. 4. SERs of the CRC-based post-Viterbi processor and Vasic’s scheme for(430, 410, 10) RS code (D = 1:3349).

Fig. 5. SERs of the CRC-based post-Viterbi processor and Vasic’s scheme for(430, 410, 10) RS code (D = 1:9070).

density function based on the multinomial distribution is thendescribed by [4]

(1)

Here, and denote the number and the probability ofno erroneous symbols in a sector, and accordinglyand . The probabilities are obtained from thecaptured symbol error statistics with length .

To compute the SER for 512 information-byte sectors, ashortened RS code based on 2 is used [5]. The overalluser density taking into account the outer RS code isdefined as , where is the rate of the outerRS code. Since an shortened RS code does not requirean interleaving, the probability of an uncorrectable sector, theSER, is simply given by

(2)

where the sum is over all combinations of such that.

It is seen from the SER comparison for the CRC-based post-Viterbi processor ( and ) and Vasic’s bit-flippingscheme in Figs. 4 and 5 that there is virtually nocompromise in the error correction capability for imposing

using the proposed approach, while the ECC capability issignificantly compromised with Vasic’s scheme. The SNR gainsat are seen to be 0.93 and 0.57 dB in Figs. 4 and5, respectively.

IV. CONCLUSION

An efficient strategy of imposing a constraint which canbe incorporated into an existing post-Viterbi error correctionsystem has been proposed. The scheme requires very little extraimplementation cost and incurs no rate penalty. When appliedto perpendicular recording utilizing a CRC error detection code,the performance gain of the proposed system compared to theuncoded system is considerable at the same BER, and no addi-tional outer ECC capability is required to achieve a reasonable

constraint.

ACKNOWLEDGMENT

This work was supported by the Samsung Advanced Instituteof Technology.

REFERENCES

[1] B. Vasic and K. Pedagani, “A runlength limited low-density parity-checkcoding scheme,” in Proc. ICC 2003, vol. 5, May 2003, pp. 3115–3119.

[2] J. Moon and J. Park, Detection of prescribed error events: Applicationto perpendicular recording, in Proc. IEEE ICC, May 2005.

[3] T. Conway, “A new target response with parity coding for high densitymagnetic recording channels,” IEEE Trans. Magn., vol. 34, no. 4, pp.2382–2386, Jul. 1998.

[4] R. D. Cideciyan, J. D. Coker, E. Eleftheriou, and R. L. Galbraith, “Noisepredictive maximum likelihood detection combined with parity-basedpost-processing,” IEEE Trans. Magn., vol. 37, no. 2, pp. 714–720, Mar.2001.

[5] Z. A. Keirn, V. Y. Krachkovsky, E. F. Haratsch, and H. Burger, “Useof redundant bits for magnetic recording: Single-parity codes and reed-solomon error-correcting code,” IEEE Trans. Magn., vol. 40, no. 1, pp.225–230, Jan. 2004.

[6] W. Feng, A. Vityaev, G. Burd, and N. Nazari, “On the performanceof parity codes in magnetic recording systems,” in Proc. IEEEGLOBECOM, 2000, pp. 1877–1881.

[7] P. Kovintavewat, I. Ozgunes, E. Kurtas, J. R. Barry, and S. W.McLaughlin, “Generalized partial-response targets for perpendicularrecording with jitter noise,” IEEE Trans. Magn., vol. 38, no. 5, pp.2340–2342, Sep. 2002.

[8] J. Moon, J. Park, and J. Lee, “CRC-based high-rate error-detection codefor perpendicular recording,” IEEE Trans. Magn., submitted for publi-cation.

[9] M. Madden, M. Öberg, Z. Wu, and R. He, “Read channel for perpen-dicular magnetic recording,” IEEE Trans. Magn., vol. 40, no. 1, pp.241–246, Jan. 2004.

Manuscript revised April 12, 2005.