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SiGe/SiGeC Design FlowSilvaco provides a complete, well integrated simulation software for all aspects of SiGe/SiGeC technology. Our SiGe/SiGeC software includes technology simulation, SPICE model extraction, interconnect parasitic analysis, SPICE circuit simulation, and traditional CAD. The TCAD Driven CAD approach provides the most accurate models to both device engineers and circuit designers.
ATLAS
CELEBRITY UTMOSTSmartSpice
QUEST
ATHENA
Gateway
Fab or Test LabMeasured Data
ATHENA/SSuprem4 enables the process design engineer to model accurately the full SiGe/SiGeC process flow with an arsenal of sophisticated and experimentally verified tools:
• Monte-Carloimplantationwithcalculationofinterstitialandvacancy damage profiles for TED diffusion effects
• Retardationofborondiffusivityingermaniumandcarbon containing films
• Effectsofcarbononinterstitialdiffusivityandrecombinationbehavior
• Interstitialinjectionduringepitaxialprocessesresultinginenhanced dopant diffusion
• Fullycoupleddiffusionmodels• Smartepitaxialsimulationautomaticallydepositspolycrystalline
films on non crystalline regions of the device• Polysilicongrainboundarydiffusionmodelsandmore.
ATHENA for Technology Simulation
Full process simulation, with sophisticated experimentally verified models for oxide growth, deposition, etch, epitaxy, implantation and diffusion.
Calibration example for the effects of a SiGeC film on adjacent boron markers from implanted silicon interstitial surface damage and subsequent TED. The difference in dif-fusion of the deeper boron marker is a direct result of carbon incorporation in the SiGe film, which effects interstitial transport properties.
SiGe/SiGeCDesignFlowsolutionsarecalculatedfromthefirstprinciplePhysics.Thisresultsinpowerful,predictive,frequencydepen-dentsolutionswhereadesignercanextractanyelementfromtheLayout,beitanInductor,Capacitor,ResistororTransmissionLineandusing3Dprocessinginformationandfundamentalphysics,extractatwoportfrequencydependentnetworkforeachcomponentandcreateanRFSPICEequivalentcircuit.SPICEequivalentcircuitsforActiveDevicescanbesimulatedfromrealisticProcessandDeviceSimulators or can be extracted from measured data. Interconnect Parasitics are extracted from Layout Driven, 3D Process Physics and FieldSolversandbackannotatedontotheSPICEnetlist.
Technology Simulation
Silicon/SiGe Multi-Quantum Well (MQW) wave-guide photo diode structure created in ATHENA using process simulation. The photodetector uses a thick epitaxial layer grown on a SIMOX Silicon On Insulator (SOI) substrate to act as a waveguide for the detector located at the top of the structure. The structure is then seamlessly imported into ATLAS for electrical and optical characterization.
Process and device simulation
Device simulation allows the designer to directly analyze the effects of his design on all relevant parameters in the device. Here the potential drop from parasitic collector resistance is shown when the device is operating at high current.
DC characteristics showing gummel plot of SiGe HBT.
ATLAS/Blaze seamlessly takes devices created in ATHENA/SSuprem4and provides numerous simulated outputs for complete virtual analysis of all aspects of the active devices:
• DCI-V,Gummelandbreakdowncurves• ACanalysisforaccurateextractionofFt/Fmaxandcapacitancedata• Sparameter,Yparameter,Zparametercalculations• TransientanalysisforlargesignalInputs• Analysisofcriticalparameterswhichimpactdevicereliability• 1/f,trapanddiffusioninducednoisecalculations• User-definablemodelsandparameters
ATLAS for Technology Simulation
Optical Helmholtz solution for the SIMOX SiGe MQW wave-guide structure created in ATHENA shown on the previous page. The 3D simulation takes account of optical absorption in the Z direction.
Photo induced current generated by SIMOX SiGe MQW waveguide detector.
I-V output characteristics of a SiGe HBT optimized for high ftmax showing low breakdown voltage.
Process and device simulation
Oncethecircuithasbeendesigned,CLEVERisusedtofieldsolvethe entire cell and calculate additional parasitic resistance and capacitance originating from the interconnect circuitry, which is thenbackannotatedontotheSPICEnetlist.Silvacoalsooffersfullchipsolutions for larger circuits using standard rule based methodology ratherthanphysics-basedsimulation.
CLEVER/STELLAR - Full 3D, Cell Level Parasitic Capacitance and Resistance Extraction
Cell level parasitic extraction using Full 3D realistic processing simulator and field solver.
Minimum noise figure versus collector current simulated in ATLAS for a SiGe HBT. The three curves are for frequencies of 2, 5 and 10 Ghz and a collector voltage of 1 volt.
STELLAR can be used to field solve much larger circuits at the expense of realistic process simulation.
Ft and Fmax data calculated from AC analysis performed at each bias point.
Process and device simulation
Silvacooffersacomprehensive,2D/3D,physically-based,layout-driventoolsetforcharacterizingandextractingfrequencydependentSPICEequivalentcircuitsforpassivecomponentsandparasitics,includingtransmissionlines,inductors,capacitorsandresistors.
QUEST - RF Model Extraction for Inductors and Parasitics Components
QUESTused in 2Dmodeallows thecircuit designer togenerateacrosssectionfromanywhereinthelayoutandproduceafrequency-dependent transmission line SPICE W-element model and RLCGdata, using basic film thickness interconnect information obtainedfrom the foundry. Since transmission lines are two dimensional in nature,a2Dsimulationonlyisrequiredinthiscase.
Transmission Line Model Extraction
Usinglayoutandinterconnectthicknessinformation,arbitraryshapedinductors,capacitorsandresistorsarecreatedinfull3DandQUEST’sphysically-based simulator generates a frequency dependent Twoportormulti-portSPICEequivalentcircuitorS-parameteranalysisforeach of the elements in the design.
Arbitrary Shape 3D Inductance, Capacitance and Resistance Extraction
Potential and field visualization for a pair of conductors.
Example Inductor 2 port equivalent circuit extraction.
3D spiral inductor structure creation and visualization showing multi-via structures for center connections.
Two port s-parameter analysis RLCG and Q factor outputs from QUEST.
Layout of typical on-chip RF spiral inductor fabricated in SiGe technology.
interconnect modeling
Layout and DRCTheCELEBRITY lineofWindows-NTCADproductsprovide thesophisticatedfea-turesrequiredforSiGe/SiGeCcircuitandlayoutdesigners.Thehierarchicallayouteditor,Expert,andfast,realtimeGuardianDRCsoftware,offerthesekeyfeatures:
• Hierarchicaldesign
• Multi-milliontransistorlayouts
• Arbitraryshapes
• FullchipandlocalDRC
• Scriptlanguage
• GDS-IIandCIFimport/export
• Optimizedautomatedrouting
• Supportforallangles,including45degreesand90degreeobjects
• Interactiveandbatchmodeoperations
• Client-serverdesignandlibrarymanagement
Layout editor with arbitrary shape capability.
Integrated real time design rule checking.
Gateway - Schematic Capture and EditorGatewaySchematicCaptureandEditoristhefront-endoftheanalog/mixedsignal/RFICdesignenvironment. It is tightly integratedwithSilvaco’scircuitsimulation,digitalsimulation,layout,DRC,ERC,LVS,andparasiticextractiontools.AdvancedhierarchicaleditingfeaturesareavailableonUnix,Linux,andWindows.
• Powerfulschematiccaptureandeditorfunctionalitytocreateandmodifymulti-view,multi-sheet,hierarchicalICdesigns
• SeamlessintegrationwithSmartSpiceCircuitSimulatorthatcreatesaninteractivedesignenvironmentwithbehavioralmodels,cross-probing,waveform display, and analysis
• Controlsmulti-userprojectswithsharedworkspacesforlibrariesofcellsand symbols used by the design team
• Smoothtransitionfromotherschematiccapturetools–out-of-the-boxsetupwithnoconsultantsneeded,supportsEDIFinput
• Easytouseatallskilllevels–withonlinehelpfornewusers
• Productiveanalogdesignenvironmentoffersparameterizedcells(Pcells),automaticsymbolgeneration,real-timesimulationviewing(marchingwave-forms),andmulti-userschematiclocking
• SameenvironmentacrossUnix,Linux,andWindowsplatforms–idealforwide-scaledeployment
Frequency response of tuned circuit amplifier circuit shown above created in Gateway, which was then run in SPICE directly from the schematic capture tool and analyzed using the integrated “cross-probing” feature.
1 GHz RF amplifier designed in Gateway using drag and drop elements, includ-ing the SiGe HBT and associated SPICE VBIC model extracted using UTMOST.
custom ic cad
UTMOST III - Parameter ExtractionUTMOST III isacompletely integratedsoftwarepackage toprovide forautomaticdataacquisition,parameter fittingandSPICEmodelextraction, optimization, simulation and model validation.
• Comprehensivedevicecharacterizationandmodelingcapabilities
• Supportsawiderangeofmeasurementequipmentandprobers
• Fullyinteractive,semi-automatic,orbatch-modeoperation
• Step-and-repeatoperationincludingwafercassettecontrol
• DC,AC,transient,andcapacitancetestroutines
• MOSFET,BJT,Diode,JFET,GaAs,SOI,TFT,andHBTmodules
• InterfacestoprocessanddevicesimulatorsandtotheSPAYN statistical parameter analysis tool
• Supportsawidevarietyofmodelsandcircuitsimulators
Features
Ft measurement and SPICE simulation from derived Gummel Poon SPICE parameters.
Measured output characteristics and SPICE simulation from derived VBIC SPICE parameters.
Measured Gummel plot and SPICE simulation from derived VBIC SPICE parameters.
Typical RF test measurement setup controlled by UTMOST.
Data can be imported into Silvaco’s statistical package, SPAYN, for analysis including wafer maps, corner models and statistical process control.
analog and mixed signal
SmartSpice RF - Expanding Proven Leadership into RF SPICE SimulationSmartSpice today is the technology and performance leader in analog circuit simulation. Rapid worldwide acceptance demonstrates SmartSpice is redefiningindustrystandards forconvergence,speed,accuracy,capacity,ease-of-use,andlicensing.SmartSpiceoffersmanyuniquefeaturesincluding:
• CompatibilitywithHSpiceTM, PSpiceTMandBerkeleySPICE
Simulation of wide band amplifier.
HBT Gummel plot simulated using SPICE VBIC models.
Load circles and s-parameters calculated using the RF SPICE current simulator.
Harmonic balance simulations in RF SPICE allows modulated signals with very wide difference in frequencies to be simulated which would require an unrealistically large member of cycles to achieve using conventional SPICE.
HBT I-V output characteristics simulating using SPICE VBIC models.
• Alibraryofthemostadvancedandcomprehensivedevice models available
• SamecapabilityavailableonbothUNIX,Linuxand PC platforms
• Aggressiveandaffordablesitelicensing
analog and mixed signal
MaskViewsisintegratedwithSilvacoproducts.
HeaDquarTers
4701 Patrick Henry Drive, Bldg. 6
santa Clara, Ca 95054 usa
Phone: 408-654-4309
Fax: 408-496-6080
JaPan [email protected]
eurOPe [email protected]
KOrea [email protected]
Taiwan [email protected]
singaPOre [email protected]
CaLiFOrnia [email protected]
408-567-1000
MassaCHuseTTs [email protected]
978-323-7901
Texas [email protected]
512-418-2929
arizOna [email protected]
480-947-2900
WWW.SILVACO.COMRev.101607_08
