Implementation Of A Testbed For Evaluating Energy

Efficiency In Passive Optical Network

Supervisor Submitted by,Dr. Luca Valcarenghi Neelakandan Manihatty Bojan

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Outline

• Introduction• Scope of the thesis• State of the art• Testbed architecture• Testbed implementation• Conclusion • Future scope • Bibliography

Introduction

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ONU architecture

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Stratix 4GT FPGA board

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FPGA architecture

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Scope of the thesis To implement an Energy Efficient ONU (ECONU)

prototype for EPON in Altera FPGA based on the finite state machine (FSM).

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State of the art

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Testbed architecture

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Frame and Packet format

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Design Specification

Behavioral Description

RTL Desctiption (HDL)

FunctionalVerification and Testing

Logic Synthesis

Gate-Level Netlist

LogicalVerification and Testing

Floor PlanningAutomatic Place & Route

Physical Layout

Layout Verification

Implementation

VLSI design flow

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Birds eye view of the design

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Negative exponential inter-arrival time

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Birds eye view of sleep controller module

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FSM implementation

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Resource utilization

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Device resources summary

Resource utilization of design

SignalTap

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Testbed setup

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Simulation + Synthesis

.sof (SRAM based object

file)

Programming the FPGA

Commands given through

System console and Signal tap

Executes commands and

provides the results back

Results

Internal Loopback Local Loopback

There are two main test modes used in the design

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Sleep time

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Low power idle time

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Wake time

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Analytical evaluation

• Sleep time Ts = 2.88µs• Low power idle time Tlp = 39.68µs• Wake time Tw = 4.48µs

• Total sleep time = Actual sleep time + Overhead associated with transitions

= Low power idle time + Sleep time + Wakeup time = 39.68µs + 2.88µs + 4.48µs = 47.04µs

So the overall percentage of the actual sleep time in a sleep request = (Low power idle time / Total sleep time)*100

= (39.68µs/47.04µs)∗100= 84.35%

• Similarly the overall percentage of the sleep time and the wake time is 6.1% and 9.5% respectively.

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Energy efficiency characteristics

Packet size = 1500 Bytes Packet size = 1000 Bytes

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Energy Efficiency characteristics

Packet size = 500 Bytes Packet size = 100 Bytes

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Analytical evaluation of energy savings

Pa : Power consumed by the ONU during Active state

Plpi : Power consumed by the ONU during Low Power Idle state

Ta : Time spent in Active state

Ts : Time spent in Sleep state

Tlpi: Time spent in Low Power Idle state

Tw : Time spent in wake state

ONUcycletime = ΣONUtimespentinindividualstates =Ta+ Ts + Tlpi + Tw

Let the energy consumed by the ONU with sleep be denoted by Es and the one without Sleep technique be Ews

Ews=Pa∗(Ta+ T s +Tlpi + Tw)

The energy consumed by the ONU when it is has the Sleep technique implemented in it, is given by the following equation.

Ews=Pa∗(Ta+Ts +Tw) +Plpi∗Tlpi

Energy Savings =((Ea−Eb)/Ea)∗100

Energy Savings =((Pa−Plpi)∗Tlpi/(Pa∗(Ta+Ts +Tlpi +Tw)))∗100

Consider Pa= 10∗ Plpi

Energy Savings =(0.9∗Tlpi/(Ta+Ts +Tlpi +Tw))∗100

By substituting the values of the Ta = 1µs; Ts= 2.88µs; Tlpi= 39.68µs; Tw = 4.48µs,

the resulting Energy Savings is around 75%26

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Generator consistency Throughput Vs Packet size

Exponential inter-arrival time results

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Conclusion• This thesis proposed and implemented a sleep mode technique in the data link

layer for Ethernet PONs in Altera Stratix 4GT FPGA. The sleep technique is based on the FSM implementation written in Verilog HDL.

• The FSM switches the ONU ”on” and ”off” based on the sleep request en-coded explicitly through out green header implementation based on the sleep time, low power idle time and wake time are all based on IEEE 803.az standard.

• The analytical evaluation for the proposed design provides Energy efficiency of 75% , when the power during active state is ten times the power at low power state. The results obtained after the implementation coincides with the analytical results. Hence substantial energy savings is achieved with our implementation.

• The implementation was performed on the testbed setup in two different modes: local loopback and internal loopback. Similar results were obtained for both the configurations. For the implementation with standard values as defined in IEEE 803.az

• Additionally, a negative exponential inter-arrival module was developed. This is integrated in the generator to emulate the inter packet arrival times. So that packet arrivals can be modeled with various statistical distributions. 29

Future scope• For the ONU to have low power consumption, it has to remain in the sleep

mode as long as possible. The longer the better. But for guaranteed quality of service (QOS), the buffers should be large enough to store all the packets which arrive even when the ONU is sleeping.

• They buffers should be intelligently managed both in terms of buffer size and the number of buffers. This in itself is an interesting task which requires buffer optimization mainly due to the limited resources available in the FPGA.

• In the real time scenario, implementation of the buffer(s) would be inevitable because:

– Numbers of users are ever increasing.– Traffic is increasing.– Bandwidth requirements are rising.– QOS has to be guaranteed.

• Taking all the above into considerations, a dynamic sleep protocol is required. This should not only manage the buffers, but also should synchronize with both the OLT and ONU.

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Grazie

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