Impedance and Transient Current Fundamentalspdnpowerintegrity.com/wp-content/uploads/2018/05/DesCon... · 2018-05-04 · " Simple RLC circuit closely represents system ... l Impedance

Impedance and Transient Current Fundamentals

Larry Smith, 1/27/15

– 2 –

Agendan PDN Overview and Measured Responsesn PDN Equations

– Frequency Domain• Target impedance• Resonant peak

– Time Domain• Transient currents• Clock edge• Time average

n Time Domain Responses– Impulse– Step– Resonance

n Which comes first, voltage or current?n Switched Capacitor Loadn Responses to CMOS loads

3

Components for Power Distribution Network (PDN)

Impe

danc

e (m

Ohm

s)

PMIC bulk cap high frequency caps die cap

PDN resonancetarget

max min

1.2 0.05 107 2

Vdd tolerance VZ mOhmI I A A

× ×= = =

− −

4

System Cross Section

• Die on Package on PCB• Capacitance is mostly on the die • Inductance is mostly in the package and PCB• Resistance is in the die, package, PCB and capacitors• Simple RLC circuit closely represents system• Next we will examine lab measurements for a real hardware system

Core Sense PCB

decap

die

package

PCB

5

PDN Impulse Response

PCB – 10mv/div

On-die – 50mv/div

Sag: 105mV

pk-pk: 172mV

pk-pk: 11mV

• FPGA circuits switched only once– Single clock edge– One impulse of clock edge current– Impulse response signature

• Fall time is 300ps– all charge must come from on-die capacitance

• Initial voltage sag:

• System PDN responds to “impulse” of current– Damped sinusoid at resonant frequency

• On-die PDN noise is much higher than PCB PDN noise

– 172 mV p-p– 105 mV sag

_ /clock edge odcV Q C∆ =

6

PDN Step Response • Burst of impulses

– Many impulses• Clock edge current

– Package current ramps up– PDN transient response

• Damped sinusoid• PDN responds when clock stops

– Inductance drives current into die capacitance– PDN response with damped sinusoid

• Clock gating– Fclock = 266MHz– Modulate at any frequency

• Core voltage– Droop: 146mV– Pk-pk: 228mV

• Larger than impulse (172 mV)

PCB – 50mv/div

Core – 50mv/div

idle

Core logic activity

7

PDN Resonance Response• Clock gating

– Fclock = 533 MHz– Fgate = 33 MHz

• Step transients repeat at PDN resonant frequency 33MHz

• Known as “Resonance Response”– AKA “periodic burst transient”

• 577mV pk-pk PDN noise– 1.1V nominal supply– +- 26% supply…

• Worst case PDN noise– Will not happen under normal operation– Clock gating can cause this– Power gating can cause this

– 8 –






9

Target Impedance Definition

• Based on Ohms Law• Two easily understood and

difficult to obtain parameters– Tolerance– Transient current

• Can be expressed as percentage of maximum current

• Target impedance is a function of frequency if

– tolerance is a function of frequency– Transient current is a function of

frequency

targetmax min

1.2 0.05 107 2

Vdd tolerance VZ mOhmI I A A

× ×= = =

− −

Supply that meets Ztarget almost certainly will not exceed specified

voltage tolerance with given transient current

… but that can be expensive …

10

Equations for Series and parallel circuits

• Measure series resonance from the FPGA balls• Simulate parallel resonance from FPGA circuits• The RLC elements are the same

01

2f

LCπ=

0LX ZC

= =

0 /- Z L CQ factorR R

= =

2

0/-peak

X L CZ Z Q factorR R

= =B i

Resonant frequency

Reactance at resonanceEstimate of impedance peak at resonance

Impe

danc

e (O

hms)

Z

ZTarget

Z0

– 11 –

PDN Parameter Calculations – Frequency Domainn Spread Sheet for PDN parameter calculations

– Inputs (independent parameters) are the green shaded cells– Results (dependent parameters) are calculated in the white cells

n Desire 100 mOhm peak at 100 MHz– Choose 50 nF for on-die capacitance

– Calculate L

– Calculate Z0

– Calculate q-factor

– Choose R for 100mOhm peak

0 /Z L C=

( )0 1 / 2f LCπ=

0- / / /q factor Z R L C R= =

0/-peak

L CZ Z q factorR

=B i

Impe

danc

e (O

hms)

Frequency Domain Vdd 1 VCore Cap 50 nFPDN loop Inductance 50.7 pHPDN loop resistance 10.1 mOhmdynamic current 1.55 AResonant Frequency 100 MHzPDN Z0 32 mOhmq-factor from PDN loop 3.15Expected impeance Peak 100 mOhmTarget Impedance 32 mOhmAssumed Die resistance 5.0 mOhmExternal PDN loop resistance 5.1 mOhm

12

Transient Current Considerations

• Transient current paradox– Commonly used terminology– But often misunderstood…

• Examples of Transient current– Impulse: Clock edge current– Step: Burst transient– Resonance: Periodic burst transient

• Itransient = Imax – Imin = dI• Current waveforms have large variation across system

– Filtering effect of inductance and capacitance– Very different time constants

• Current profiles have frequency content depending on length of time, dt– 100’s of pSec only affects die– Few nSec affects package– 10’s of nSec affects PCB– µSec affects VRM

13

n Clock edge current:− Instantaneous current drawn

by die logics at clock edges

n Charge per clock cycle:− Independent of clock frequency

n Dynamic current:− Time averaged clock edge current− Comes with the clock− Static (leakage) current not included− Used for target impedance design− Proportional to clock frequency

0 2 4 6 8 100

10

20

30

40

50

60

70

Time [ns]

Cur

rent

[A]

Clock Edge Current

Dynamic Current

Area is charge per cycle

Clock

∫ ⋅=T

edgeclk dttiQ0 _ )(

∫ ⋅==T

edgeclkdynamic dttiT

TQI0 _ )(1/ 0 2 4 6 8 10

0

10

20

30

40

50

60

70

Time [ns]

Cur

rent

[A]

unchanged

doubled

Current Definitions – On-Chip Level

Time Average Dynamic Current

• System level current considerations• Low Activity:

– Clock is active but Data is Idle

• High Activity: – Clock and Data are active

• Transient Current: – high-activity dynamic current minus low-

activity dynamic current– AKA power transient

Low Activity Low ActivityHigh Activity

Clock Edge Current

Time Average Dynamic Current

System Level PDN responds to power transients.Clock edge currents are filtered by the package.

– 15 –

PDN Parameter Calculations – Time Domainn Dynamic current is easily calculated

– Average bench current – Clock frequency– Assumes all clock cycles are equal

n Each average clock cycle consumes this amount of charge

n Charge is consumed from on-die capacitance

n Impulse response (droop) from single clock cycle

n Step response (droop) from fast edge

n Resonance response (peak-peak) from repeating steps

/cycle dynmic clockQ I f=

/ 1.55 /1 3150

cycle dynamic clockclock edge

Q I f A GHzV mVODC ODC nF

= = = =

Q CVdQ C dV

== i

0 1.55 32 49step stepV I Z A mOhm mV= = =i i

0LPDN ZC

=

Frequency Domain Vdd 1 VCore Cap 50 nFPDN loop Inductance 50.7 pHPDN loop resistance 10.1 mOhmdynamic current 1.55 AResonant Frequency 100 MHzPDN Z0 32 mOhmq-factor from PDN loop 3.15Expected impeance Peak 100 mOhmTarget Impedance 32 mOhmAssumed Die resistance 5.0 mOhmExternal PDN loop resistance 5.1 mOhm

Time Domain f clock 1 GHz

charge per clock cycle (Qcycle) 1.55 nCoulExpected clock edge droop (impulse) 31 mVExpected step response droop 49 mVExpected peak-peak noise at resonance 198 mV

4 4- 1.55 100 198resonance tran peakP P I Z A m mVπ π

= = Ω =i i

– 16 –






Impulse Response – PWL Current Source

– 17 –

n Impulse of charge is consumed from PDN

n Happens in less than 1 clock cyclen Calculate droop from Q=CV

n Simulated Droopl 29 mV

l Some current came in during impulse

n Droop is determined by on-die capacitancel Inductance has no effect

l Impedance peak has no effect

dynamic

clock

IQ

f=

/ 1.55 /1 3150

dynamic clockdroop

I f A GHzV mVODC nF

= = =

Convention: Current into a circuit element is positiveImpulse of current

drawn by circuit load

PDN loop current

Voltage response

Step Response and Characteristic Impedance - Transient

– 18 –

n PDN parameters chosen so that

n PDN Parametersl Vdd=1Vl Itransient=1.55Al Tolerance=5%l Cap = 50 nFl Inductance = 50.7 pH

n Step Response Droopl 50 mVl Same as 5% tolerance

1 5% 321.55target

transient

Vdd toleranceZ mOhmI× ×

= = =

50.70 3250

L pHZ mOhmC nF

= = =Make Z0=Ztarget in order to have step response droop = tolerance

0 /targetZ Z L C= =

Step of currentdrawn by circuit load

PDN loop current

Voltage response

Resonance Response

– 19 –

n Estimate P-P noisel Zpeak is 103 mOhms

l Itran = 1.55A pulses for 5 nSec

l The 4/π comes from Fourier transform of square wave

n Simulated P-P noisel 201 mV

n Mitigate resonant peak byl Reducing L

l Increasing C

l Increasing R (damping)

4

4 1.55 103

203

resonance tran peakPP I Z

A m

mV

π

π

=

= × Ω

=

Repetitive steps of currentdrawn by circuit load

PDN loop current

Voltage response

– 20 –






Current, Voltage and Time for Reactive Componentsn Capacitorn Voltage lags behind current

– Current into capacitor changes voltage

– I/C is the forcing function– dv/dt is the result

n Inductorn Voltage leads current

– Voltage across inductor changes current

– V/L is the forcing function– di/dt is the result

– 21 –

di Vdt L

=dv Idt C

=1V I dtC

= ∫ i1I V dtL

= ∫ i

Transient Current, Rise Time and di/dtn If di/dt is a result of V/L….n Then why do we often consider di/dt to be the enemy, the cause of PDN noise?

l The “small-signal” ratio of di/dt is not the problem

n The “large-signal” transient current is the problem (dI)l A larger transient current contains more noise energy and requires lower impedance

n A short time span (dt) makes the problem worsel Raises the frequency of the noise. l May stimulate high frequency impedance peak if it is fast enoughl dt determines the portion of the PDN that will supply the current

u VRM, board capacitors, package capacitor, On-die capacitance

n dI and dt are independent parameters and should not be considered to be a ratiol Large di/dt is associated with low inductance and is a good thing

– 23 –

Voltage and Current in Time – Impulse Response

n Single clock edge creates impulse n Sequence of Events

– Circuits consume die current (charge)– Die voltage droops– Current comes in from outside inductor

• Brings voltage back to nominal– Current diminishes as die voltage rises above nominal

n Inductor current ramps up until die voltage returns n Current into die capacitance leads die voltage

Inductor current responds to voltage across it (voltage leads current)

Die capacitor voltage lags behind inductor current

Load CurrentPDN Current

Die Voltage

+

Die Voltage

--

+ --

PDN Current

– 24 –

Half the Inductance Doubles the di/dt

n Cut PDN inductance in half– 25.35 pH

• down from 50.7 pHn Charge consumed from die is constantn Inductor di/dt doubles

– Slope is twice as steep– Current ramps up faster

n Initial droop is the same– Resonant frequency is higher– q-factor is lower

di/dt is the inductor response to V/L

+

Die Voltage

--

+ --

PDN Current

Load CurrentPDN Current (solid)

Die Voltage

PDN Current with half the Inductance (dashed)

Die Voltage with half the Inductance (dashed)

– 25 –

Key Concepts for PDN on-die capacitance and inductorn The on-die voltage can only be changed by passing current through the capacitance

n The root cause of PDN voltage noise is charge drawn from the on-die capacitance

– The on-die voltage noise is inversely proportional to C

– The voltage noise during the clock cycle is determined by the charge (integral I x dt)

n Inductor current does not come in from the outside world until the die voltage drops

– Current through the inductor remains constant until a voltage appears across it

– A smaller inductor makes a higher di/dt and brings current in faster (this is good)

1V I dtC

= ∫ i

1I V dtL

= ∫ i

di Vdt L

=

+

Die Voltage

--

+ --

PDN Current

– 26 –

Take-Aways

n Increase the die capacitance to reduce the voltage noise– Fast PDN noise droops are proportional to 1/C

n Reduce the system inductance to bring current (charge) into the die faster– Incoming current reduces the charge delivered by the on-die capacitance

n Both of these are costly– But you get what you pay for

– 27 –






Time Domain Load Circuit

• Previous Loads– Current source

• Current is independent of voltage• Provides no damping

– Time varying resistor• Current diminishes with less voltage• Provides damping

• New Load Circuit– Operates the same way as CMOS circuits

• Current is proportional to voltage• Provides damping

– Portion of the ODC is switched• Switch factor

– Easily handles power transients• Load capacitance changes with time• Take some capacitance from the load and put it back into ODC

Load Operation

• Switch low-to-high– Current charges lower cap– Upper cap discharges

• Switch high-to-low– Current charges upper cap– Lower cap discharges

• Resistor sets time constant– 2x current for each edge– Reverses direction for each edge– 1x current drawn from ODC for each edge

• Switch factor– Calculated in spread sheet – Draws dynamic current from package– Expressed as percentage of ODC

• Transient current– Load capacitance varies with time– Example: draw 8 amps at 500 MHz (max current)

• 10% of ODC is placed in load cap position• A 50% current transient is desired (draw 4 amps)• Load cap is reduced by half to 5% of ODC• Clock frequency remains the same but 4 amp transient has

occurred• Real CMOS circuits operate this way

ODC

ODC

Load cap

Load cap

Load Waveforms• Load voltage alternates between 0V and 1V (red)• 2x Current is drawn through resistor both

directions (blue)• 1x Current is drawn from ODC on each edge

(green)• Events

– 10nSec: load starts– 20nSec: load drops in half– 30nSec: back to full load

• 10% switching factor– 40nSec: half load

• 5% switching factor• Load capacitance changes with time• Time constant is set with resistor

31

Calculate Switch Activity from Q=CV

• One Clock Edge– PDN Impulse Response

• Initial voltage sag:

• Calculate average clock edge charge

• Calculate the capacitance that must have switched

• Calculate the switch factor given the on-die capacitance

_ /clock edge odcV Q C∆ =

Voltage volts 1.10Dynamic AVG current per channel or bank* amps 10.0clock frequency MHz 533charge per cycle nCoul/cycle 18.8load capactiance that switched nF 17.1switch factor % 5.7DieODC (on-die capacitance) nF 300

10amp 18.8nCoul533MHzedge

currentqfrequency

= = =

18.8nCoul 17.1nF1.1Vswitched

qCV

= = =

17.1nCoul. . 0.057 5.7%300 nCoul

switchedqS FODC

= = = =

– 32 –






Impulse Response – Switched Capacitor Load

– 33 –


n Happens in less than 1 clock cyclen Calculate droop from Q=CV

n Simulated Droopl 29 mVl Some current came in during impulse

n Droop is determined by on-die capacitancel Inductance has no effectl Impedance peak has no effect

dynamic

clock

IQ

f=

/ 1.55 /1 3150

dynamic clockdroop

I f A GHzV mVODC nF

= = =

Step Response and Characteristic Impedance - Transient

– 34 –

n PDN parameters chosen so that

n PDN Parametersl Vdd=1Vl Itransient=1.55Al Tolerance=5%l Cap = 50 nFl Inductance = 50.7 pH

n Step Response Droopl 52 mVl Nearly 5%l Same as tolerance

1 5% 321.55target

transient

Vdd toleranceZ mOhmI× ×

= = = 50.70 3250

L pHZ mOhmC nF

= = =

0 /targetZ Z L C= =

To have step response droop = tolerance, make Z0=Ztarget

Resonance Response – Switched Capacitor Load

– 35 –

n Estimate P-P noisel Zpeak is 103 mOhmsl Itran = 1.55A pulses for 5 nSec

l The 4/π comes from Fourier transform of square wave

n Actual P-P noisel 197 mV

n Mitigate resonant peak byl Reducing Ll Increasing Cl Increasing R (damping)

4

4 1.55 100

198

resonance tran peakPP I Z

A m

m

π

π

=

= × Ω

= Ω

Compare Impulse, Anti-Impulse and Step Responses

– 36 –

n Anti-impulse is one missing pulsel Signature is nearly opposite that

of impulse

n Compare droopsl Impulse

u 29 mV

l Stepu 55 mV

l Anti-impulseu 36 mV

n Mitigationl Only C helps impulses

l Both L and C help step response

Anti-step Response – Switched Capacitor Load

– 37 –

n Anti-step happens when current goes awayl Signature is nearly opposite

that of step response

n Compare responsesl Step droop

u 56 mV

l Anti-step peaku 38 mV

u Starting point is down because of DC IR drop

n Step response should have more damping from on-die loadl Current source load does not

show this

Summary n PDNs are best analyzed and designed in the frequency Domain

– Reactive components: R, L and C

n PDN time domain responses are all the only thing that matter to the product– Impulse, Step, Resonance responses must be managed

n The Target Impedance is the reference level to determine the performance of PDN– The step response will stay within tolerance if Z0 = Ztarget– The p-p resonance response is determined by Zpeak

n CMOS dynamic current comes from a series of current (charge) impulses– Logic activity draws an impulse of charge at each clock edge– Average clock cycle charge is calculated from bench current and frequency– On-die voltage droop from single impulse is calculated from Q=CV

n The on-die voltage must droop before current comes in from outside world– Capacitor dv/dt = I/C– Inductor di/dt = V/L– Large signal transient current is very important, small signal di/dt (slope) is not very important

n Switch capacitor loads behave like CMOS– Current source loads have no damping

n PDN time domain noise is mitigated by:– Capacitance for clock edge impulse response– Capacitance and inductance for step response– Resistance (q-factor) for resonance response

0 /Z L C=

targettransient

Vdd toleranceZI×

=

4resonance tran peakPP I Z

π=

/ fcycle dynamic clockQ I=

/cycle dynamic clockdroop

Q I fV

C ODC= =

0droop stepV I Z= ×

2 /peak

X L CZ X QR R

= =B i

0

0

_ peak

loop

Z ZQ factorZ R

= =

PDN Tutorial contents were drawn from these publications

n L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, T. Roy, "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology," IEEE Transactions on Advanced Packaging, Vol.22, No.3, P284, August 1999.

n L.D. Smith, S. Sun, P. Boyle, B. Krsnik, "System Power Distribution Network Theory and Performance with Various Noise Current Stimuli Including Impacts on Chip Level Timing,” Proc. Custom Integrated Circuits Conference, September 2009.

n S. Sun, L. D. Smith, P. Boyle, B. Krsnik, "On-Chip PDN Noise Characterization and Modeling,” Santa Clara, CA, DesignCon 2010.

n L.D. Smith, M. Sarmiento, Y. Tretiakov, S.Sun, Z. Li, S. Chandra, “PDN Resonance Calculator for Chip, Package and Board, Santa Clara, CA, DesignCon 2012.

BACKUP SLIDES• Comparison of current source,

current impulse and switched capacitor loads..

– 40 –

Impulse Response – Compare PWL Current and Switched Capacitor Load

– 41 –


n Triangle current sourcel dottedl PWL current curvel Area under curve is charge consumed

n Switched Capacitor Loadl Solidl Smooth current curvel Capacitor load calculated to consume

correct charge

n Small amount of current (blue) comes in from inductor during current pulsel Slightly reduces voltage droop

dynamic

clock

Iq

f=

/ 1.55 /1 3150

dynamic clockdroop

I f A GHzV mVODC nF

= = =

Impulse Response – Zoomed Out Compare

– 42 –


n Triangle current sourcel PWL current curve

n Switched Capacitor Loadl Smooth current curve

l Capacitor load calculated to consume correct charge

dynamic

clock

Iq

f=

/ 1.55 /1 3150

dynamic clockdroop

I f A GHzV mVODC nF

= = =

Step Response

– 43 –

n Straight current sourcel dashed

n Impulse current sourcel dotted

n Switched capacitor loadl Solid

n Currentsl Load current is green

l Bump current is blue

n Voltages are similarl Charge and time averaged

current consumed from on-die capacitance is similar

Resonance Response

– 44 –

n Straight current source

n Impulse current source

n Switched capacitor load

n Currentsl Load current is green

l Bump current is blue

n Voltages are similarl Charge and time averaged

current consumed from on-die capacitance is similar

Resonance Response – triple the current

– 45 –

n More voltage droop at higher current levelsl Baseline current has tripled

l Z0 is now 3x Ztarget

n Sources behave differentlyl Current sources draw same current without

regard to voltage

l Switched capacitor circuit draws less current at less voltageu Has more damping

Documents

Impedance and Transient Current Fundamentalspdnpowerintegrity.com/wp-content/uploads/2018/05/DesCon... · 2018-05-04 · " Simple RLC circuit closely represents system ... l Impedance