4
Impact of Random Telegraph Noise with Various Time Constants and Number of States in CMOS Image Sensors Rihito Kuroda a , Akinobu Teramoto b and Shigetoshi Sugawa a,b a Graduate School of Engineering, Tohoku University, b New Industry Creation Hatchery Center, Tohoku University 6-6-11-811, Aza-Aoba, Aramaki, Aoba-ku, Sendai, Miyagi, Japan 980-8579 TEL: +81-22-795-4833, FAX: +81-22-795-4834, Email address: [email protected] ABSTRACT In this work, the impact of random telegraph noise (RTN) with various time constants and number of states to noise characteristics of CMOS image sensors are summarized based on a statistical measurement and analysis of a large number of MOSFETs. The obtained results suggest that from a trap located relatively away from the gate insulator/Si interface, the trapped carrier is emitted to the floating diffusion (FD) node. Also, an evaluation of RTN using root mean square values tends to underestimate the effect of RTN with large amplitude and relatively long time constants or multiple states. It is proposed that the amplitude of noise should be incorporated during the evaluation. INTRODUCTION Detection, characterization and reduction of random telegraph noise (RTN) are critically important in CMOS image sensors (CIS) [1] . A transition of the trap state (filled or empty) of in-pixel source follower (SF) during correlated double (CDS) sampling generates RTN in CIS. RTN induces relatively large noise amplitude at fixed pixels, and the visibility of RTN in captured images is quite significant. Especially for CIS with sub-electron readout noise, RTN becomes a stumbling block to achieve photon-countable sensitivity with all the pixels [2] . By using the array test circuit, we have previously reported statistical analysis of RTN regarding the effects of device structures, process conditions, detailed analysis of time constants and so on [3-8] . The parameters of RTN include amplitude, time constants (time to capture, c and time to emission, e ,) and number of states, and these parameters vary significantly among transistors. For example, measurement results of RTN with sampling period of 1μs and sampling time of 600s revealed that the time constants ratio (< c >/< e >) in two-state RTN is distributed for at least nine order of magnitude [6] . Also, various types of multi-state RTN incorporated with multiple number of traps in a transistor have been reported to appear [7] . The effect of RTN during CIS operation may also vary due to the different sets of RTN parameters. For CIS in general, the effect of RTN is evaluated by the measured values of root mean square of pixel output signal after CDS. The effect of RTN with various parameters to the readout noise of CIS has not been fully studied. Recently, an extraction method of characteristic time constants of RTN ( s ) based on double sampling has been reported to be useful [9] . In this work, we describe the impact of RTN with various time constants and number of states in CIS operation using CDS in order to clarify the effects of RTN with various parameters and propose an evaluation method thereof. Distribution of time constants and their behavior to gate overdrive voltage are summarized first. Then, using the waveforms obtained by fast and long sampling (1s period for 600s) of MOSFETs with RTN, noise characteristics in CDS operation with various sampling intervals and sampling numbers were analyzed and important findings are summarized. EXPERIMENTAL SETUP Fig.1 shows the test circuit used in this work to statistically analyze the RTN characteristics [3-8] . Fig.2 shows the block diagram of measurement system. Fig.3 summarizes the experimental procedure in this work. The array test circuit was fabricated by a 0.22μm technology node CMOS technology. The gate oxide thickness and gate size (width/length) of measured MOSFETs are 5.6nm and 0.28μm/0.22μm, respectively. At first, output signal of 131K MOSFETs were measured by non-CDS frame sampling to extract MOSFETs with RTN waveforms. Then, for randomly selected 721 MOSFETs with RTN, non-CDS continuous sampling was carried Fig.1 Test circuit to statistically characterize RTN of in-pixel SF. Test Chip PKG Amp. ADC Voltage generator FPGA PC Board Power supply Low Noise Bias Source clk. pulses digital o/p analog o/p Probe card Wafer (On-wafer type) (PKG assembled type) Unit cell VOUT Current Source VREF VG VD Horizontal shift register Vertical shift register Analog memory Fig.2 Block diagram of measurement system. 43 R12

Impact of Random Telegraph Noise with Various Time ... Workshops/2017 Workshop/2017 Papers/… · W/L = 0.28/0.22 Sampling period / time= 10ms / 500 s D rms out for each MOSFET with

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does not change very much in octagonal transistors. Therefore, the transistor structure which does not have the influence of STI edge in the channel carriers is effective for reducing the threshold voltage variation. Fig. 11 shows the correlation between VRMS and SS for the rectangular and the octagonal transistors, respectively. SS was extracted at current range of 10-7 A to 10-6 A. Here, the SS of transistors with VRMS higher 90 μV showing RTN signals were plotted. It is clear that pixels where RTN is observed are often found in an area larger than the average SS value indicated by dotted lines in this figure. The obtained result shows that transistors with large SS lead to large VRMS

[8] in rectangular and octagonal transistors. Fig. 12 shows the appearance probability of transistors with RTN, defined by VRMS of more than 90 μV as a function of the segmented SS regions for rectangular and octagonal transistors. Here, the bin size of SS was taken at 2 mV/decade. It is clear that when SS becomes larger, the appearance probability of transistors with large VRMS becomes higher[8]. Comparing these two types of transistors, there are large SS values in rectangular transistors. It shows that the percolation of channel occurs due to the STI edge. Furthermore, the result suggests that the trap density at the STI edge is higher than that at the gate insulator film on main channel because the appearance probability of octagonal transistors is smaller than that of rectangular transistors at the same range of SS. Fig. 13 shows the cross sectional views of the trapezoidal transistors. Comparing (a) with (b), the transistors with narrow gate width at source side induce

higher carrier density at source side than transistors with narrow gate width at drain side under constant drain current operation. For this reason and from the distribution in Fig. 6(c), it is considered that the increase of current density at source side is effective for reducing RTN because the traps near source side are more influential to the RTN appearance probability[7], and higher drain current density operation reduces the effect of the parasitic transistor due to the sub-channel formed by electric field concentration around the STI edge.

CONCLUSION

In this paper, by evaluating the array test circuit with various shapes of SF transistors in pixels of a CMOS image sensor, it was demonstrated that transistor without STI edge is effective for reducing RTN because of the suppression of generating percolated channel around STI edge where the trap density is likely to be high. It was also shown that increasing carrier density at source side of the channel is effective to reduce RTN. These findings are important to the design of in-pixel SF transistors with small RTN for low noise CMOS image sensors.

REFERENCES [1] C. Leyris et al., Proc. ESSCIRC, p. 376, 2006. [2] M. J. Kirton, et al., Adv. Phys. 38, p. 367, 1989. [3] A. Yonezawa, et al., Proc. Int. Rel. Phys. Symp., p. 3B.5.1, 2012. [4] T. Goto, et al., JJAP 54, p.04DA04-1, 2015. [5] D. Pates, et al., ISSCC, Tech. Dig. Papers, p.418, 2011. [6] M.W. Seo, et al., IEEE Trans. ED, 61, 6, p. 2093, 2014. [7] K. Abe, et al., Proc. Int. Rel. Phys. Symp, p.996, 2009. [8] R. Kuroda, et al., IEEE Trans. ED, 60, 10, pp. 3555, 2013.

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VBS= -1.9VIDS=0.1μA

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bin size= 2mV/dec

Fig. 11. Correlation between VRMS and SS for (a) rectangular transistors (Pix. 2), (b) octagonal transistors (Pix. 6).

Fig. 12. Appearance probability of transistors with RTN as a function of SS.

Fig. 13. Cross sectional views of trapezoidal transistors. (a) Trapezoidal transistor with shorter gate width at source side, (b) Trapezoidal transistor with longer gate width at source side.

(a) (b)

(a) (b)

Impact of Random Telegraph Noise with Various Time Constants and Number of States in CMOS Image Sensors Rihito Kuroda a, Akinobu Teramoto b and Shigetoshi Sugawa a,b

a Graduate School of Engineering, Tohoku University, b New Industry Creation Hatchery Center, Tohoku University

6-6-11-811, Aza-Aoba, Aramaki, Aoba-ku, Sendai, Miyagi, Japan 980-8579 TEL: +81-22-795-4833, FAX: +81-22-795-4834, Email address: [email protected]

ABSTRACT

In this work, the impact of random telegraph noise (RTN) with various time constants and number of states to noise characteristics of CMOS image sensors are summarized based on a statistical measurement and analysis of a large number of MOSFETs. The obtained results suggest that from a trap located relatively away from the gate insulator/Si interface, the trapped carrier is emitted to the floating diffusion (FD) node. Also, an evaluation of RTN using root mean square values tends to underestimate the effect of RTN with large amplitude and relatively long time constants or multiple states. It is proposed that the amplitude of noise should be incorporated during the evaluation.

INTRODUCTION Detection, characterization and reduction of random

telegraph noise (RTN) are critically important in CMOS image sensors (CIS)[1]. A transition of the trap state (filled or empty) of in-pixel source follower (SF) during correlated double (CDS) sampling generates RTN in CIS. RTN induces relatively large noise amplitude at fixed pixels, and the visibility of RTN in captured images is quite significant. Especially for CIS with sub-electron readout noise, RTN becomes a stumbling block to achieve photon-countable sensitivity with all the pixels[2]. By using the array test circuit, we have previously reported statistical analysis of RTN regarding the effects of device structures, process conditions, detailed analysis of time constants and so on[3-8]. The parameters of RTN include amplitude, time constants (time to capture, c and time to emission, e,) and number of states, and these parameters vary significantly among transistors. For example, measurement results of RTN with sampling period of 1μs and sampling time of 600s revealed that the time constants ratio (<c>/<e>) in two-state RTN is distributed for at least nine order of magnitude[6]. Also, various types of multi-state RTN incorporated with multiple number of traps in a transistor have been reported to appear[7]. The effect of RTN during CIS operation may also vary due to the different sets of RTN parameters. For CIS in general, the effect of RTN is evaluated by the measured values of root mean square of pixel output signal after CDS. The effect of RTN with various parameters to the readout noise of CIS has not been fully studied. Recently, an extraction method of characteristic time constants of RTN (s) based on double sampling has been reported to be useful[9]. In this work, we describe the impact of RTN with various time

constants and number of states in CIS operation using CDS in order to clarify the effects of RTN with various parameters and propose an evaluation method thereof. Distribution of time constants and their behavior to gate overdrive voltage are summarized first. Then, using the waveforms obtained by fast and long sampling (1s period for 600s) of MOSFETs with RTN, noise characteristics in CDS operation with various sampling intervals and sampling numbers were analyzed and important findings are summarized.

EXPERIMENTAL SETUP Fig.1 shows the test circuit used in this work to

statistically analyze the RTN characteristics[3-8]. Fig.2 shows the block diagram of measurement system. Fig.3 summarizes the experimental procedure in this work. The array test circuit was fabricated by a 0.22μm technology node CMOS technology. The gate oxide thickness and gate size (width/length) of measured MOSFETs are 5.6nm and 0.28μm/0.22μm, respectively. At first, output signal of 131K MOSFETs were measured by non-CDS frame sampling to extract MOSFETs with RTN waveforms. Then, for randomly selected 721 MOSFETs with RTN, non-CDS continuous sampling was carried

Fig.1 Test circuit to statistically characterize RTN of in-pixel SF.

Test ChipPKG

Amp. ADC

Voltage generator

FPGA

PC

Board Power supply

Low Noise Bias Source

clk.pulses

digital o/p

analog o/p

Probe cardW

afer

(On-wafer type)

(PKG assembled type)

Unit cell

VOUT

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VREF

VG VD

Horizontal shift register

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cal s

hift

regi

ster Analog

memory

Fig.2 Block diagram of measurement system.

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out for each MOSFET with 1μs sampling period for 600s and the parameters of RTN were extracted. After that, the CDS waveforms with various time intervals and sampling numbers were constructed from the obtained non-CDS raw data, and the noise parameters such as root mean square of pixel output voltage (Vrms) and maximum RTN amplitude (ΔVRTN) were extracted to be analyzed.

RESULTS AND DISCUSSIONS Fig.4 shows the cumulative probability distribution of

Vrms of 131K MOSFETs with five drain current (ID) conditions measured at the step 1 in Fig.3. RTN waveforms appeared in about 10% of measured MOSFETs. As previously reported, appearance probability of high Vrms due to RTN is reduced by increasing the drain current. It is because the effect of a trap becomes smaller when the number of carriers in channel is larger. Fig.5 shows the ratio of number of RTN states for the measured MOSFETs under non-CDS continuous sampling extracted at the step 4 in Fig.3. About 40% of the measured MOSFETs with RTN in this work exhibited more than two states under the measurement condition. This suggests the impact of multi-state RTN toward CIS noise characteristics should be paid attention. Fig.6 shows the extracted mean time to capture <c> as a function of mean time to emission <e>. They are distributed broadly for at least six orders of magnitude from several micro seconds to several seconds[6]. Fig.7 shows the dependencies of <c> and <e> on the VGS for extracted 35 MOSFETs[5], and Fig.8 shows the energy band diagrams with capture and emission processes to explain the results in Fig.7. In Fig.7(a), <c> decreases exponentially as VGS increases for all of the extracted MOSFETs. When VGS increases, the channel electron density increases exponentially within the measured conditions. Then the capture probability, which is inversely proportional to <c>, increases exponentially[5]. The dependency of <e> on VGS is categorized into three types as shown in Fig.7(b-d). Here, <e> depends on the distance and difference of energy levels between the trap and conduction band of substrate to which the carrier is emitted[4-5]. In Fig.7(b), <e> increases as VGS increases, it is because the potential barrier toward Si increases. In Fig.7(c), <e> does not

change, indicating the trap position is near the interface. The results in Fig.7(d), where <e> decreases as VGS increases, indicate that for a part of MOSFETs with relatively long <e>, i.e., located relatively away from the interface, trapped electrons are emitted to the poly-Si gate electrode side instead of Si channel side. This is especially problematic to CIS aiming for photon-countable sensitivity because the emitted electrons are mixed with signal electrons at the FD node. This may limit the thinning of the gate oxide of SF, which is effective to reduce RTN amplitude due to the gate capacitance increase.

Figs.9-10 show the relationship of Vrms and VRTN between continuous sampling and CDS modes for various numbers of CDS sampling. Vrms has long been employed as index of noise, however RTN with a large VRTN and a long time constant is underestimated for some applications like movie video capturing in low light level or it may be even undetected because of small Vrms. The VRTN is not suppressed by the CDS operation as indicated in Fig.10 if a capture or an emission occurs during the CDS interval. Fig.11 shows the waveforms, histograms and Vrms as a function of CDS interval for specific four samples A~D shown in Figs.9-10.

Fig.3 Experimental procedure in this work. CDS waveform was constructed by measured continuous sampling data.

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Fig.5 Pie chart of the number of RTN states for (a) ID=0.1A and (b) ID=5.0A, respectively.

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Extract MOSFETs with RTN waveform

non-CDS continuous sampling of randomly picked 721 MOSFETs with RTN

Sampling period / time = 1 μs / 600 sVD =2.5 V, ID=0.1, 0.3, 1, 3, 5 μA

Set Vbs=-1.2 V for each MOSFET

Extract RTN parameters: number of states, c, e, s, Vrms

and RTN Amplitude (VRTN)

CDS data construction from step Sampling period / time= 10ms / 500 s

CDS time interval = 1, 2, 3, 5, 7, 10, 15, 20, 30 μs

Extract noise parameters after CDS: Vrms and RTN Amplitude (VRTN)

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The characteristics of Vrms as a function of CDS interval are well fitted for two-state RTN cases by the following equation 1[9], which is a function of the time constants and VRTN.

For the sample D which shows multi-state RTN, its VRTN in CDS operation is determined by the direct transition between the most distant states. This cannot be characterized by taking into account the Vrms only. Consequently, for RTN with relatively long time constant as well as with multiple states, the VRTN should be taken into account together with the Vrms for characterization.

CONCLUSIONS The impact of RTN with various time constants and

number of states to noise characteristics of CIS were demonstrated in this work. It is suggested that from a trap located relatively away from the gate insulator/Si interface, the carrier is emitted to the FD node, which is to be mixed with signal photoelectrons. An evaluation of RTN using Vrms values tends to underestimate the effect of RTN with large amplitude and relatively long time constants or multiple states. It is proposed that the amplitude of noise should be incorporated for the evaluation of RTN. These findings are important for characterization and reduction of RTN. The effect of RTN in correlated multiple sampling will be studied based on the framework developed in this work.

REFERENCES [1] X. Wang, M F. Snoeji, P. R. Rao, A. Mierop, A. J.P

Theuwissen, “Random telegraph signal in CMOS image sensor pixels,” IEDM, Tech. Dig., pp.115-118, 2006.

[2] M-W. Seo, S. Kawahito, K. Kagawa, K. Yasutomi, “A 0.27e−rms Read Noise 220-μV/e− Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process,” IEEE EDL, Vol.36, No.12, pp.1344-1347, 2015.

[3] K. Abe, S. Sugawa, R. Kuroda, S. Watabe, N. Miyamoto, A. Teramoto, T. Ohmi, Y. Kamata, and K. Shibusawa, “Analysis of source follower random telegraph signal using nMOS and pMOS array TEG,” Proc. IISW, pp. 62-65, 2007.

[4] A. Teramoto, F. Fujisawa, K. Abe, S. Sugawa and T. Ohmi, “Statistical Evaluation for Trap Energy Level of RTS Characteristics,” Symp. VLSI Technology, Dig. Tech. Papers, pp.99-100, 2010.

[5] Y. Yonezawa, A. Teramoto, T. Obara, R. Kuroda, S. Sugawa, T. Ohmi, “The Study of Time Constant Analysis in Random Telegraph Noise at the Subthreshold Voltage Region,” Proc. Intl. Reliability Phys. Symp., XT.11.1-6, 2013.

[6] T. Obara, A. Yonezawa, A. Teramoto, R. Kuroda, S. Sugawa, T. Ohmi, “Extraction of time constants ratio over nine orders of magnitude for understanding random telegraph noise in metal-oxide-semiconductor field-effect transistors,” Jpn. J. Appl. Physics, Vol.53, pp.04EC19-1-7, 2014.

[7] T. Obara, A. Teramoto, A. Yonezawa, R. Kuroda, S. Sugawa and T. Ohmi, “Analyzing Correlation between Multiple Traps in RTN Characteristics,” Proc. Intl. Reliability Phys. Symp., 4A.6.1-4A.6.7, 2014.

[8] R. Kuroda, A. Teramoto and S. Sugawa, “Rondom Telegraph Noise Measurement and Analysis based on Arrayed Test Circuit toward High S/N CMOS Image Sensors,” Proc. Intl. Conf. Microelectronic Test Structures, pp.46-51, 2016.

[9] C. Y-P. Chao, H. TU, T. Wu, K-Y. Chou, S-F. Yeh, F-L. Hsueh, “CMOS Image Sensor Random Telegraph Noise Time Constant Extraction From Correlated To Uncorrelated Double Sampling,” J. Electron Device Society, Vol.5, No.1 pp.79-89, 2017.

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(a) (b) (c) (d)Fig. 7 (a) <c> and (b-c) <e> as functions of VGS. <c> for all the extracted MOSFETs follow the same dependency on VGS, i.e., <c> decreases exponentially as VGS increases. For <c>, three dependencies were observed; in (b) <c> increases, in (c) <c> does not change and in (d) <c> decreases as VGS increases, respectively.

Poly-Si gate (FD)

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Fig.9 Vrms extracted in CDS with 7sec interval and 10ms period as a function of Vrms extracted in continuous sampling for different CDS sampling numbers; (a) 100, (b) 1000, (c) 10000 and (d) 50000. Markers A~D indicate specific four MOSFETs.

Fig.10 VRTN extracted in CDS with 7sec interval and 10ms period as a function of VRTN extracted in continuous sampling for different CDS sampling numbers, (a) 100, (b) 1000, (c) 10000 and (d) 50000. Markers A~D indicates specific four MOSFETs. The VRTN in CDS increases as the sampling number increases and tends to reach the VRTN in continuous samping mode multiplied by squre root of two.

Fig.11 Waveforms and histogram in continuous sampling and CDS, and Vrms as functions of double sampling interval for samples A~D. Sample C exhibits a relatively long s, thus Vrms in CDS becomes relatively small. However, the VRTN is as large as that of continuous sampling mode times square root of two when signal transition occur during the CDS interval.

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0.5

1.0

1.5

2.0

2.5

3.0

Vrm

s [m

V]

Double sampling interval [sec]

Sample A Sample B Sample C Sample D

Con

tinuo

us

sam

plin

g w

avef

orm

CD

S w

avef

orm

(7s

ec in

terv

al)

Con

tinuo

ussa

mpl

ing

hist

ogra

m#

of s

ampl

ing:

108

CD

Shi

stog

ram

7

sec

inte

rval

# of

sam

plin

g: 5×

104

V rm

sve

rsus

CD

S in

terv

al#

of s

ampl

ing:

104

-12.0 -8.0 -4.0 0.0 4.0 8.0 12.0100

101

102

103

104

105

Freq

uenc

y

Output voltage [mV]

1192 1196 1200 1204 1208 1212104

105

106

107

108

109

1010

Freq

uenc

y

Output voltage [mV]

0.0 20.0 40.0 60.0 80.0 100.0-12.0

-8.0

-4.0

0.0

4.0

8.0

12.0VRTN=12.7mV, Vrms=1.58mV

Out

put v

olta

ge [m

V]

Sampling time [sec]

0.0 5.0 10.0 15.0 20.0

1192

1196

1200

1204

1208

1212 e=85s, c=8.0s, s=7.3s VRTN=10.1mV, Vrms=1.58mV

Out

put v

olta

ge [m

V]

Sampling time [msec]

0.0 20.0 40.0 60.0 80.0 100.0-12.0

-8.0

-4.0

0.0

4.0

8.0

12.0VRTN=17.3mV, Vrms=0.43mV

Out

put v

olta

ge [m

V]

Sampling time [sec]

1188 1192 1196 1200 1204 1208104

105

106

107

108

109

1010

Freq

uenc

y

Output voltage [mV]

-12.0 -8.0 -4.0 0.0 4.0 8.0 12.0100

101

102

103

104

105

Freq

uenc

y

Output voltage [mV]

0.0 5.0 10.0 15.0 20.0

1188

1192

1196

1200

1204

1208 e=53s, c=332s, s=45s, VRTN=9.65mV, Vrms=1.97mV

Out

put v

olta

ge [m

V]

Sampling time [msec]

0.0 20.0 40.0 60.0 80.0 100.0-12.0

-8.0

-4.0

0.0

4.0

8.0

12.0

VRTN=12.6mV, Vrms=0.88mV

Out

put v

olta

ge [m

V]

Sampling time [sec]

1188 1192 1196 1200 1204 1208104

105

106

107

108

109

1010

Freq

uenc

y

Output voltage [mV]

-12.0 -8.0 -4.0 0.0 4.0 8.0 12.0100

101

102

103

104

105

Freq

uenc

y

Output voltage [mV]

0 5 10 15 20 25 30 350.0

0.5

1.0

1.5

2.0

2.5

3.0

Vrm

s [m

V]

Double sampling interval [sec]

0.0 1.0 2.0 3.0 4.0 5.01188

1192

1196

1200

1204

1208

1212

VRTN=12.3mV, Vrms=1.88mV

Out

put v

olta

ge [m

V]

Sampling time [msec]

0.0 20.0 40.0 60.0 80.0 100.0-12.0

-8.0

-4.0

0.0

4.0

8.0

12.0VRTN=13.6mV, Vrms=1.55mV

Out

put v

olta

ge [m

V]

Sampling time [sec]

1188 1192 1196 1200 1204 1208 1212103

104

105

106

107

108

109

Freq

uenc

y

Output voltage [mV]

-12.0 -8.0 -4.0 0.0 4.0 8.0 12.010-1

100

101

102

103

104

105

Freq

uenc

y

Output voltage [mV]

0 5 10 15 20 25 30 350.0

0.5

1.0

1.5

2.0

2.5

3.0

Vrm

s [m

V]

Double sampling interval [sec]

Direct transition betw eenmost distant states

Due to direct transitions

Due to direct transitions

Eq.(1)

Four states RTN

− 46−