ijpam.eu Impact Of Via And Materials On Signal Integrity · Impact Of Via And Materials On Signal Integrity Biswa Ranjan Barik and A.Kalirasu Department of EEEM , AMET University,

Impact Of Via And Materials On Signal

Integrity

Biswa Ranjan Barik and A.Kalirasu

Department of EEEM, AMET University, Chennai, India

[email protected] and [email protected]

Abstract

Providing Signal integrity or signal quality at high

frequency is an important aspect in recent trends in

advanced packaging system where one bad bit

dramatically affects whole configuration. While

designing PCB different types of discontinuities come

into picture where designing of via which is normally

used as an interconnect between two different layers and

crosstalk which occurs due to coupling of energy from

one line to another when electromagnetic field of

different structures interacts are the major drawbacks for

providing signal integrity. In this project we have shown

the importance of via and its effect on signal integrity by

designing a four layer single via by using HFSS and also

try to show the impact of materials on cross-talk which is

one of the most discontinuities occurs while providing

signal integrity with the help of cross-talk calculator.

Key Words :- Signal integrity, VIA, Crosstalk,

Cross-talk calculator, HFSS

1.Introduction

Signal integrity is the process of assuring ultimate high fidelity to a

signal transmitted between a transmitter(driver) and receiver for

proper functioning of the circuit. A region of voltage where a digital

International Journal of Pure and Applied MathematicsVolume 114 No. 7 2017, 583-594ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

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receiver distinguish between a high voltage Vih and low voltage Vil

is known as threshold region below and above which the signal bits

can be received under all conditions. Hence to ensure signal integrity

the design engineer must guarantee that under any condition the

system must provide a high voltage that should not go above Vih and

should not go below Vil. With the continuous increase of operating

speed, frequency, and circuit density, as well as the decrease of circuit

dimension, system form factor, and logic level, it is increasingly

critical to ensure good SI design for high-speed digital circuits

[1].There are many critical aspect while providing signal integrity for

high speed digital design such as Signal propagating on transmission

lines (loss, terminations ,crosstalk etc),via, connector & package

modeling, non-ideal return paths, Power integrity etc.

As frequency increases and signal rise time reduces, via causes

impedance discontinuities resulting in signal reflections and hence

deterioration of signal integrity (SI) and system performance .Here

we have designed a “VIA” using HFSS and try to figure out its

reflection and transmission coefficient, Voltage standing wave Ratio,

Y-parameter etc .

Crosstalk will occur on the chip, PCB board, chip package, on

connector cables etc. As technology and customer demands push for

physically smaller and faster products, the amount of crosstalk in

digital systems is increasing dramatically. First, crosstalk will change

the performance of the transmission lines in a bus by modifying the

effective characteristic impedance and propagation velocity, which

will adversely affect system-level timings and the integrity of the

signal. Additionally, crosstalk will induce noise onto other lines,

which may further degrade the signal integrity and reduce noise

margins [2]. to more accurately detect crosstalk while designing of

PCB we have taken various materials having different permeability

values and putting the value in Crosstalk-calculator which is a free

CAD software available online .we have tabulated values and proved

that different materials with same configuration may provide different

cross-talk and signal integrity can improve by proper selection of

material.

International Journal of Pure and Applied Mathematics Special Issue

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we have organized our paper as follows. Section 2 Explains about the

Impact of VIA on signal integrity where we have shown how

capacitance and inductance affects on via design. Section 3 we have

designed and simulated a Four layer single via using HFSS and

explain its result output. Section 4 we tabulated crosstalk in PCB by

changing various materials permeability values and in section 5 we

conclude our paper followed by Reference.

2. Impact of Via on Signal Integrity

When we send any kind of signal from the silicon pad at the driver to

the silicon pad at receiver it will usually transverse through via and

connectors. A via is a hole drilled through PCB to connect

components to various traces and to make connection between various

layers, We can represent VIA also as a Vertical transmission- line It

consist of Pad, anti-pad and barrel. The barrel is a conductive material

that fills the hole to allow an electrical connection between layers, the

pad is used to connect the barrel to the component or trace and the

anti-pad is a clearance hole between the pad and the metal on a layer

to which no connection is required [2]. The most common type of via

is called “Through hole via”because it is made up of drilling through

the board ,Other types of via which are used in MCM(Multi Chip

Module) and PCB are Blind via,Buried Via,Micro via,etc

Fig:1 Equivalent circuit of Through Hole Via[2] Fig:2 Types of

Via Used in PCB Design[3]


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Here we can represent the via model as a simply PI network,where

capacitor represents the via pad capacitance on layer 1 and 2

respectively and the series inductance represents the barrel.The main

effect of capacitance is that it will slow down the signal edge after

several transitions.The relation between capacitance and Via can be

represented as[2]

Where εr is the relative permeability of material,D1 is the diameter of

via pad and D2 is the diameter of via antipad and T is the thickness of

PCB.

Via also add some amount of series inducatance which will degrade

signal integrity and also decreases the effect of decoupling capacitance

The relation between inductance and VIA can be represented as[2]

* (

) +

Where „h‟ is via height also known as its length and „d‟ is diameter of

barrel.Normally Via inductance affects more in providing signal

integrity than capacitance.

3.VIA Design Using HFSS

As our project is high frequency structure with multi conductor

transmission line ports which are driven by source, the solution type

taken as Driven Terminal, Unit as „inch‟ and grid size as 0.1

inch.Then draw VIA according to the position and size given in

Table-1and fix the to 0.7 and assign color on the design point of view

transperency. After completion of design you may face the problem

that two cylinders overlap each other and center at same location this

can cause design error hence to remove above drawback substract

Antivia 1 from FR4_1, FR4_2, FR4_3, GND_1, GND_2 and

Via1from Antivia1 using boolean operation and donot forgot to check

clone tools objects before subtracting. Similarly do boolean unite

operation to unite FR4_1, FR4_2, FR4_3 to


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Table 1:-Via Design Consideration

Antivia 1 and Trace1, Trace2 to Via1. To remove overlap error

between trace and air box subtract it by using boolean subtract

operation. Draw two ports by assigning above values given in table

and make it as wave port by using operation HFSS >Excitation

>Assign > Waveport. Finally select outerface of air1 and assign it as

radiation by using operation HFSS >Boundary>Assign> Radiation

.Finally add solution setup by using operation HFSS >Analysis Setup

>Add Solution Setup and assign maximum number of passes as 5,and

maximum delta S= 0.01 and add sweep type as Fast,and frequency

setup type as linear step,starting frequency as 1 Ghz and stop

frequency as 10 Ghz and sweep size as 0.5 Ghz.analyze all and

simulate design for getting results .

Draw Name Centre

position

Size Material

Box 1 FR4_1 (0,0,0) (2,2,0.005) FR4_Epoxy

Box 2 FR4_2 (0,0,0.0064) (2,2,0.047) FR4_Epoxy

Box 3 FR4_3 (0,0,0.0548) (2,2,0.005) FR4_Epoxy

Box 4 GND_1 (0,0,0.005) (2,2,0.0014) Copper

Box 5 GND_2 (0,0,0.0534) (2,2,0.0014) Copper

Box6 Trace1 (0,1,0.0598) (1.005,0.005,0.0014) Copper

Box7 Trace2 (0.995,1,0) (1.005,0.005,-0.0014) Copper

Cylinder1 Via1 (1,1.0025,0) Radius=12 mil,

Height=0.0598 in

Copper

Cylinder2 Anti

Via1

(1,1.0025,0) Radius=20 mil,

Height=0.0598 in

FR4_Epoxy

Box8 Air1 (0,0,0.0598) (2,2,1) air

Box9 Air2 (0,0,0) (2,2,-1) air

Rectangle1 Port 1 YZ-Plane (2,0.978,0.005),Y=0.05,Z

= -0.05

Copper

Rectangle1 Port 2 YZ-Plane (0,0.978,0.005),Y=0.05,Z

= 0.05

Copper


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Fig:3 Design of Via Using HFSS

Fig:4 Terminal S-parameter(S11,S12,S21,S22)

Fig:5 Terminal Y-Parameter

1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00Freq [GHz]

-22.50

-20.00

-17.50

-15.00

-12.50

-10.00

-7.50

-5.00

-2.50

0.00

Y1

HFSSDesign1XY Plot 1 ANSOFT

Curve Info

dB(St(Trace1_T1,Trace1_T1))Setup1 : Sw eep1




1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00Freq [GHz]

-45.00

-40.00

-35.00

-30.00

-25.00

-20.00

-15.00

-10.00

-5.00

Y1


Curve Info

dB20(Yt(Trace1_T1,Trace1_T1))Setup1 : Sw eep1




1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00Freq [GHz]

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

3.25

Y1


Curve Info

VSWRt(Trace1_T1)Setup1 : Sw eep1

VSWRt(Trace1_T2)Setup1 : Sw eep1


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Fig:6 Terminal VSWR

Table:2 Result output of S11,S12,S21,S22

4. CrossTalk

Cross talk is the main cause of signal integrity in IC design and

occurs due to mutual influence of two nearby parallel traces.One is

called agressor and other is called as victim. and victim influenced

due to coupling of capacitance, mutual impedance and also for non-

ideal gate operation . The impact of crosstalk-induced variations

depends on trace-to-trace spacing, dielectric constant, and cross-

sectional geometry and can be minimized by using proper wire

spacing and changing size of driver. The magnitude of noise due to

mutual inductance is

and due to capacitance is

.It is of two types, a portion of noise which

travel towards near end of the line called as near-end cross talk and

portion will travel towards far-end of the line known as far-end cross

talk. The design engineer should know that near end cross talk is

always positive where as far end cross talk is always negative

Freq [GHz]dB(St(Trace1_T1,Trace1_T1))Setup1 : Sw eep1




1 1.000000 -18.409484 -0.565598 -0.565598 -19.957189

2 1.500000 -15.260807 -1.024357 -1.024357 -16.773830

3 2.000000 -9.170205 -1.794675 -1.794675 -9.216167

4 2.500000 -9.287657 -1.913113 -1.913113 -8.919378

5 3.000000 -15.710723 -1.536930 -1.536930 -14.891437

6 3.500000 -10.217413 -2.042901 -2.042901 -11.576233

7 4.000000 -6.652311 -3.031598 -3.031598 -7.979918

8 4.500000 -7.026185 -3.310793 -3.310793 -9.098115

9 5.000000 -10.030367 -3.059377 -3.059377 -14.558510

10 5.500000 -15.140707 -2.896404 -2.896404 -20.165756

11 6.000000 -21.537333 -2.924329 -2.924329 -18.530721

12 6.500000 -11.338850 -3.428190 -3.428190 -12.984243

13 7.000000 -7.298418 -4.324201 -4.324201 -9.571688

14 7.500000 -6.614665 -4.863250 -4.863250 -9.714190

15 8.000000 -7.670507 -4.904312 -4.904312 -12.794800

16 8.500000 -9.665929 -4.763155 -4.763155 -17.821738

17 9.000000 -11.113898 -4.727642 -4.727642 -19.835736

18 9.500000 -8.323827 -5.344491 -5.344491 -12.767963

19 10.000000 -5.680781 -6.517817 -6.517817 -9.205930

HFSSDesign1Data Table 1 ANSOFTS-parameter


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Fig:7 Cross talk due to Lm and Cm[2]

Fig:8 Cross talk Equations[2]

A. Impact of materials on Crosstalk

Materials are also affecting crosstalk, and proper material selection

is a key factor for providing signal integrity. Hence to prove above

we have taken two PCB design i;e in Fig 9 where two traces are

equidistant from plane H1 = H2(H represents height of trace

from plane and taken to be 12 mils) and in Fig 10: traces are not

equidistant from plane i:e H1 > H2(Here H1=15mils,H2 =12 mils)

.We got all result by using Crosstalk- Calculator. Here it should be

noted that distance between two trace, rise time and parallel length

also affect signal integrity .Here we have taken rise time as 1.5 ns and

propagation delay as 0.165 ns and by putting above values we got that

any trace length more than 1.5 inch will be treated as transmission

line. Hence we have taken parallel length as 2 inch, and value of D

taken as 25 mils. By changing various values of permittivity we got

different cross talk values by fixing all other values constant.


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Fig:9 Traces are equal distance from plane

Fig:10 Traces are unequal distance from plane

B. Result Output

Table 3:Output Crosstalk for Design Fig:9

S.No Materials εr Crosstalk(db)

1 vacuum 1 -26.88149

2 Teflon 2.1 -25.24888

3 Taconic-Rf-35(tm) 3.5 -23.79133

4 Silicon_dioxide 4 -23.37021

5 glass 5.5 -22.3075

6 Rogers TMM 6 -22.00412

7 Rogers R03006 6.15 -21.91709

8 Silicon_Nitrate 7 -21.45437

9 Al_N 8.8 -20.61212

10 Alumina_92pct 9.2 -20.44524

11 ArlonAR1000(Tm) 10.2 -20.05409

12 silicon 11.9 -19.46065

13 Ferrite 12 -19.42815

14 Galium _Arsenide 12.9 -19.14605

S.No Materials εr Crosstalk(db)

1 vacuum 1 -25.43725

2 Teflon 2.1 -23.80465

3 Taconic-Rf-35(tm) 3.5 -22.34709


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Table4: Output cross talk for Design Fig:10

5.Conclusion

In our project we have shown that how Via effect on signal integrity

and also its design using Simulation software HFSS. From the result

output it is proved that the design can be considered in high frequency

application .Here the solution frequency taken as 10 Ghz and design

result shows that it is giving best output at 6 -Ghz. We also

experimented the Via by taking higher frequency of 20 Ghz and we

surprised that it is not only operating at this frequency also giving best

output at 17.4 Ghz. In our project we also try to show the impact of

materials on crosstalk and for two design is considered and result

output shows that more the permittivity more cross talk will be

generated, hence it is better to take less permittivity material in PCB

design to provide better signal integrity. And also from our result we

got that with the same material and configuration if two traces are not

equidistant from each other it will again add some more cross talk,

hence it better to take less variation between trace 1 to trace 2 and

more efficiently two traces equidistant from each other for providing

better signal integrity.

Reference

[1] Stephen H. Hall, Howard L. Heck ,Advanced signal integrity

for high-speed digital designs” A John Wiley & Sons, Inc.

Publication ISBN 978-0-470-19235-1 (cloth).

4 Silicon_dioxide 4 -21.92597

5 glass 5.5 -20.86326

6 Rogers TMM 6 -20.55988

7 Rogers R03006 6.15 -20.47285

8 Silicon_Nitrate 7 -20.01014

9 Al_N 8.8 -19.16788

10 Alumina_92pct 9.2 -19.001

11 ArlonAR1000(Tm) 10.2 -18.60985

12 silicon 11.9 -18.01641

13 Ferrite 12 -17.98391

14 Galium _Arsenide 12.9 -17.70181


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[2] Stephen H. Hall, Garrett W. Hall, James A. McCall, High-

speed digital system design: A handbook of interconnect theory

and design practices A John Wiley & Sons, Inc. Publication

ISBN 0-471-36090-2 (cloth).

[3] Weng Yew Chang, Richard, Kye Yak See, Eng Kee Chua,

Comprehensive Analysis of the Impact of Via Design On High-

Speed Signal Integrity,9th Electronics Packaging Technology

Conference 1-4244-1323-0/07/2007 IEEE.

[4] Sunghoon Chun , Yongjoon Kim, Taejin Kim and Sungho

Kang, A High-level Signal Integrity Fault Model and Test

Methodology for Long On-Chip Interconnections, 2009 27th

IEEE VLSI Test Symposium.

[5] Jun Fan, Senior, Xiaoning Ye, Jingook Kim,Bruce

Archambeault, and Antonio Orlandi, Signal Integrity Design for

High-Speed Digital Circuits: Progress and Directions, IEEE

Transactions On Electromagnetic Compatibility, Vol. 52, No. 2,

May 2010.

[6] Svetlana C. Sejas-Garcia1, Gerardo Romo, Reydezel

Torres-Torres Impact of the Configuration of Ground Vias

on the Performance of Vertical Transitions Used in Electronic

Packages2009,IEEE Mtt-S International Microwave Workshop

Series On Signal Integrity And High-Speed Interconnects

(Imws2009-R9).


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ijpam.eu Impact Of Via And Materials On Signal Integrity · Impact Of Via And Materials On Signal Integrity Biswa Ranjan Barik and A.Kalirasu Department of EEEM , AMET University,