Iftekharul Karim Bhuiya - DiVA portal

Design of a High Speed AGC Amplifier for Multi-level Coding Master thesis performed in Electronic Devices

by

Iftekharul Karim Bhuiya

LiTH-ISY-EX--06/3803--SE 2006-06-19

Design of a High Speed AGC Amplifier for Multi-level Coding

Master thesis in Electronic Devices at Linköping Institute of Technology

by


LiTH-ISY-EX--06/3803--SE

Supervisor : Andrea Plötz , Optical Communications Group, Fraunhofer Institute for Integrated Circuits, Erlangen , Germany

Examiner : Professor Christer Svensson

Linköping , Sweden June 19, 2006

Presentation Date

May 19, 2006Publishing Date (Electronic version)

June 19, 2006

Department and Division

Division of Electronic DevicesDepartment of Electrical Engineering

URL, Electronic Versionhttp://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6509

Publication Title

Design of a High Speed AGC Amplifier for Multi-level Coding

Author(s)


Abstract

This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a largeinput swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.

KeywordsBroadband amplifier, high speed amplifier , 4-PAM Signaling , multi-level signaling, AGC amplifier ,automatic gain control, shunt-shunt feedback, wideband amplifier

Language

X EnglishOther (specify below)

Number of Pages85

Type of Publication

Licentiate thesisDegree thesisThesis C-level

X Thesis D-levelReportOther (specify below)

ISBN (Master thesis)

ISRN: LiTH-ISY-EX--06/3803--SE

Title of series (Licentiate thesis)

Series number/ISSN (Licentiate thesis)

vi

Abstract

This thesis presents the design of a broadband and high speed dc-coupled AGC

amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It

is a high frequency analog design with several design challenges such as high -3 dB

bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large

input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant

differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed.

Moreover, the gain control circuit has been designed in analog domain. The amplifier

incorporates both active and passive feedback in shunt-shunt topology in order to

achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35

micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.

vii

Acknowledgments

In the very beginning I would like to thank Allah the Almighty for all his blessings

that helped me to sojourn along the trajectory of life so far. Then I would remember

my beloved mother who has encouraged me always to chase down the crown of

academic success.

I am grateful to my thesis examiner , Professor Christer Svensson to initiate the thesis

work with an interesting circuit. Besides , I would like to express my thanks to the

people at Fraunhofer IIS in Germany including my supervisor , Andrea Plötz and

other people with whom I had many invigorating discussions. Particularly I

remember Popken and Harald Nebauer for their attitude to share their wealth of

experience and insight with a new guy like me. Thank you all !

Iftekhar

Linköping , Sweden

[email protected]

vii

Concise Contents 1. Introduction . . . . . . 01

2. Specifications . . . . . . 09

3. System Architecture . . . . . 11

4. Wide-band VGA . . . . . 27

5. AGC in Analog Domain . . . 49

6. Impedance Matching Stages .. . 56

7. Chip Layout . . . . . . 61

8. Post Layout Simulation Results . . 66

9. Power Budget . . . . . . 68

10. Conclusion . . . . . . 69

11. Future Work . . . . . . 69

12. Appendix . . . . . . 70

13. References . . . . . . 73

viii

Contents in Detail 1. Introduction . . . . . . 01

1.1 Incentive . . . . . . 01

1.2 Multilevel Signaling . . . . 02

1.3 The Role of AGC Amplifier . . . 05

1.4 Limiting Amplifier vs AGC Amplifier . . 06

2. Specifications . . . . . . 092.1 Specification List . . . . . 09

2.2 Origin of the Specs . . . . . 09

3. System Architecture . . . . . 113.1 System-level Plan . . . . . 11

3.2 Key Design Challenges . . . . 12

3.2.1 Wide Bandwidth . . . . . 12

3.2.2 Wide Dynamic Range . . . . 13

3.2.3 Gain Variation . . . . . 13

3.2.4 AGC Circuit in Analog Domain . . . 14

3.2.5 Signal Delivery to Off-chip loads . . . 14

3.3 Exploring the Design Constraints . . 15

3.3.1 Fully Differential Signal Path . . . 15

3.3.2 High ft Transistor for High BW . . . 16

3.3.3 BW Shrinkage . . . . . 18

3.3.4 Avoid BW Bottleneck . . . . 20

ix

3.3.5 Low Zout complicates the design . . 20

3.3.6 DC Coupling of Cascaded Stages . . . 22

3.3.7 Larger Device for Low Mismatch . . . 23

3.3.8 Inductor-less Circuit . . . . 24

3.3.9 Low Impedance Nodes in Signal Path . . 25

4. Wide-band VGA . . . . . 274.1 VGA Features . . . . . 27

4.2 VGA Design Constraints . . . . 30

4.3 Exploring VGA Topology . . . . 31

4.3.1 VGA with Source-degenerated Resistor . 32

4.3.2 VGA with Current Injection . . 34

4.3.3 Gilbert Cell . . . . 36

4.3.4 Gilbert Cell with Cherry-Hooper Load . . 37

4.3.4.1 Cherry-Hooper Amplifier . . . . 38

4.3.5 Cherry-Hooper VGA . . . . 43

4.3.6 CH VGA with Parallel Feedback . . 45

4.3.7 Orthogonally Biased CH VGA . . 46

4.3.7.1 Practical Issues . . . . 47

5. AGC in Analog Domain . . . . 495.1 AGC Architecture . . . . . 49

5.2 Gain Control Amplifiers . . . . 51

x

5.3 How to Generate Vc ? . . . . 53

5.4 Peak Detector . . . . . 55

6. Impedance Matching Stages . . . 566.1 Output Matching Stages . . . . 56

6.1.1 Output Buffer . . . . . 57

6.1.2 Wide-band Predriver . . . . 58

6.2 Input Matching Stage . . . . 59

7. Chip Layout . . . . . . 617.1 Layout Issues . . . . . . 61

7.2 Full Chip Layout . . . . . 61

7.3 Block-level Layout . . . . . 63

8. Post Layout Simulation Results . . 66

9. Power Budget . . . . . . 68

10. Conclusion . . . . . . 69

11. Future Work . . . . . . 69

12. Appendix . . . . . . 7012.1 The Ringing of the Source Follower . . . 70

13. References . . . . . . 73

xi

AbbreviationsAGC Automatic Gain Control

VGA Variable Gain Amplifier

ISI Inter-symbol Interference

TIA Trans-impedance amplifier

SNR Signal to Noise Ratio

PAM Pulse Amplitude Modulation

CH Cherry-Hooper

CDR Clock and Data Recovery

BW -3 dB Bandwidth

CS Common Source

1. Introduction 1

1. Introduction 1.1 Incentive

Computer revolution has brought many changes in the society. Nowadays computer networks can

be seen not only in offices and labs but also in homes. People are also using the computer for a variety

of purposes ranging from computation intensive simulation to typing , playing and other entertainment.

As a result , more and more networks will emerge. Consequently a good market exists for low cost high

speed serial data communication link for short distances ranging from 1 meter to 10 m such as

computer to computer and computer to peripheral objects including printers, video cameras ,laptops ,

MP3 players etc.

Figure 1.1 : A Typical Computer Network

In such a short distance , communication links can be implemented in a number of ways as illustrated

in Figure 1.2 [1] . Traditionally parallel bus consisting of many wires have been used. But this solution

Figure 1.2 : A Typical Computer Network

1. Introduction 2

is expensive and power hungry. Normal optical fiber which is quite good for long distance

communication link is costly and area-inefficient for this short distance. Polymer optical fiber (P.O.F)

or copper cable is a better solution for these short range data links.

1.2 Multilevel Signaling Usually a low cost cable has a low -3dB BW. But for high speed data transfer , the cable should

have high – 3 dB BW , but such cables are expensive. How to solve that problem ? Well , one solution

is that we still want to use low BW cable , but more amount of data will be sent at the same time.

How ?

To get the answer to this big question, we should look into Nature. If we see the genetic code

in D.N.A as illustrated in Figure 1.3 [2] , it is not binary coding , rather it has four letters. So , each

letter can represent two bit values. In other words , using the same amount of molecules , 4-letter

Figure 1.3 : The D.N.A Structure

coding will pack twice the information than the binary coding. An analogous example is a multi-

storied building where using the same land , more people can be accommodated compared to a single

storied people. So , instead of sending only two signal levels (high and low ) through the channel

, we can send more levels where each level will represent more bits as illustrated in Figure 1.4 [3].

1. Introduction 3

Figure 1.4 : Eye Diagrams for Binary and multilevel Signaling

Then comes the question of how many levels ? 3 or 4 or 8 or more ? We need to consider

several factors here. If the levels are more , the spacing between the adjacent levels will be less. And

less spacing means more susceptibility to the noise and ISI . Moreover , the resolution of the receiver

has to be very high. Well, this limited receiver resolution might be circumvented if the spacing is made

larger by using the large swing at the transmitter end. But , for maintaining the same spacing, more

levels mean larger swing at the transmitter end. However, the transmitter has also limited output swing.

Thinking all these factors 4-PAM is an optimum choice. Here PAM means pulse amplitude

modulation. One important advantage of this modulation scheme compared to the frequency

modulation is that transmitter and receiver architectures are easier to design. Besides , in this wire-

line communication , noise is not as high as in wireless channel. So , PAM is quite suitable for this

wire-line channel.

However , 4-PAM is not a free lunch. It also has some disadvantages as follows.

1. Timing loss : Rise and fall time between different levels are not equal at all. So , major

transitions takes more time compared to minor transitions as shown in Figure 1.5 [3].

1. Introduction 4

Figure 1.5 : Signal Transitions in 4-PAM Signaling

2. Reflection : A large reflection can easily engulf or corrupt the next low level symbol.

3. Crosstalk : If several parallel wires carry 4-PAM signals , then crosstalk may corrupt the

signal levels easily.

However , these problems can be solved to a great extent if we eliminate major transitions and also use

gray coding. This scheme is called full swing eliminated coding as illustrated in Figure 1.6 [3].

Figure 1.6 : Major and Minor Signal Transitions in 4-PAM Signaling

1. Introduction 5

1.3 The Role of AGC Amplifier

A typical optical fiber transceiver as illustrated in Figure 1.7 [4] has a TIA that does not

receive constant signal swing from the fiber optic channel. Because , the length of the channel can vary

a lot. Besides , the quality of the channel also vary. As a result , the TIA needs a AGC circuit to provide

constant output swing which is, however, not large enough for the decoding by the CDR chip. Hence ,

an amplifier caller limiting amplifier or limiter is interposed between the TIA and CDR chips. This

limiter , a stand alone chip in most of the cases , amplify the TIA output swing to a constant logical

swing. The AGC amplifier can be a good substitute for these limiter and AGC module. In industry ,

this AGC amplifier is also called optical post amplifier.

Figure 1.7 : A Typical Fiber Optic Transceiver

1. Introduction 6

Apart from the fiber optic transceiver, the transceiver for the twisted pair line as illustrated in

Figure 1.8 [ 1 ] , also needs this AGC amplifier. In this context , the “ receive amplifier” can be

replaced by the AGC amplifier.

Figure 1.8 : A Typical Twisted Pair Line Transceiver

1.4 Limiting Amplifier vs AGC Amplifier

Most of the papers in the literature deal with limiting amplifiers. And those designs

have many tricks. In order to apply those tricks in the context of the AGC amplifier, we need to

understand deeply the difference between the limiting amplifier and the AGC amplifier.

The limiter has a fixed gain voltage transfer curve which also has a limiting region. It is

also simpler to design. However , the AGC amplifier always operate in the linear region whereas the

limiting amplifier saturates when the input signal swing is high as shown in Figure 1.9 [5].

1. Introduction 7

Figure 1.9 : Voltage Transfer Curves for the AGC amplifier and the limiting Amplifier

Moreover , from the perspective of the noise and random jitter , the AGC amplifier is better [5].

While the input signal is binary also called 2-PAM , the output signal swing of a limiting amplifier is

fully digital swing as illustrated in Figure 1.10. Now, if the input signal swing is 4-PAM signal, then

Figure 1.10 : The Eye Diagram for the Binary Signaling

1. Introduction 8

the limiter will not amplify each symbol level equally. As a result , each eye of the output signal swing

will not be equal to each other as illustrated in Figure 1.11. This fact will make the signal detection and

decoding difficult for the subsequent CDR chip

.

Figure 1.11 : The Asymmetric Eye Diagram for the PAM-4 Signaling

2. Specifications 9

2. Specifications2.1 Specification List

The specifications of the chip are listed below.

Input Swing range : 120 mVp-p ~ 1800 mVp-p ( differential )Output Voltage Swing : 1800 mVp-p (differential )Small Signal Gain : 0 dB ~ 23.522 dBInput Symbol Rate : 1 Gsym /s ( 2 Gbps )Input Impedance : 50 ohms ( Single – ended )Output Impedance : 50 ohms ( Single – ended ) -3 dB Bandwidth : more than 500 MHz , close to 1GHz Low Frequency Cut-off : DC ( fully dc-coupled ) Supply Voltage : 3.3 VPower Consumption : Relaxed. Technology : 0.35 micron CMOSPortability : should be portable to 0.18 micron or lower geometry process.Linearity : High , eyes should have equal heights.

2.2 Origin of the Specs : For choosing the lower bound of the input dynamic range , the real world facts

have been taken into consideration. Input signal has four levels with equal spacing. Minimum

spacing should not be less than 20 mV in single ended case in order to make signal generation and

measurement easier. Hence single ended minimum input swing is 60 mVp-p while differential

input swing is twice , that is, 120 mVp-p. However, the offset cancellation circuit is not needed due

to such limit.

For choosing the output swing,we should consider that single ended binary signal

swing should be at least 200 mVp-p for detection by the receiver down the signal chain. So ,

minimum eye height for binary signal swing is 400 mVp-p diff. However , in 4-PAM should be

three times as it has three eyes. But for easy detection by the next stage CDR circuit , the higher

eye-height is better. So, instead of 1200 mVp-p , 1800 mVp-p is chosen.

2. Specifications 10

Typically ,the VGA gain should be 0 dB while the input signal is maximum. So, the upper

bound of the input dynamic range is chosen as 1800 mVp-p equal to output differential swing.

The AGC amplifier is a stand-alone chip. It has to be tested after fabrication. Hence for interfacing

with the 50 ohm probes the input and output impedances of the chip should be 50 ohms.

Regarding the -3dB bandwidth, we should consider the high speed input signal as a Fourier

series. The amplifer output should contain , atleast ,the fundamental frequency. For a symbol rate

of 1 Gsym/s , the symbol period of the input PRBS signal is 1000 ps. For the fastest transition in

PRBS case ,that is, 010101 ..sequence , the fundamental frequency component has a period of 2000

ps , that is , the -3 dB BW is greater than or equal to 0.5 GHz. However , for less intersymbol

interference which is more acute in multi-level signalling , the BW should be close to the symbol

rate , that is , 1GHz. This also helps to compensate the BW shrinkage due to cascading with a TIA.

Regarding the low frequency corner of the BW ,we should consider that the incoming

random data might have long sequence of zeros or ones, Such data has very low frequency

components close to DC. So, the low frequency corner of the chip is set to zero. If the offset

cancellation circuit were present , then this limit would be somewhat higher.

Concerning the power consumption , the wireline transceiver in the high speed datacom link

is not a portable stuff. So no worry for the battery cost. Hence , some relaxed limit can be imposed

for power consumption.

Regarding the linearity , the CDR circuit down the signal chain prefer incoming signals with

symmetric eyes. Because, the decision thresholds can be placed in the middle of the eyes and

detection circuit can be designed easily. As shown in the Figure 2 , the unequal spacing in the eyes

of the output signal of AGC amplifier due to non-linearity makes the CDR circuit difficult to

design.

3. System Architecture 11

Figure 2 : Effect of Non-linearity in the Eye Diagram

While choosing the process technology , the fabrication cost has been considered.

Nowadays , the 0.35 micron CMOS process is quite cheap. So , the chip should be fabricated first in

a cheap process and then tested . If the post-fabrication result is quite OK , then 0.18 micron or

more expensive process should be considered. To make this easier , the design of the circuit should

be portable to the low Vdd process.

Some other specifications related to jitter , noise figure and group delay [22] are ignored

here as the client, Fraunhofer IIS , was more interested in AGC and the linearity or symmetry of

the output eyes.

3. System Architecture

3.1 System-level Plan The architecture of the chip can be portrayed in Figure 3.1 in the beginning. The

high speed input signal will be received by an input stage with proper impedance matching. Then

the signal will be channeled into a variable gain amplifier (VGA) which will generate constant

output swing that will be detected by an automatic gain control (AGC) circuit which will generate

gain control signals for the VGA.


After the VGA comes a buffer stage which will drive the VGA output signal over

the parasitic-infested path towards the 50 ohms off-chip loads.

Figure 3.1 : System Architecture of the AGC Amplifier IC

3.2 Key Design Challenges In order to implement the above system architecture in silicon a good

number of challenges have been encountered. Among those challenges, the important ones are

listed below.

1. Wide bandwidth

2. Wide Dynamic Range

3. Gain variation with high linearity and sufficient BW

4. AGC circuit in analog domain

5. Delivering high frequency analog signal to 50 ohm off-chip loads.

3.2.1 Wide bandwidth High speed signal path through the input stage, VGA and buffer must have broad

bandwidth so that high frequency harmonics of the input signal can reach the output loads. But

parasitics make it difficult to maintain large BW. However, the signal path through the AGC circuit

should have low BW so that noise can not cause instability.


3.2.2 Wide Dynamic Range

Maximum input signal swing is 1.8 Vpp (diff.) , that is , 900 mVp-p (single-ended ).

Maximum output signal swing is 1800 mVp-p (diff.). This is quite high compared to 3.3V power

supply. To accommodate such a large dynamic range in the high speed signal path with only 3.3 V

Vdd is quite challenging , since the transistors run into the non-saturation region when signal swing

goes higher.

3.2.3 Gain Variation

Ideally, the voltage transfer curve of the VGA should always be linear for any gain

control voltage as shown in Figure 3.2 . But , while varying the gain of the VGA , the linearity of

the voltage transfer curve is not always maintained. For some control voltages, non-linearity pops

up in the transfer curve. Then the output swing range decreases.

Figure 3.2 : Ideal Voltage Transfer Curves of the VGA

It is quite challenging to maintain sufficient linear region in the transfer curve while

changing the gain of the VGA. The same is also applied for BW as shown in Figure 3.3. As the

gain increases, BW decreases and vice versa due to the constant gain-bandwidth product. But ,

even for the maximum gain , minimum BW should be greater than 500 MHz .


Figure 3.3 : Gain vs Frequency Curves of the VGA

3.2.4 AGC circuit in analog domain

Gain control can be done in two ways. Digital or Analog . But digital implementation

requires a processor or some other control logic with weights stored in a memory. A separate chip

then might be needed. If implemented on the same chip , then all those pathological issues related

to mixed signal chip will come up. Hence , analog version of gain control is much more economical

and elegant. But, this requires design tricks that are not so cheap !

3.2.5 Signal Delivery to Off-chip loads

While traveling towards the off-chip loads , analog signal encounters a lot of parasitic

capacitance which are killer particularly for high frequency harmonics. One solution is to make the

output node as low impedance node. However , then the gain of the preceding stage decreases

drastically. Hence, it is quite challenging to deliver the high frequency analog signals to low off-

chip loads over the parasitics-laden path.

All the above challenges are in some ways correlated. So , one cannot isolate one challenge

from the rest of the others. In other words , the circuit needs to be optimized while giving attention

to all those challenges simultaneously. The following Figure 3.4 illustrates this web of analog

delight or pain !


Figure 3.4 : The Web of Analog Design

In order to avoid design iterations and achieve first-pass success , it would be wise to understand

all the design constraints that originate due to this polygon-dilemma . So , we should first explore

the design constraints before jumping into the design of each building block.

3.3 Exploring the Design Constraints

3.3.1. Fully differential signal path The high speed signal path should be fully differential , because it provides the following benefits.

1. It doubles the output swing compared to the single ended version. This is quite advantageous

particularly when supply voltage is low.

2.. Good linearity, cancellation of even order non-linearity in differential output due to the odd-

symmetric transfer curve [6] . However, the single ended output has even order harmonics. The

following Figure 3.5 illustrates this idea.

Single ended swing Differential Swing

Figure 3.5 : The Voltage Transfer Curves of the Differential Amplifier


3. Good power supply rejection ratio ( PSRR ) , at high freq. active power supply rejection is not

possible.

4. Source Followers can not be used. Because, threshold voltage is in the signal path. So voltage

headroom available for signal swing is reduced.

3.3.2 High ft

Transistor for High BW

The transistors in the high speed signal path should have high transit frequency (ft) in order

to maintain high BW. Usually ft is defined as the frequency for which current gain is unity. It is

equal to the ratio of transconductance to gate capacitance as shown below.

Here , gate capacitance actually includes gate to channel capacitance and overlap capacitance as

shown in Figure 3.6 [7] . Physically ft implies the high frequency behavior of the transistor. For

allowing high frequency harmonics of the input signal pass through the transistor , voltage across

the gate to source should change rapidly. When charge is being accumulated on the gate plate

( positive node ), the bottom plate of the gate capacitance gets negative charge fast due to high gm.

As a result , high freq voltage can build up across the gate to source node of the transistor. So , the

Figure 3.6 : The Parasitics of an NMOS Transistor

higher the ft , the larger the BW of the circuit. In order to get high ft transistor , current density of

the transistor as shown in the following equation need to be maximized [7]. Besides , minimum

channel length device should be used so that device parasitics remain small.


The ft of the transistor is also affected by input common mode voltage. As shown in the following

equation , gm is related to dc voltage of gate to source nodes. Hence , all the transistors in the high

speed path need to be biased with high common mode voltage. However , the input output swing

range should also be considered.

In case of differential amplifiers, one nice and tricky way to get high ft transistor is to increase

gm by using high bias current Iss instead of increasing width and the device parasitics of the

input transistor as illustrated below.. However , the disadvantage is high power consumption.

Figure 3.7 : The Input Transistors of a Differential Pair

Another important issue is the load of this differential amplifier. This load should be resistive

instead of pMOS, because pMOS has lower carrier mobility and hence for the same gm of NMOS

transistor, pMOS has to be much wider .So more device parasitics and hence lower ft.


3.3.3 BW Shrinkage

When several amplifiers are cascaded , total bandwidth gets lower than the cell bandwidth.

This is because , as illustrated in Figure 3.8 [7], the gain transfer function of each stage is low

pass filter type.

Figure 3.8 : Cascaded Amplifiers with Transfer Functions

The total gain of the cascade can be expressed in the following equation.

If the system BW is w1 , then we can express it in terms of cell bandwidth as shown

subsequently.


So as the number of stages increases , the total BW shrinks more but weakly due to presence of

the square root relation. The following Figure 3.9 [7] illustrates this fact. However , total gain An

increases rapidly. As a result , overall gain-bandwidth product increases.

Figure 3.9 : Transfer Functions of a cascaded amplifier with different no. of stages In the above analysis , each stage of the cascade is a simple first order stage. For any type of

order , the generalized relation between system BW and cell-BW can be represented by the

following equation. Here , m is related to order. For a 2nd order stage , m is equal to 4.


According to this equation , BW shrinkage is less for high order stages. So , the more poles each

stage has , the better system-BW is. This is a guiding factor while choosing the right topology of

each building block of the AGC amplifier in the high speed path. However , one important issue is

missing here. This equation does not capture the loading effect of the succeeding stage on its

preceding stage. So, in reality BW shrinkage is higher [8].

3.3.4 Avoid BW bottleneck

The low BW of the upstream cell will cancel the benefits of high BW cell down the

chain because the high frequency harmonics of the random data will be blocked or attenuated by

the upstream cell . So, proper care should be given to the BW of all the building blocks in the high

speed path. In this context, the input capacitance of the chip is quite important. This capacitance

should be low [8]. Because , in the receiver of the high speed data link TIA precedes AGC

amplifier. Since cascading inevitably degrades the system BW, the loading effect of the AGC

amplifier will exacerbate the situation. To get low Cin , high speed input pad with low capacitance

should be used.

3.3.5 Low Zout complicates the design

The output signal of the VGA is analog, not digital. So , the output buffer cannot be a

current switch or CML buffer. The output swing of the buffer depends on the load impedance

and bias current. Since, output load impedance is only 50 ohms which is quite low , high bias

current is needed to maintain 1.8 Vp-p output swing which is quite large. To accommodate large

bias current , the input transistors of the output buffer as illustrated in Figure 3.10 have to be quite

big. But big size brings large capacitance that will load the preceding VGA greatly.


Figure 3.10 : Initial System Architecture of the AGC Amplifier IC

The situation gets worse as the BW of the VGA is variable. VGA is not suitable and

strong enough to drive the output buffer. A fixed gain stage is in a better position to tolerate the

huge capacitive loading of the output buffer. Moreover, it is easier to design. As a result , we need

to interpose another stage between the output buffer and the VGA as illustrated in Figure 3.11.

Called “ Predriver ” , this stage will provide less capacitance to the preceding VGA.

Figure 3.11 : Final System Architecture of the AGC Amplifier IC

However , the addition of this extra stage is not a free lunch. The total system BW will be

degraded as more BW shrinkage arises due to the extra stage. This entails less freedom on the

VGA architecture. Because , VGA itself is not a single-stage amplifier. It should be composed of

several low gain stages. However , this number of VGA cells cannot be high as more stage means

more BW shrinkage as well as low SNR [10].


3.3.6 DC coupling of cascaded stages Input signal is random by nature. So , it might have long sequence of the same symbol level

as illustrated below.

Figure 3.12 : Waveform of PAM-4 Signaling

As a result , its spectrum has substantial amount of dc and low frequency contents which

will be blocked if on-chip ac-coupling capacitor is small. So , the capacitor should be prohibitively

big, The better solution is to use dc coupling for the cascaded stages. This choice requires the

input and output common mode levels to be equal. This condition influences the topology search of

the VGA and other building blocks in the high speed signal path. Particularly for VGA , it is quite

important as can be seen in the VGA chapter later. For dc coupling of the same VGA cells , the

transistors in the interface as illustrated in Figure 3.13 should be biased in such a way that they

always remain in the proper region of interest ( saturation region ) . In order to ensure this , cell bias

current should be kept constant while changing gain of the VGA.

Figure 3.13 : DC Coupling in Cascaded stages


The dc bias levels that have been used in the final chip design are shown in Figure 3.14. Those

values have to be considered carefully while keeping in mind how to get high ft transistors as well

as wide dynamic range with respect to low Vdd.

Figure 3.14 : Common Mode levels in Cascaded Stages

3.3.7. Large Device for Low Mismatch

Analog design is very much entangled with layout issues because the transistor understands

pure Newtonian physics , not the circuit designer's mind. So , layout issues are quite important.

To get proper performance from the differential architecture , symmetry should be maintained in

both branches. This symmetry is very much desired to get high linearity in the voltage transfer

curve. In order to get symmetry, mismatch between the two branches has to be reduced as much as

possible. This mismatch as shown in the following equations [7] are dependent on the device size.

So , while designing the circuit , we should use large transistors and resistors.


For good matching between a pair of circuit components , interdigitation and common centroid

techniques are used as illustrated in Figure 3.15 collected from Internet. Large device size is helpful

to do this. But large device is accompanied by large parasitics which degrades BW. So a trade-off

is needed.

Figure 3.15 : Layout of Current Mirror

Another issue is location. The Elements to be matched should be placed close together in the

layout. This requires some extra attention to choose the right topology. Not all topologies are

suitable for these conditions.

3.3.8 Inductor less Circuit

In high speed design usually inductors are used to enhance the BW of the circuit. Typically

inductors helps to speed up the charging of the load capacitance by causing delay or inertia in the

variation of current through the load as illustrated in Figure 3.16 [7].


Figure 3.16 : Shunt Peaked Amplifier

However , from the beginning it was decided not to use any inductor in the design because models

available for inductors are not good in quality. As a result , other type of BW enhancement

techniques have to be explored while designing the building blocks in the high speed signal path.

3.3.9 Low Impedance Nodes in Signal Path

In a cascade of stages each node in the interface between two adjacent stages

contribute a pole whose magnitude depends on the resistance and capacitance associated with that

node. For high BW , we need high frequency poles for which large pole capacitance must be

accompanied by low pole resistance. So we need low ohmic nodes. For achieving this , output

resistance of the preceding stage should have much mismatch with respect to the input resistance of

the succeeding stage. Called ' strong impedance mismatch ' [12] , this trick is better illustrated in

the Figure 3.17.


Figure 3.17 : Strong Impedance Mismatch

There are several ways to implement such strong mismatch. For a stage with high Zin and

low Zout , a source follower can be used. For a stage with high Zin and high Zout,a

transconductance stage is suitable. For a stage with low Zin and Zout , a transimpedance stage can

be used.

4. Wide-band VGA 27

4. Wide-band VGA

4.1 VGA Features

A VGA is a special type of amplifier whose gain can be changed by applying a gain

control voltage. Its typical voltage transfer curves [12] are shown in Figure 4.1 . The amplifier

enters into the limiting region when input swing is equal or greater than 1-dB compression point.

Figure 4.1 : Voltage Transfer Curves of a VGA

As shown in the above picture, VGA amplifies the low input swing signal and attenuates the

high swing signals. Its small signal gain can be controlled by changing either transconductance

or output resistance since gain is dependent on these two parameters as shown in the following

equation.

But , to change gm , bias current should be changed since ,as shown in the following

equation, width or length of the transistor should not be changed.

outRmgoAv =

4. Wide-band VGA 28

But the change in bias current also causes change in the input swing range of VGA if VGA has a

differential architecture as implied in the following equation.

This is quite important since when input signal swing is high , gain should be lowered. Then if gain

is lowered by decreasing gm, that is , by decreasing bias current ,then input swing range will

degrade. This degradation will add non-linearity in the output signal if input signal swing is quite

high.

A change in gm will also cause variation in the BW of the VGA as ft is related to gm as shown in

the following equation.

For high gm , parasitics of the transistor will increase , then BW will degrade. So , to some extent ,

the product of gain and BW remain constant. In other words , we need to trade gain for BW and

vice versa. However , this is not the whole story. From other perspective ,we can say that BW

trades with delay [20]. This trade-off is usually observed in the distributed amplifier and those

topologies where inductors are used . However , in VGA design , the concept of constant gain-BW

product is enough.

DIL

WoxCnmg

= µ2

( )LW

oxCn

Iss

ppswingdvµ

*2*2_ =−

4. Wide-band VGA 29

Some typical gain vs frequency curves for a VGA are shown below. Care should be taken

while designing the VGA so that the BW does not fall below the minimum required BW.

Figure 4.2 : Voltage Transfer Curves of a VGA

Apart from changing the gain by varying gm , output impedance can also be changed. However ,

then the output pole position will be affected as shown in the following equation.

So, again comes the constancy of the gain-BW product !

In order to change the resistance , the target resistor should be placed in parallel with a

pMOS or nMOS as illustrated in the following figure. This transistor should be biased in triode

region. However , if it moves into other regions such as sub-threshold or saturation region , non-

linearity appears in the output signals.

Figure 4.3 : Variable Resistor

outCoutRout1=ω

4. Wide-band VGA 30

4.2 VGA Design Constraints In a previous chapter we have explored the design constraints that are related to each

high speed building block of the AGC amplifier. Now we are going to discuss some design

constraints that are specific to the wideband VGA. This type of VGA must provide constant

output swing for all type of input swings as illustrated in Figure 4.3(a). However a typical VGA

has low output swing when input swing is high as shown in Figure 4.3(b).

(a) ( b ) Figure 4.3 : Transfer Curves for a (a) typical VGA , (b) ideal VGA

To circumvent this problem , a cascade of VGA cells with different gains can be used. All

the VGA cells will be controlled in such a way that output swing is held constant at the tail-end of

the cascade as shown below.

Figure 4.4 : VGA Cascade

4. Wide-band VGA 31

In this VGA cascade , maximum allowable gain in each VGA cell has to be low , because

high gain means low BW that might cause BW bottleneck. We need to do gain-BW trade-off

here. Besides, each VGA cell should be suitable for broadband cascading . In other words , nodes

in the interfaces should be low ohmic.

Another important design issue is the relation between small signal gain variation and large

signal properties. Ideally, small signal gain variation should not influence the dc bias level and other

large signal properties of the circuit. This type of relation may be called orthogonal since small

signal current and bias current as illustrated below may be viewed as two vectors who are

perpendicular or orthogonal to each other.

Figure 4.5 : Orthogonal Biasing

4.3 Exploring VGA Topology VGAs are widely used in many applications such as in cell-phone receivers where

received signal strength vary due to the change in distance from the base station. But the VGA in

RF domain is usually of narrowband whereas VGA in high speed serial data communication is

wideband. In hearing aid VGAs are also used. But those are tailored to low frequency operation.

However, we need to survey the existing VGAs in order to get some ideas that might

be helpful to design our required VGA. Let's explore this exciting world of VGAs.

4. Wide-band VGA 32

4.3.1 VGA with Source-degenerated Resistor

The following circuit [13] as shown in Figure 4.5 can be used as a VGA if R1 is converted

into a variable resistor as implied in the gain equation. This architecture can provide excellent

linearity if R1 is relatively much larger than (1/ gm). This can be done in two ways- either

Figure 4.6 : VGA with source degeneration

R1 or gm has to be quite big. However, in order to provide high gm, a CMOS transistor has

to be quite large in size compared to the BJT transistor [17] . So arises large parasitic capacitance

that degrades BW. In order to avoid BW degradation , we need to make R1 quite large. But , the

bias current flows through R1. And since R1 is a linear resistor , it will take a large voltage

headroom. As a result , output swing will decrease.

Moreover , if the value of R1 is changed, dc bias levels of the circuit will also change since

the bias current flows via R1 . So we can say that the circuit cannot be biased orthogonally.

The output node of this circuit is a high impedance node as R2 which can not be low for high

gain ) is in parallel with the rds of the CMOS transistor which is quite high. The input node is

also a high impedance node since Rin of the CMOS transistor tends to be infinite in the low

frequency domain. As a result , if this circuit is cascaded with the same cell , then the interface

node will not be low ohmic. So , the BW of the cascade will be degraded a lot.

mgRRAvo 1

1

2

+=

4. Wide-band VGA 33

The problem of orthogonal biasing can be solved if the current source is split into two current

sources with equal current rating as shown in the following circuit [13] ! The circuit should be

biased in such a way that no dc current should flow via R1 pairs. But the output node is still

Figure 4.7 : Orthogonally biased VGA with source degeneration

high impedance node ! How to solve it ?

Well , some analog gurus at Cornell university [5 ] have solved this problem using shunt

shunt feedback locally as shown in the following circuit.

Figure 4.8 : Orthogonally biased VGA with source degeneration and shunt-shunt feedback

4. Wide-band VGA 34

This Bi-CMOS process has some excellent properties as mentioned below,

1. Local feedback via ZF and Q2 makes the output node a low impedance node. So , same-

cell cascading wil not degrade the overall BW!

2. Q2 acts as a level shifter.As a result, no dc current flows via ZF. So, orthogonal biasing is

now possible.

3. ZF has low pass characteristics as illustrated in the upper left figure. It adds a zero that

cancels the dominant pole. So, BW gets enhanced.So far , we have seen some interesting tricks that might be utilized in the design of the target VGA !

4.3.2 VGA with Current Injection

This interesting topology was explored because my thesis examiner has suggested it [14]

in the beginning of my research work. As illustrated in Figure 4.8, we can use a nMOS or pMOS

transistor as a load of a common source amplifier. Then output impedance is (1/gm ) in parallel

with the rds of the transistor. If some tricks are applied, this architecture can become a highly

linear amplifier as shown in the following gain equation. Because, the gain is dependent on

geometric parameters , not on input signal.

(a) (b)

Figure 4.9: Common Source Amplifier with (a) nMOS load (b) pMOS diode load

4. Wide-band VGA 35

Now if we can vary the load current without disturbing the bias current of the input transistor

, then we can get an elegant VGA ! The following circuit illustrates this concept. The gain control

voltage should be used to control the current of the current source load (Is ). Here, the drain

current of M1 transistor is equal to the sum of both the M2 and (Is) currents.

Figure 4.10 : VGA with Current Injection Load

The differential versions of the above circuit [8] are shown below [1].

(a) (b)

Figure 4.11 : VGA with Current Injection (a) nMOS Load (b) pMOS load.

4. Wide-band VGA 36

However , the above circuit [1] has some drawbacks as mentioned below.

1. pMOS transistors adds a lot of capacitance to the high speed signal path. This degrades the

BW.

2. nMOS load has body-effect. So, it adds non-linearity !

3. Active load consumes some voltage headroom. So , not suitable for high output swing.

4. Orthogonal biasing is not possible ! When drain current of M2 is changed during gain

variation , output dc level changes although weakly. This is manifest in the following

equation.

5. The output node of this circuit is a high impedance node as (1/gm2 ) , which cannot be

much low for high gain , is in parallel with the rds of the CMOS transistor which is quite

high. The input node is also a high impedance node since Rin of the CMOS transistor tends

to be infinite in the low frequency domain. As a result , if this circuit is cascaded with the

same cell , then the interface node will not be low ohmic. So , the BW of the cascade will

be degraded a lot.

After this long exploration we can confidently conclude that this VGA cell is not suitable for our

AGC amplifier. Let|'s steer our ship to another direction.

4.3.3 Gilbert Cell

This topology as shown below [15] is quite famous and find widespread use in many

domains. Here, the bias current of a differential amplifier (M1 , M2) can be varied with the help of

four transistors ( M3 – M6). When gain control voltage is maximum , then small gain is also

positive and vice versa.

Figure 4.12 : Gilbert Cell

max when 1 == ctrlVRgAv Lm

min when 1 =−= ctrlVRgAv Lm

4. Wide-band VGA 37

However , this topology has some disadvantages as mentioned below.

1. Too many transistor are on a stack ! And each one occupies a voltage headroom. As a

result, available voltage headroom for the output signal is quite low. The situation gets

worse if Vdd is also low.

2. Orthogonal biasing is not possible. Because , when Vctrl changes , bias current changes

,which in turn change the voltage drop over load resistor. As a result , output dc level

changes. This might affect the biasing of the input transistor of the next stage VGA cell.

Hence this architecture is not suitable for dc coupling. If Vdd is low , this issue become

more serious.

3. The output node of this circuit is a high impedance node as R1 which can not be low for

high gain ) is in parallel with the rds of the cascode CMOS transistors which is quite

high. The input node is also a high impedance node since Rin of the CMOS transistor tends

to be infinite in the low frequency domain. As a result , if this circuit is cascaded with the

same cell , then the interface node will not be low ohmic. So , the BW of the cascade will

be degraded a lot. However , some analog masters [8] have solved this high output impedance problem by using a

special trick called “ Cherry-Hooper load ”.

4.3.4 Gilbert Cell with Cherry-Hooper Load

This majestic topology as illustrated below is used by some German analog gurus [12].

Well , in order to understand its full beauty ,we should first understand the origin of the Cherry-

Hooper load. Let's steer the ship to that direction.

4. Wide-band VGA 38

Fig 4.13 Gilbert Cell with Cherry-Hooper Load

4.3.4.1 Cherry-Hooper Amplifier

This topology [8] as illustrated below is a solution to the BW degradation of the

cascade of common source amplifiers. As shown in the following equations , gain and BW in the

cascade are tightly coupled. Due to cascading , the capacitive load at the interface gets increased.

Figure 4.14 : Cascade of Common Source Amplifiers

4. Wide-band VGA 39

Miller effect also aggravates this situation. Hence the pole at the interface ( wx ) becomes low

and the overall BW degrades. One way to solve this problem is to decrease the resistive load of

the first stage. But then , as implied from the following equations, gain decreases.

Well , basically what we want for high BW is to charge the capacitive load in the high speed path

rapidly. In this context , an inductor placed in series with the resistive load is quite helpful.

However , as mentioned before , inductors will not be used in our chip design. Well , if capacitive

load can be divided into two parts , then charging and discharging will be faster and BW

improves. So, we can isolate the capacitance of the second stage from the that of the first stage by

interposing a source follower between the two stages. The following circuit [8] illustrates this trick.

Figure 4.15 : Source Follower in a Cascade of Common Source Amplifiers

However, the use of the source follower has some demerits.

Firstly, it has body effect and the output swing at the (x) node is limited since the source follower

occupy some voltage headroom.

4. Wide-band VGA 40

Secondly, the gain of the soure follower is not equal to one , rather little less. So , signal attenuation

occurs.

Thirdly , the huge capacitive load of the M2 stage may cause ringing in the frequency region of

interest if the output impedance of the first stage is higher than the (1/gm ) of the source follower.

This ringing problem is better explained in the appendix section.

Instead of using the source follower , we can use voltage current feedback also called the shunt

shunt feedback where voltage at the output node is sensed and then current is fed into the input

node. Actually, there are a number of feedback techniques out of which only the voltage-current

feedback decreases both the Zin and Zout. Using this techniques we can get low impedance

nodes in the high speed path. The resultant topology as illustrated in Figure 4.16b [8] is called

Cherry-Hooper amplifier [16]. Here the feedback resistor Rf provides current into the first stage

after sensing the voltage at the output of the second stage.

(a) ( b )

Figure 4.16 : (a) Cascade of CS amplifiers , (b) Cherry-Hooper Amplifier

Below the above two topologies are compared. We can clearly observe that in the Cherry Hooper

amplifier , gain can be made independent of the output impedance ! In other words , those two

parameters are loosely coupled.

4. Wide-band VGA 41

( a) ( b )

Figure 4.17 : (a) Equations for Fig 4.16a (b) Equations for Fig 4.16b

Besides, Rout and Rx is quite low. As a result strong impedance mismatch occurs at the output

node and the interface node (x) node. The following figure better illustrates this issue.

Consequently the overall BW does not degrade much.

Figure 4.18 : Strong Impedance Mismatch

4. Wide-band VGA 42

The differential version of the Cherry-Hooper amplifier [8] is shown in Figure 4.19a. Here pMOS

current source loads add capacitance to the high speed signal path and consequently decreases the

BW.

Figure 4.19 : Differential CH Amplifier with (a) Current Source Load , (b) Resistive Load

However, this problem can be solved by using resistors for biasing [8] as shown in Figure 4.19b.

This resistive Cherry-Hooper amplifier along with the Gilbert cell can become an interesting VGA

as illustrated in Figure 4.20. Although this circuit has been shown earlier , it is repeated here to

help better understanding.

Figure 4.20 : Gilbert Cell with Cherry Hooper Load

4. Wide-band VGA 43

Although elegant , this topology has some features that has made it unsuitable for our AGC

amplifier. Those features are mentioned below.

1. The bias resistor consumes large voltage headroom as it provides bias currents to the both

internal and external differential amplifiers. So available voltage headroom for the output

signal is reduced.

2. However , too many transistors are stacked. As a result , output swing range is further

reduced.

3. For gain variation , bias current is varied. But this bias current also flows via the output

resistor. As a result output dc level changes. This might affect the biasing of the input

transistor of the next stage VGA cell. Hence this architecture is not suitable for dc

coupling. If power supply ( Vdd ) is low , this issue become more serious.

4.3.5 Cherry-Hooper VGA

Without using the Gilbert cell, the Cherry-Hooper amplifier in its own right can be used as a

VGA as illustrated below.

Figure 4.21 : Cherry Hooper VGA

4. Wide-band VGA 44

Since the gain as shown below is dependent on the gm of the input transistor , it can be varied by

simply controlling the bias voltage of the current source.

But this circuit has some disadvantages. The bias current flows via the gain setting resistor ( Rf).

So, it is not orthogonally biased ! The pMOS current sources degrades the BW by adding

capacitance in the high speed signal path. However , it can be solved by substituting the pMOS with

simple resistor.

But , then when the tail current is varied for changing the gain , the output dc level changes as the

voltage drop over the resistor changes. So, this VGA topology is not suitable for dc coupling

because the change in output dc level might affect the biasing of the input transistor of the next

stage VGA cell. If Vdd is low , this issue become more serious.

However , some Japanese guys [18] have solved this dc-coupling problem. Their trick is worthy of

exploration. Let' steer the ship to that direction.

Fmm

Fmo Rgg

RgAv 12

11 ≈

−=

21

mgxRoutR ≈=

4. Wide-band VGA 45

4.3.6 Cherry-Hooper VGA with Parallel Feedback The following wideband circuit as shown in Figure 4.22 has constant output dc level

even though the bias current of the external pair is varied because the source follower M3 provides

the isolation. However , M3 is not free from the body effect. As a result , the required VGS is quite

big. So signal swing at the internal node is quite limited. So, this topology cannot satisfy the

requirement of the high output swing as needed in our AGC amplifier.

Figure 4.22 : CH VGA with Parallel Feedback

Fmo RgAv 1≈

21

mgoutR ≈

4. Wide-band VGA 46

Moreover , this circuit is not orthogonally biased as the bias current flows via the gain setting

resistor as implied in the above equations. These two demands – orthogonal biasing and high output

swing can be satisfied if we apply some special tricks on the above circuit. The resultant circuit

topology is discussed below.

4.3.7 Orthogonally Biased CH VGA

In the following circuit feedback resistor , instead of the bias current , is varied for

controlling the gain. The bias current for the external differential pair is provided via a resistor

instead of the output load resistor (RD). No pMOS or nMOS is used. So , high output swing can be

achieved.

Figure 4.23 : Orthogonally Biased CH VGA

DRmgFR

xR2

≈

4. Wide-band VGA 47

The whole circuit can be biased in such a way that no dc current flows via feedback path.

Orthogonal biasing ! As a result , when the value of feedback resistor changes for gain variation,

output dc level does not change as evident in the equations (27,28 ) . So , dc coupling is possible.

The feedback path provides shunt shunt feedback. So , both the interface node and the output node

become low ohmic. So comes the benefit of the strong impedance mismatch. So , this topology is

suitable for broadband cascading. Moreover , the circuit is more complex than a second order stage.

So , less BW shrinkage ! Considering all these features we may safely conclude that we have finally

discovered the right topology !

4.3.7.1 Practical Issues If we observe the following voltage transfer curves of this “golden” VGA as

illustrated in Figure 4.24, we see that when signal swing is high, non linearity pops up. One of the

reasons is that the feedback transistor , which is supposedly be in the triode region or in the cut-off

region , always run into other forbidden domains such as sub-threshold or saturation regions.

Fmm

Fmo Rgg

RgAv 12

11 ≈

−=

21

mgxRoutR ≈=

4. Wide-band VGA 48

Figure 4.24 : Voltage Transfer Curves of the Orthogonally Biased CH VGA

To circumvent this problem a cascade of three VGA cells have been used in such a way that output

swing of each VGA always remains in the linear region. As a result , the net output swing after the

third VGA is not high enough . So we have used a fixed gain CH amplifier to provide the remaining

gain. This fixed gain amplifier belongs to the same topology without the pMOS transistor in the

feedback path.

Now comes the challenging problem of how to control the gain of each VGA in a

synchronized way. Let's explore that problem.

5. AGC in Analog Domain 49

5. AGC in Analog Domain

5.1 AGC Architecture

The VGA cascade must provide constant output swing while adding as little non-linearity

as possible.. When input signal swing is low , the gain in the cascade should be progressively bigger

starting from moderately low gain and ending in very high gain as illustrated above so

Figure 5.1 : VGA Cascade with Gain Levels

moderately low gain and ending in very high gain as illustrated above so that each VGA can

accommodate the input signal within its linear range. However, when input signal swing is high ,

then it has to be attenuated first and then gradually amplified in the subsequent stages. As a result,

each VGA will operate within its linear region. Now comes the question of generating gain control

voltages ?

To solve this problem , some published works [ 5, 11] have been carefully studied. Those works

have shown some tricks which have helped to design the gain control circuit. As illustrated in the

following picture, each VGA gets its own gain control voltage from a single-ended amplifier. All

these three amplifiers are connected to the same capacitor on which the information regarding the


existing output swing level of the AGC amplifier is stored as a voltage (Vc).

Figure 5.2 : VGA Cascade with Gain Levels and Gain controlling Amplifiers

When the gain control voltage (Vagc) decreases, the equivalent feedback resistance as implied in

the following figures decreases . As a result, gain decreases too.

Figure 5.3 : VGA Cascade with Gain Levels and Gain Controlling Amplifiers

The voltage transfer curves of the three gain control amplifiers have to be determined carefully.

These amplifiers should be synchronized in such a way that when Vc increases , Vc and the gain of

Fmo RgAv 1=


each amplifier should change in the same direction. As an example , if the output swing of the VGA

cascade is higher than the expected value , then Vc should increase , then logically the gain of each

VGA should decrease so that the output swing of the third VGA falls closer to the expected below.

This kind of regulation implies that each gain control amplifier should be non-inverting amplifier.

And they should be co-related in such a way that the first VGA always operate between the very

low and moderately high gain region whereas the second VGA should operate from low to high

region. Lastly, the third VGA should provide gain ranging from high to very high level. All these

issues are illustrated in the following figure.

Figure 5.4 : Transfer Curves of the Gain Control Amplifiers

5.2 Gain Control Amplifiers

But how to design amplifiers with such voltage transfer curves ? None of these amplifiers has

its maximum output at Vdd. For the gain control amplifier of the first VGA in the VGA cascade,

output swing can vary from low ,close to zero voltage , to moderately high. A pMOS transistor with

resistive load as illustrated below can provide such property. The gate overdrive of pMOS is made

intentionally big according to the following equation where width or length can be tweaked.

Figure 5.5 : Gain Control Amplifier for the first VGA in the Cascade

( )LWCgVVoxn

mOVsatDS µ

==)(


The second gain control amplifier differs from the first one only in terms of its lower limit which is

higher. So ,when Vc is high , pMOS gets shut down , then Vout can be still high if a constant dc

current can be injected . This idea is shown below. However , care should be taken while biasing

the current source in this circuit.

Figure 5.6 : Gain Control Amplifier for the second VGA in the Cascade

For designing the third gain control amplifier as illustrated below, the pMOS input transistor can

not be used any more because the lower limit is too high. So, a nMOS input transistor with an

Figure 5.7 : Gain Control Amplifier for the third VGA in the Cascade

intentionally large gate-overdrive is chosen according to the equation 31. But for the high upper

limit, a diode connected pMOS transistor load with a constant current bias by an extra

( )LWCgVVoxn

mOVsatDS

µ==)(


current sink transistor is used. This constant current according to the equation 32 helps the pMOS

load consume a large voltage headroom even when the nMOS transistor is shut down.

5.3 How to Generate Vc ?

The Vc generating circuit is shown below. This architecture has its initial

motivation in some published works [ 5, 11]. The peak output and the average output of the third

VGA cell are extracted by peak detector circuits and then are compared with respect to an

expected peak value which is equal to Vav plus an offset voltage . When the peak value is

Figure 5.8 : Vc Generating Circuit

( ) Poxp

sTH

LWCI

SG VV +=µ

2


is greater than the expected peak , then Vc increases and then the gain of each VGA cell also

decreases. As a result , the peak output of the third VGA cell also decreases and fall close to the

expected peak.

In order to make the differential amplifier with offset,we need to keep in mind the following design

constraints.

1. Vc needs wide swing range.

2. Vc should be ripple-free.

3. AGC path should have low BW.

4. Cagc has to be big.

5. Vpeak and Vav are not quite high. So, input pairs should be pMOS.

6.

I In order to make the differential amplifier with offset ,we have used the following circuit

topology [5,11]. Here the reference resistor is placed in series with an input transistor to get an

offset voltage.

Figure 5.9 : Differential Amplifier with Offset

This offset voltage along with the average voltage is equal to the peak value when the bias current

is equal in the both branches as illustrated in the following equation 33.


Here the sum on the right side of the equation 33 is considered as the expected peak voltage. If real

peak value is greater than the expected peak , Vc increases.

5.4 Peak Detector

The peak detector [19] used in the AGC circuit has the following architecture.

Figure 5.10 : Peak Detector

Here transistors act as diodes. But they should load the preceding VGA with less capacitance. So

their size should be small. However, peak should be detected quickly. Decay current should be low.

But it should be quite stable. Hence special bias circuit with careful layout is needed. For average

detection, R should be big. Otherwise , single ended swing will be affected.

refss

avpeak RIVV

+=

21

6. Impedance Matching Stages 56

6. Impedance Matching Stages

6.1 Output Matching Stages The high speed signal as shown in Figure 6.1 undergoes a cascade of three VGA cells and

a fixed gain CH amplifier which maintain a constant output swing .This signal swing consisting of 4

levels is not digital swing , rather analog. So , the subsequent stage down the channel cannot be a

CML buffer, rather a predriver and an output buffer as illustrated above.

Figure 6.1 : AGC Amplifier Architecture However the design of those blocks have some specific constraints as follows.

No source follower should be used. Ringing comes up in the output signal since the output

pad provides a large capacitive load in parallel with the 50 ohm load. For more elaborate

explanation , the appendix should be checked.

Besides , transistors in the output buffer are quite wide in order to accommodate the large bias

current required for large output swing over low impedance load ( close to 50 ohm).So , its Cin is

quite huge. But the predriver has relatively low Cin.

Moreover , large input and output swing range since signal has already undergone four stages


upstream. The small signal gain of the output buffer is close to unity. Signal attenuation occurs!

To compensate this reduction in signal swing , some gain should be provided by the predriver.

6.1.1 Output Buffer The following circuit [20,8] called ft doubler is used as the output buffer. Here,

small signal ground has moved from the drain node of the Iss1 or Iss2 to the Vcm node where

Vcm is the average voltage of the input signals. As a result, input differential signal encounters two

Cgs in series. So , the effective input capacitance is halved. So the ft of the input transistor is

doubled !

Figure 6.2 : Output Buffer

RT shown here is called anti-reflection resistor which is required to absorb any refection coming

from the far -end due to the improper termination on that end. The value of this resistor line should

be chosen carefully while keeping in mind that the incoming reflection will encounter parasitics at

the bond wire and output pad which will lower the real value of RT . So, this resistor should be

somewhat bigger than 50 ohm [10, 8]. An added advantage is that equivalent output resistance will

be higher than 25 ohm. So , less bias current will be required to maintain the target output swing.


6.1.2 Wide-band Predriver

This novel circuit is originally proposed in [10] where it is used as a limiting amplifier

. As illustrated below , the circuit has low ohmic nodes in the high speed path due to the shunt

shunt feedback. However, unlike the resistive feedback in the conventional CH amplifier, active

feedback is used here.

Figure 6.3 : Predriver Circuit

To make this circuit click , we need to apply some well-guided tricks. Iss2 should be twice than Iss1

whereas Iss3 should be quite small.


6.2 Input Matching Stage

So far we have ignored the input matching. Now is the time to look into this. A carefully

designed input stage preceding the VGA as illustrated below should help the chip to absorb as

much frequency contents as possible. So it should provide broadband matching. However, for that

purpose , common gate topology is not suitable.

Figure 6.4 : AGC Amplifier Architecture

This input stage should also have low capacitance in order to avoid loading on the preceding stage

(TIA). Another important issue is the pad capacitance which degrades input return loss (S11) at

high frequency.

For our chip , a resistor topology as illustrated in Figure 6.5 has been chosen. It provides good

broadband matching. However, it adds noise!


Figure 6.5 : Input Matching Stage

Since 50 ohms is quite low, any high frquency noise from the dc voltage source of the input

common mode level might disturb the input transistors badly. Hence, common mode resistance

should be quite big compared to 50 ohms.

7. Chip Layout 61

7. Chip Layout

7.1 Layout Issues

Analog layout is a tedious , labour-intensive job. But it has to be done quite carefully,since

transistors on chip obey the laws of physics , not the whims of the IC designer's mind. This issue is

more critical in high speed analog layout. To avoid layout iteration we need to check the following

tips [21].

1. Differential signal path should be symmetric.

2. The axis of the differential pairs should coincide with the thermal axis for good matching ,

particularly when temperature sensitivity is an issue.

3. Interconnect capacitance should be minimized.

4. Metal layers should not run over the resistors.

5. Trust Physics , not the simulator.

In the subsequent pages the full chip layout and the layout of other building blocks are

shown.

7.2 Full Chip Layout The output pads are at the top whereas the input pads are at the bottom. The big blue

metal inside the chip is for power supply. The rightmost block is the AGC module and the leftmost

blocks constitute the bias circuitry. The cascaded blocks along the centre of the axis are in the

7. Chip Layout 62

Figure 7.1 : Layout of the Full Chip

high speed path path. The layout of the individual blocks are shown subsequently.

7. Chip Layout 63

7.3 Block-level Layout

Figure 7.2 : Layout of Output Buffer + Predriver

7. Chip Layout 64

Figure 7.3 : Layout of VGA

7. Chip Layout 65

Figure 7.4 : Layout of AGC

8. Post Layout Simulation Results 66

8. Post Layout Simulation Results

The analog extracted view with all its parasitic capacitances of the full chip was tested

with three different type 2 7 - 1 PRBS signals each of which in turn was generated by PAM-4

generator as shown in Figure 7.1. The details of PAM-4 generator are mentioned in the appendix.

No jitter was added in the input signal. Each input signal has about 107.5 ps long ISI spread. Each

middle eye width is 892 ps whereas the symbol rate is 1 Gsym/sec.

The results of the output eye diagrams are also shown below. Here , the middle eye is considered

as the reference eye.

Figure 7.1 : The Eye Diagrams of the Input Signal

8. Post Layout Simulation Results 67

Figure 7.2 : The Eye Diagrams of the Output Signal

From the above table we can extract some interesting features.

1. ISI spread increases as the input signal swing decreases , because the corresponding gain of

the chip increases while the BW decreases.

2. The output differential signal swing is around 1700 mVpp whereas the target spec is 1800

mVpp.

3. The eye-height of each eye in all three cases are greater than 400 mVpp which is the

minimum.

4. In every case all three eyes are almost equal to each other – a testament to the good

linearity of the voltage transfer curve of the chip.

9. Power Budget

Although the requirement of the power consumption is not stringent , still it cannot be

ignored. The DC power consumption of each building block as shown in Figure 9

Figure 9 : AGC Amplifier Architecture

has been estimated from the DC analysis of the transistor level schematic. The following results

have been found.

1. Each VGA cell consumes about 5.107 mA current from a 3.3 V power supply. The resulting

power consumption is 16.8531 mW.

2. The Cherry-Hooper amplifier which is almost alike to the VGA consumes about 5.107 mA.

3. The predriver consumes about 20.658 mA current . The corresponding power consumption

is 68.1714 mW.

4. The output buffer consumes about 54.46 mA current which corresponds to 179.718 mW

power consumption.

5. The high speed path , in total , consumes 95.546 mA current that corresponds to 315.3018

mW power consumption.

Here the power consumption of the AGC and bias circuit are not mentioned.

10. Conclusion 69

10. Conclusion Now is the time to sum up all the work , brain storming and sleepless nights in the six

month long journey at Fraunhofer IIS in Germany.

In a nutshell ,

1. I have explored various topologies for VGAs and discovered a right topology.

2. Designed VGA , AGC , predriver and output buffer and biasing circuits.

3. Completed full chip layout and post-layout simulation.

11. Future Work

In future we expect that extensive corner simulations as well as Monte Carlo simulation

will be performed. Secondly , the chip should be fabricated and tested. Then a CDR chip for 4-

PAM signaling should be designed. Thirdly a transceiver for 4-PAM signaling should be

designed.

12. Appendix 70

12. Appendix

12.1 The Ringing of the Source Follower

The source follower or common drain amplifier as shown in Fig 12.1 has some interesting

properties that become manifest in the high frequency domain. Since the AGC amplifier is a

broadband amplifier, we need to consider this issue deeply.

(a) ( b )

Figure 12.1 : Source Follower in (a) schematic , ( b ) small signal model

The output impedance of the source follower can be derived from the following small signal model

where the output impedance of the preceding stage is represented by Ri.

Figure 12.2 : Source Follower in (a) schematic , ( b ) small signal model

12. Appendix 71

Ignoring the parasitic capacitances of the gate to drain and drain to bulk capacitances of the

transistor, Zx can be represented by the following equation.

The property of an inductive impedance is that the impedance increases as the frequency increases.

As illustrated below , Zx becomes inductive when Ri is higher than (1/gm ) . This case is usually

common since source followers are commonly used as a buffer between a low impedance load and

high gain amplifier whose output impedance is quite high. The problem

Figure 12.3 : Output Impedance of the Source Follower in two cases

of ringing arises if this low impedance load is accompanied by a capacitive load. To better illustrate

this idea , we need to observe the following circuit which is equivalent to the previous small signal

model of the amplifier. Here the inductor ( L ) along with with the capacitive load at the output

will form an LC tank whose resonant frequency may fall in the passband of the AGC amplifier.

12. Appendix 72

Figure 12.4 : Small Signal Model of Source Follower for Output Impedance Calculation

along with the corresponding equations

Then ringing will appear in the step response as illustrated below. The presence of ripple in the

signal is not good for the subsequent CDR circuit. Then ringing will appear in the step response as

illustrated below [12].

Figure 12.5 : Step Response of the Source Follower

13. References 73

13. References

1. Jafar Savoj, Stanford EE392H course

2. www.tokyo-med.ac.jp/genet/picts/dna.jpg

3. Jared Zerbe , Lecture on Multi-level Signalling, Stanford EE392H course

4. Razavi , “ Prospects of CMOS Technology for High Speed Optical Communication Circuits” ,

IEEE JSSC , vol. 37 , no. 9 , Sep. 2002 5. D. Kucharski and K.T. Kornegay, “Jitter Considerations in the design of a 10-Gb/s automatic gain

control amplifier” , IEEE Tran. On Microwave theory and techniques , vol. 53 , no. 2 Feb 2005

6.. Behzad Razavi , “Design of Analog CMOS Integrated Circuits ”

7. M. Perrott , MIT 6.976 lecture notes

8. B. Razavi , “Design of Integrated Circuits for Optical Communications”

9. Ali Hajimiri et al. “ Bandwidth Enhancement for TIAs ”, IEEE JSSC, vol.39, no.8 ,Aug04

10. S. Galal and B. Razavi , “ 10- Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-μm

Technology” , IEEE JSSC , vol. 38 , no. 12 , DEC. 2003.

11.Mihai A. T. Sanduleanu , Paul Manteman , “ A Low Noise, Wide Dynamic Range,

Transimpedance Amplifier with Automatic Gain Control for SDH/SONET ( STM16/OC48) in a 30

Ghz ft BiCMOS Process ” , Philips Research Eindhoven

12. H.-M. Rein et al. “Design Considerations for Very High Speed Si-Bipolar IC's Operating up to 50

Gb/s” , IEEE JSSC , vol. 31 , no. 8, Aug 1996.

13. Md. Iqbal Younus, Ph.D Thesis, “Circuit Design For Low Voltage Wireless Receiver With

Improved Image Rejection”, Ohio State University.

14. . Stefan Andersson, C. Svensson, “ A 750 MHz to 3 GHz Tunable Narrowband Low-Noise

Amplifier” , ISY Department , www.ek.isy.liu.se

15. Jerzy Deborawski, Lecture notes of RF Transceiver course , Linkoping University , Sweden

16. E. M. Cherry and D.E. Hooper , “The design of wide-band transistor feedback amplifier ”,

in Proc. Inst. Elec. Eng. , vol.110 , Feb 1963, pp. 375-389.

17. J. M. Steininger, “Understanding Wide-band MOS Transistors”

18. N. Ishihara et al , “ 9 Ghz Bandwidth, 8-20 dB Controllable Gain Monolithic Amplifier Using

AlGaAs /GaAs HBT Technology” , Electronics Letters , Sep. 14 , 1989 , vol. 25 , no. 19.

13. References 74

19. R.G. Meyer , “Low Power Monolithic RF Peak Detector Analysis” , IEEE JSSC, vol. 30, no.1 ,Jan

1995, pp. 65-67.

20. T.H.Lee , “CMOS Radio Frequency Integrated Circuits” book

21.Gilbert , Toumazou et al , “Trade-offs in Analog Circuit Design” book

22. E. Säckinger , W. C. Fischer, “ A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48

Receivers”, IEEE JSSC, vol. 35 , no. 12 , Dec 2000.

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