IEEE10/NSSR. Kass N21-4 1

A. Adair, W. Fernando, K.K. Gan, H.P. Kagan, R.D. Kass,

H. Merritt, J. Moore, A. Nagarkar, S. Smith, M. Strang

The Ohio State UniversityP. Buchholz, A. Wiese, M. ZiolkowskiUniversität Siegen

OUTLINEIntroductionResult on PIN Receiver/Decoder ChipResult on VCSEL Driver ChipSummary

IEEE10/NSSR. Kass

Proposal to add one more layer to the current pixel detector:Insertable B-Layer or IBLInstallation ~ 2015-6Optical readout will use VCSEL/PIN arrayPropose to use an updated version of current driver (VDC) & receiver/decoder (DORIC) chipsUpgrades include redundancy & individual VCSEL current controlValuable experience for development of SLHC system

Experience gained from the development/testing of such new chips would help the development of on-detector array-based opto-links for SLHCWill discuss results from 1st prototype chip (130 nm) submitted 2/2010, received 6/2010, beam test 8/2010 N21-4 2

~1.85m

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Chip Content

Decoder (40/80/160/320 Mb/s, spare)

Decoder (40Mb/s)

Decoder (40Mb/s)

Decoder (40Mb/s)

Design Photo

CML Driver with pre-emphasisVCSEL Driver with pre-emphasisVCSEL Driver with pre-emphasisVCSEL Driver VCSEL Driver (spare)

1.5 mm

VCSEL: Vertical Cavity Surface Emitting Laser diodeVDC: VCSEL Driver CircuitPIN: PiN diodeDORIC: Digital Optical Receiver Integrated CircuitThe DORIC decodes bi-phase mark encoded clock & commands

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PIN Receiver/Decoder

PIN

Prototype chip only.

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Command Decoder Interface

Courtesy of FE-I4 of IBLPrototype: majority voting, 3 command decodersProduction: majority voting, up to 11 command decoders

In prototypechip only

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Test card

chip

Decoder Test Card

PIN opto-packULM 5 Gb/s

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Recovered Clock/Data

320 Mb/sDecoded clock

Decoded data

Decoder recovers clock & data from bi-phase mark input stream

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PIN Receiver/Decoder

All channels work at 40 Mb/sMulti Speed version works at 40, 80, 160, & 320 Mb/s160 & 320 Mb/s need external bias tuning for proper operationSteering signal to the spare channel works

Peak-to-peak clock jitter:40 Mb/s: 1420 ps (multi speed)80 Mb/s: 750 ps160 Mb/s: 193 ps320 Mb/s: 103 ps

Threshold for no bit errors:40 Mb/s: Multi speed: 40 A Ch 1: 19 A Ch 2: 22 A Ch 3: 20 A80 Mb/s: 58 A160 Mb/s: 74 A320 Mb/s: 110 A

Measured Jitter & Threshold

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VCSEL Driver SectionChannel

Select (3:0)

CommandWrite Write Enable (3:0)

DAC Bits (7:0)

input added for prototype chip only.

SetDAC

VCSEL

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VDC Test Setup

Light from the 4 VCSELs

R. Kass

Opto-chip

Finisar 5 Gb/s VCSEL array

Fiber aligned over VDC/VCSEL 2

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VDC Results

Power-on reset circuitIn the present pixel detector an open control line disables 6 opto-links Prototype chip has a power-on reset circuitchips will power up with several mA of VCSEL current Test portcan steer signal received to spare VDC/VCSELcan set DAC to control individual VCSEL currents All 4 channels run error free at 5 Gb/sincludes the spare with signal routed from the other inputs

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VCSEL Driver with Pre-Emphasis

Pre-emphasis working with tunable width and height

R. Kass

Mainamplitude

Pre-emphasis

160 Mb/s

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Eye Diagrams @ 4.8 Gb/s

R. Kass

No pre-emphasisRise/fall times: ~60-90 ps Measured with 4.5 GHz optical probeBit error rate < 5x10-13

VDC 3Spare VDC: rerouted from VDC 2

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Irradiation Results

2 chips were packaged for irradiation with 24 GeV/c protons at CERN in August 2010Each chip contains 4 channels of drivers and receiversTotal dose: 1.6 x 1015 protons/cm2

All tests are electrical to avoid complications from degradation of optical componentsLong cables limited testing to low speedObserve little degradation of the devicesEvaluation of full performance await the return of devices to OSU from CERN

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VDC Irradiation Results

VDC driving 25 Ω with constant control current (CC)Previous VDC prototypes (130 nm) irradiated in 2008 Drive current decreases with radiation for constant CCdriver circuit fabricated with thick oxide processPMOS and NMOS have different threshold voltage shiftsUse only PMOS in the current mirror in 2010 prototype See improvement in the 2010 version

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2010

2008

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Single Event Upset Rate

SEU hardend latches or DAC could be upset by traversing charged particles126 latches per 4-channel chipSEU tracked by monitoring the amplitude of the VDC drive current13 instances (errors) of a channel steered to a wrong channel in 71 hours for chip #1 Similar upset rate in chip #2Estimate SEU rate: σ = 1x10-16 cm2

particle flux ~3x109 cm-2/year @ opto-link location SEU rate ~3x10-7/year/link

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Summary

Prototyped opto-chip for 2nd generation ATLAS pixel opto-linksIncorporated experience from current opto-links by adding: redundancy to bypass broken PIN or VCSEL channel individual VCSEL current control power-on reset to set VCSEL current to several mA upon power upResults of tests:VCSEL driver can operate up to ~ 5 Gb/s with BER < 5x10-13

PIN receiver/decoder works even at low thresholdOnly small decrease in VDC output current after irradiationVery low SEU rate in latches/DACAll added functionalities work! All results are

preliminary

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