IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI ... · OWER dissipation is one of the most important aspects of current nanoscale VLSI design. Ultralow power (ULP) operation

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

A Low-Voltage Radiation-Hardened 13T SRAMBitcell for Ultralow Power Space Applications

Lior Atias, Student Member, IEEE, Adam Teman, Member, IEEE, Robert Giterman, Student Member, IEEE,Pascal Meinerzhagen, Member, IEEE, and Alexander Fish, Member, IEEE

Abstract— Continuous transistor scaling, coupled with thegrowing demand for low-voltage, low-power applications,increases the susceptibility of VLSI circuits to soft-errors,especially when exposed to extreme environmental conditions,such as those encountered by space applications. The mostvulnerable of these circuits are memory arrays that cover largeareas of the silicon die and often store critical data. Radiationhardening of embedded memory blocks is commonly achievedby implementing extremely large bitcells or redundant arraysand maintaining a relatively high operating voltage; however,in addition to the resulting area overhead, this often limitsthe minimum operating voltage of the entire system leading tosignificant power consumption. In this paper, we propose thefirst radiation-hardened static random access memory (SRAM)bitcell targeted at low-voltage functionality, while maintaininghigh soft-error robustness. The proposed 13T employs a noveldual-driven separated-feedback mechanism to tolerate upsetswith charge deposits as high as 500 fC at a scaled 500-mV supplyvoltage. A 32×32 bit memory macro was designed and fabricatedin a standard 0.18-µm CMOS process, showing full read andwrite functionality down to the subthreshold voltage of 300 mV.This is achieved with a cell layout that is only 2× larger thana reference 6T SRAM cell drawn with standard design rules.

Index Terms— Critical charge, low voltage, radiation effects,radiation hardening, single-event upset (SEU), soft errors,space applications, static random access memory (SRAM),subthreshold, ultralow power (ULP).

I. INTRODUCTION

POWER dissipation is one of the most important aspectsof current nanoscale VLSI design. Ultralow power (ULP)

operation is of particular importance in VLSI chips for spaceapplications, where available energy resources are limited.Future small, low-cost satellites have an even lower powerbudget, as the total satellite weight is often reduced byrestricting the use of heavy batteries and power supplies. Themost efficient way to achieve ULP operation in integrated

Manuscript received July 28, 2015; revised November 27, 2015; acceptedJanuary 6, 2016. This work was supported by the Tashtiyot Program throughthe Israeli Ministry of Science.

L. Atias, R. Giterman, P. Meinerzhagen, and A. Fish are with EmergingNanoscaled Integrated Circuits and Systems Laboratories, Faculty of Engi-neering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail: [email protected]; [email protected]; [email protected];[email protected]).

A. Teman was with the Telecommunications Circuits Laboratory, Instituteof Electrical Engineering, Swiss Federal Institute of Technology Lausanne,Lausanne 1015, Switzerland. He is now with Emerging Nanoscaled IntegratedCircuits and Systems Laboratories, Faculty of Engineering, Bar-IlanUniversity, Ramat Gan 5290002, Israel (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2016.2518220

circuits is to aggressively reduce the supply voltage (VDD)and operate all components of the chip in the near-thresholdor subthreshold region [1], [2], thereby significantly reduc-ing both static and dynamic power consumption. However,in addition to the well-known challenges of a low-voltagecircuit design, such as increased delay, sensitivity to processvariations, and temperature fluctuations, low-voltage circuitsare much more susceptible to radiation effects than circuitspowered at nominal supply voltages [3].

Soft errors or single-event upsets (SEUs) caused byradiation strikes are the primary causes of failure in VLSI cir-cuits operating within a highly radiating environment. Accord-ingly, maintaining data integrity in light of SEUs has becomean integral aspect of memory cell design [4]. Soft errorsoccur when an energetic particle hits and passes through asemiconductor material, potentially causing a bit flip in thememory cell [5], [6]. The energetic particle frees electron–hole (e–h) pairs along its path in the material as it losesenergy. When the particle hits a reverse-biased p-n-junction,such as a transistor diffusion-bulk junction, the injected chargeis transported by drift and causes a transient current pulse thatchanges the node voltage. Data loss occurs when the collectedcharge (Qcoll) exceeds the critical charge (Qcrit) that is storedin the sensitive node. The charge deposited by a particle strikecan be calculated from the integral of the transient currentpulse, and Qcrit is defined as the minimum charge depositedin a sensitive node that results in a memory bit flip [7].

SEUs and other similar single-event effects (SEEs) are oftenconsidered when designing for space applications and otherhigh-radiation environments. However, due to the reductionof Qcrit with technology scaling [8], SEUs can also occurin standard terrestrial environments at nonnegligible rates [9].Architectural solutions, such as error correction coding andtriple modular redundancy (TMR) [10], [11], are often noteffective for small arrays in ULP systems operated at lowsupply voltages, due to their high complexity and the resultingperformance penalty. Technology solutions, such as silicon-on-insulator and other process techniques, can improve the datareliability but do not entirely solve the SEE problems, andoften high volume manufacturing is not feasible [12]. Previ-ously proposed bitcell solutions, such as the Dual Interlockedstorage Cell (DICE) [13], are designed for superthresholdoperation and fail when operated at low voltages.

In this paper, for the first time, a radiation tolerant bitcell,specifically designed for low-voltage operation, is proposed.The 13T dual-driven separated-feedback bitcell employs

1063-8210 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.


2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

several novel techniques to achieve robust SEU suppression,and is shown to tolerate upsets with charge deposits ashigh as 500 fC when operated at a scaled 500-mV supplyvoltage. Careful layout considerations were incorporated tofurther improve multiple-node strikes, while maintaining aunit cell size that is only 2× larger than a standard 6T staticrandom access memory (SRAM) bitcell, implemented in thesame 0.18-µm CMOS process. Extensive dynamic and staticanalyses were carried out to prove functionality and upsettolerance. Silicon measurements of a 32 × 32 (1 kb) memorymacro show full functionality down to 300 mV.

The rest of this paper is organized as follows. Section IIpresents the issue of SEUs in SRAM cells. Section IIIdescribes the design and architecture of the 13T bitcell.In Section IV, the radiation tolerance of the proposedbitcell is described, based on a unique self-correction mecha-nism. Section V presents the considerations in constructingthe bitcell layout, followed by test chip measurements inSection VI. Section VII concludes this paper.

The contributions of this paper are as follows.1) The proposed radiation-hardened bitcell is a pioneer

solution for embedded memories in low-power spaceapplications.

2) Implementation of SRAM arrays based on the proposedbitcell reduces area and power consumption by 30%compared with the common TMR approach.

3) The proposed solution shows high stability undervarying voltage and process parameter variations, an out-standing advantage over the conventional 6T SRAM cell.

4) High-radiation tolerance is achieved under scaledsupply voltages, into the subthreshold region.

5) The novel dual-driven separated-feedback mechanismis introduced and implemented, in order to improve thebitcell robustness.

II. STANDARD SRAM UNDER SEUs

SRAM blocks occupy the majority of the chip areaand are the primary contributors to leakage power inmany modern systems, including those intended for spaceapplications [14]–[16]. These trends lead to two majorconclusions. First, due to their static power consumption,scaling the supply voltage of the SRAM macros is an efficientmethod to reduce total chip power. Second, the probability ofa radiation strike on an SRAM bitcell is relatively high dueto the large area that the SRAM core occupies. Therefore,SRAM soft-error mitigation has become essential for robustsystem design.

The conventional 6T SRAM memory cell, shownin Fig. 1(a), utilizes an active feedback loop between twocross-coupled inverters in order to retain its stored data value.This structure of the SRAM cell is very sensitive to SEUs,as any upset that causes one of the data nodes to cross theswitching threshold of the adjacent inverter will result in a bitflip. When operating at low voltages, the switching thresholddecreases, thereby increasing the soft-error susceptibility ofthe circuit.

To demonstrate an SEU causing a failure in 6T SRAMbitcell, the following example will assume that an energetic

Fig. 1. (a) Conventional 6T SRAM cell. (b) Example of an SRAM bit flipcaused by an SEU.

particle strikes a circuit storing a logic 1 (Q = VDD andQB = 0 V). If the particle strikes the drain of the cutoffpMOS transistor, M3, charge will be generated, temporarilychanging the state of QB . For notation purposes, we will referto this type of positively charged strike as a 0 to 1 upset atnode QB , as opposed to a negatively charged strike, whichwe will refer to as a 1 to 0 upset at this node. Before thedeposited charge can be evacuated to the power supply throughthe conducting transistor of the feedback inverter (M1), thefeed-forward inverter (M2 and M4) switches and discharges Q.This, in turn, enforces the wrong state at QB , thereby latchingthe error into the memory cell, as shown in Fig. 1(b).

The amount of charge needed in order to exceed Qcrit istwo orders-of-magnitude smaller than the charge that can bedeposited by an energetic particle strike in space. Since Qcritdecreases with both voltage and technology scaling, bothof these trends impair the SEU tolerance of the SRAM.Therefore, the typical cross-coupled inverter structure cannotachieve sufficient radiation tolerance under low supplyvoltages. Considering static-noise margin as a baseline metricfor measuring the stability of an SRAM cell [17], simulationsshow that a typical 6T bitcell implemented in a 0.18-µmCMOS process and operated at 500 mV has ∼190 mV ofmargin. For this margin, a deposited charge of ∼3 fC canalready cause a bit failure. However, the charge generatedby a particle in space can reach up to several hundredsof femtocoulomb [4]. To overcome particle strikes of thismagnitude, an alternative cell topology must be considered.

III. PROPOSED 13T RADIATION TOLERANT BITCELL

A. Bitcell Design

SRAM design for low-voltage operation has becomeincreasingly popular in the recent past. Various bitcell designsand architectural techniques have been proposed to enableoperation deep into the subthreshold region [15], [18]–[21].These designs generally incorporate the addition of a numberof transistors into the bitcell topology, compared withthe baseline 6T SRAM bitcell, trading off density withrobust, low-voltage functionality. However, these bitcells weredesigned for operation under standard operating environments,and thereby, do not provide sufficient robustness to SEUsunder high-radiation conditions. In addition, the designarchitecture of these cells is based on the standard 6T cell;therefore, the 6T cell has the same hardening ability to most,if not all, these unprotected cells. As shown in Section II,the radiation hardening ability of the 6T cell is extremely low,


ATIAS et al.: LOW-VOLTAGE RADIATION-HARDENED 13T SRAM BITCELL 3

Fig. 2. Schematic of the proposed 13T radiation-hardened bitcell.

especially when compared with radiation hardening solutiondesigns.

The proposed bitcell is specifically designed to enablerobust, low-voltage, ULP operation in space applicationsand other high-radiation environments. This is achieved byemploying a dual-feedback, separated-feedback mechanismto overcome the increased vulnerability due to supply voltagescaling. The schematic representation of the proposed 13T bit-cell is shown in Fig. 2. The storage mechanism of this circuitcomprises five separate nodes: Q, QB1, QB2, A, and B ,with the acute data value stored at Q. This node is driven bya pair of CMOS inverters made up of transistors N3, P3, N4,and P4 that are, respectively, driven by the inverted data level,stored at QB1 and QB2. QB1 and QB2 are, respectively,driven to VDD or GND through devices P1, P2, N1, and N2that are controlled by the weak feedback nodes A and B thatare connected to Q through a pair of complementary devices(P5 and N5) gated by QB2. By driving the acute data levelby a pair of equipotentially driven, but independent, inverters,a strong, dual-driven feedback mechanism is applied withnode separation for SEU protection. This setup effectivelyprotects Q from an upset, while achieving a high criticalcharge at node Q, as shown in Section IV.

B. Storage Mechanism (Hold)

The proposed 13T bitcell features two stable states, repre-senting a logic 1 and a logic 0, defined as the voltage level atnode Q. The ON/OFF states of the devices and the resultingvoltage state at the internal nodes are shown in Fig. 3. Similarto a standard cross-coupled inverter structure, inverted voltagelevels are held at the internal data nodes. Starting with thelogic 1 state [Fig. 3(a)], the low level at QB2 enables Q tocharge A to VDD through P5, thereby cutting off P1 and P2 andeliminating any pull-up currents to QB1 and QB2. Leakagecurrents from the strongly driven Q node through N5 chargenode B , thereby turning ON N1 and N2 and enabling a

Fig. 3. Stable states of the 13T bitcell. For simplicity, devices N6–N8 wereomitted from this figure.

discharge path to assist in holding QB1 and QB2 at 0. Notethat both nodes A and B are driven to a predetermined levelduring the write operation, as described below, and thereforeare not reliant on the aforementioned leakage currents to setthe initial storage level of the cell.

An almost symmetric process occurs in the logic 0 state,as shown in Fig. 3(b). In this case, QB2 is high, allowing Bto discharge through N5 to Q and cutoff the pull-down pathsfrom QB1 and QB2 through N1 and N2, respectively. Anycharge stored at node A will leak through P5 to Q, enablingpull-up paths through P1 and P2 to QB1 and QB2 in order toreplenish any charge lost at these nodes.

C. Inherent SEU Tolerance

Two basic principles provide the proposed bitcell withinherent SEU tolerance.

1) The data are read out from node Q, such that anytemporary upset on other nodes can be tolerated.

2) The assisting nodes are designed with redundancyto ensure that any upset will be mitigated by theother nodes.

When a radiation strike causes a value change on any nodeof the bitcell, the other four internal nodes are designed, sothat the state change at this node cannot flip the cell and thedisruption is suppressed within a deterministic recovery time.For example, an upset at Q will quickly be suppressed throughthe dual-driven mechanism created by the internal inverters.Due to their separated nature, upsets at QB1 and QB2 willnot be able to change the state at Q and will return to theiroriginal state. Detailed analysis of these disruptions, as wellas every other possible node upset, is provided in Section IV.In addition, careful layout positioning considerations weretaken to protect the bitcell from multiple-node upsets (MNUs),as described in Section V.

D. Write Operation

Standard SRAM topologies, such as the 6T bitcell, writedata by driving the new level directly into the storage nodes,and therefore are required to overcome the circuit’s stronginternal feedback. In contrast to this method, the proposed cell



Fig. 4. Write stability demonstrated through 3-D phase portraits for bothwrite operations.

achieves writes by driving the weak feedback nodes (A and B),thereby removing much of the ratioed contention, inherent todirect access. A pair of write access transistors (N6 and N7)connect a unified write bitline (WBL) to nodes A and B . Thesedevices are controlled by a write wordline (WWL), such thatwhen WWL is raised, A and B are pulled toward the leveldriven upon WBL. This virtual connection between A and Bcreates inverters out of the transistor pairs of N1, P1 andN2, P2, driving QB1 and QB2 to the opposite level of WBL.Accordingly, the written data level is driven back to Q throughthe dual-driven feedback inverters, bringing the cell to a stablestate.

In order to demonstrate write stability of the proposedbitcell, Fig. 4 shows the 3-D phase portraits of both typesof write operations (write 0 and write 1) with VDD = 500 mV.These plots were assembled by initiating a write opera-tion under the assumption of any given initial state in the(QB1, QB2, and Q) state space. Write stability is achievedwhen only a single stable output state is possible for anyinitial condition, or more clearly, when all vectors convergeto the same point in the state space. This is the case forboth operations—the write 1 operation [Fig. 4(a)] converges to(0, 0, and 0.5 V), and the write 0 operation [Fig. 4(b)]converges to (0.5, 0.5, and 0 V), as required. Other thanthe fact that this characteristic ensures a successful writeoperation, it is also important in case of a particle strike duringthe write access, as the write will still succeed, even though

Fig. 5. Statistical MC simulations of writing 0 to cell 1 and 1 to cell 2 ona postlayout netlist.

Fig. 6. Distribution of write margin according to the WBL sweep method.1000 MC samples were taken at VDD = 500 mV.

the strike will move the cell to a different point in the statespace.

Writeability of the cell is further shown with dynamic stabil-ity simulations and write margin distribution according to theWBL sweep method [22]. Dynamic stability is shown in Fig. 5,showing successful write 0 and write 1 operations applied totwo separate cells and simulated over 1000 Monte Carlo (MC)samples on a postlayout netlist. The average duration of thesewrite operations is 8 ns for write 0 and 15 ns for write 1 withVDD = 500 mv. The write margin distribution of the cell atthis operating voltage is shown in Fig. 6 with a very robustmean of 219 mV and a standard deviation of 12.4 mV.

E. Read and Half Select

The proposed 13T bitcell features single-ended readoutthrough the read access transistor (N8). This device iscontrolled by a separate read wordline and connected to acolumn-shared read bitline that is precharged prior to theread operation and conditionally discharged, depending onthe voltage stored at Q. Due to the dual-driven feedback thatdrives Q to its stable value, this read operation is both morerobust and faster than the read operation of standard SRAMbitcells. Read failures in 6T SRAM cells occur when theaccess transistor is stronger than the pull-down transistor dueto local variations. However, the proposed cell employs a pair



Fig. 7. Half-select functionality for both, storing 1 (cell 1) andstoring 0 (cell 2), cases.

of pull-down transistors (N3 and N4), which significantlydecrease the probability of such a read failure, enabling robustoperation at low voltages. In addition, these two devices alsoprovide a lower resistance pull-down path to achieve a fasterbitline discharge. The separated read and write ports alsoprovide two-ported functionality, often required in memorymacros, such as those used for register files.

The majority of the previously proposed bitcells fea-turing a single-ended read, such as the standard two-port8T SRAM cell, suffer from susceptibility to half-select fail-ures. Half-select situations occur during write operations whenonly some of the bits that share the same wordline are to bewritten. In a standard 6T SRAM cell that shares wordlinesand bitlines for both read and write operations, biasing thebitlines for a read operation ensures that the cell will notbe written to. However, as read margin is often the limitingfactor in supply voltage scaling, single-ended readout is oftenused as an alternative to the standard differential readout.This either leaves the cell susceptible to half-select failuresor eliminates the option of partial row writes—a real problemif bit-interleaving is desired for minimizing the probability ofmultiple-bit failures.

In the case of the proposed cell, a half-select situation willindeed occur during a partial row write. However, due tothe strong, dual-driven feedback mechanism and the indirectwrite operation through the weak feedback nodes, the cellprovides robust half-select stability. During a bit-masked writeoperation, the tristate WBL drivers of the nonselected cellsare set to their high-impedance state, floating the bitlines. In aworst case situation, during which the nonselected WBL isdriven to the opposite level than that stored in the cell priorto the half-select cycle, the floating charge will be dischargedthrough Q without causing a bit flip. This is shown in Fig. 7for 1000 MC samples at VDD = 500 mV. Fig. 7 shows twocells in the same row, storing 1 and 0, respectively, underworst case half-select situations. Each WBL was initialized atthe voltage opposite to that stored in its bitcell, and at theonset of a write operation (rising-edge of WWL), the WBLswere floated. In all cases, only a slight disrupt can be seenon Q, and this is quickly suppressed as the bitline charge isdischarged through A and/or B to Q.

To summarize and demonstrate the cell operation describedin this section, representative write, read, and upsetsuppression events are shown in Fig. 8 with a 500-mV supply

voltage. In this scenario, a 1 is written into a cell initially stor-ing a 0, followed by a 1-pC particle strike that discharges Q toa negative voltage. This upset is quickly mitigated, such thatthe subsequent read operation outputs the correct data. A sim-ilar sequence follows with a 0 written into the cell, followedby a 0 to 1 upset at QB1 and a subsequent read operation.This strike is also mitigated, resulting in a correct readout.

IV. SEU TOLERANCE

A. Disrupt Modeling

The proposed 13T bitcell was designed for robust, upsettolerant operation in a high-radiation environment, such as thatencountered by space applications. When a particle strike, thecharacteristic of such an environment, passes through a semi-conductor material, a disrupt occurs due to the drift currentof the generated e–h pairs in a reverse-biased p-n junction.If the particle hits an unbiased junction, the generated e–hpairs will spontaneously recombine and not induce a currentpulse due to the absence of an electric field. However, a strikeon a reverse-biased junction causes a transient current [I (t)]at the connected node, characterized by a fast rise time anda gradual fall time. This current can be modeled according tothe double-exponential model [23]

I (t) = Qcoll

t f − tr

(e− t

t f − e− ttr

)(1)

where Qcoll is the charge collected due to the particle strike,tr is the rise time, and t f is the fall time. Qcoll depends onthe type of the ionizing particle, trajectory, energy value, andimpact location. The technology-dependent rise and fall timeswere taken as 10 and 200 ps, respectively, for the considered0.18-µm process [3]. The critical charge is calculated fromthe numerical integration of the injected current pulse thatcauses a bit flip. Section IV-B describes the describes thebitcell tolerance to a 500-fC disruption at each cell node forrelevant standby states.

B. Disrupt Tolerance

The multiple internal nodes of the proposed 13T circuitand the possibility of strikes of both positive and negativepolarities require an analysis of each type of strike to evaluatedisrupt tolerance. As previously mentioned, a correct readoutonly requires the data to be stable at node Q, and therefore,it is sufficient to consider the voltage at this node for such anevaluation. Fig. 9 shows the reaction of the storage node, Q,to particle strikes at each of the internal nodes of the proposedbitcell. A typical 500-fC strike with VDD = 500 mV is shownfor every node, and where applicable, the reaction to bothpositive and negative charge strikes is shown. Note that thereare no plots shown for a negative upset at node A or a positiveupset at node B , as there is no reversed-biased p-n junctionconnected to these nodes in the respective standby states. Theinsets of each subfigure show the results of 1000 MC samplesfor this type of particle strike, all resulting in a successfulrecovery. The recovery mechanisms that successfully enablethe cell to recover and retain its initial state for every possibleupset are described hereafter.



Fig. 8. Subsequent write-upset-read events, demonstrating quick cell recovery. The waveforms were plotted for a 500-mV supply voltage with the particleenergies of 1 pC.

1) 0 to 1 Upset at Q: Following a positive particlestrike at node Q while holding 0 [Fig. 9(a)], both QB1and QB2 remain high, quickly discharging the injectedcharge through N3 and N4. During this upset event, B startsto charge through N5, enabling N1 and N2 to dischargeQB1 and QB2. However, since P5 remains in cutoff, A stayslow, causing P1 and P2 to successfully combat the dischargeof QB1 and QB2 until the injected charge to Q has beendischarged.

2) 1 to 0 Upset at Q: Following a negative particle strikeat node Q while holding 1 [Fig. 9(b)], both QB1 and QB2remain low, quickly replenishing the lost charge at Q throughP3 and P4. During upset event, A starts to discharge throughP5, enabling P1 and P2 to charge QB1 and QB2. However,since N5 remains in cutoff, B stays high, causing N1 and N2to successfully combat the charge of QB1 and QB2 until Qhas fully recovered. However, note that as shown in Fig. 8,a 1 to 0 upset at Q causes node B to switch from 1 to 0.This phenomenon occurs due to a higher than typical energeticparticle strike, which was intentionally used in this simulationto demonstrate the cell recovery capability. In cases of highlyenergetic particles, the double-exponential model of (1) canoften cause the voltage to drop below 0. In this example,the voltage of Q drops below 0, and therefore, even thoughthe gate potential of N5 remains at 0, transistor N5 is nowconducting, since the difference between the gate potential andthe drain terminal of this transistor (node Q) is greater thanthe threshold voltage of N5. However, even in this worst casescenario of a drastic voltage drop in the storage node, Fig. 8shows that the proposed cell is resilient and able to recover.

3) 0 to 1 Upset at QB1: A positive strike at QB1 in a hold 1state [Fig. 9(d)] will enable N3 to attempt to discharge Q.However, P4 will remain ON, as QB2 is not affected, therebylimiting the temporary voltage drop at Q. The 0 level storedat QB2 also keeps N5 cutoff N5, maintaining the level of Bhigh. Therefore, N1 is able to discharge the current that wasinjected into QB1, as P1 is cutoff due to the high level storedon A.

4) 1 to 0 Upset at QB1: A negative strike at QB1 in ahold 0 state [Fig. 9(c)] will enable P3 to attempt to charge Q.Combating this operation is N4, limiting the temporary voltagerise at Q, as QB2 is not affected and retains its high state.In addition, the 1 level stored at QB2 cuts off P5, such thatthe level of A remains low. Therefore, P1 is able to replenishthe lost charge at QB1, while N1 is cutoff due to the low levelstored at B .

5) 0 to 1 Upset at QB2: A positive strike at QB2 in a hold 1state [Fig. 9(f)] will enable N4 to attempt to discharge Q.Combating this operation is P3, limiting the temporary voltagefall on Q, as QB1 is not affected. Since QB2 switches itsvalue to 1, it cuts off P5, maintaining the level of A high toensure that P1 and P2 remain close to keep QB1 and QB2low. During this operation, B starts to discharge through N5,closing N1 and N2. Since the two inverters are combatingeach other, B would not completely close N1 and N2, andthis results a quickly discharge of QB2 back to 0. Since QB1was always at 0, Q will charge back to 1.

6) 1 to 0 Upset at QB2: A negative strike at QB2 in ahold 0 state [Fig. 9(e)] will enable P4 to attempt to charge Q.Combating this operation is N3, limiting the temporary voltage



Fig. 9. Behavior of node Q under all possible SEUs with charge deposit of 500 fC and VDD = 500 mV. Insets: results of 1000 MC simulations.

rise on Q, as QB1 is not affected. Since the value of QB2changed to 0, A starts to charge to 1 through P5 closingP1 and P2. However, since N5 is in cutoff, B stays low, to

ensure that N1 and N2 remain close keeping the charge storedat QB1 to successfully combat the charge of Q by evacuatingthe injected charge through N3.



TABLE I

Qcrit OF BITCELL NODES

7) 1 to 0 Upset at A: Following a negative particle strikeat node A while holding 0 [Fig. 9(g)] will cut off P1 and P2.However, both QB1 and QB2 remain high, and therefore,P5 stays cutoff to prevent this upset from affecting Q. Thevoltage at Q is only able to rise up to 70 mV and is quicklydischarge through N3 and N4. The cell data are alwaysavailable during this upset event. A would start to dischargedue to leakage currents through P5, reenabling P1 and P2 tokeep QB1 and QB2 charged. B is not affected during thisupset.

8) 0 to 1 Upset at B: Following a positive particle strike atnode B while holding 1 [Fig. 9(h)], N1 and N2 will both becutoff. However, both QB1 and QB2 remain low, and there-fore, N5 stays cutoff, preventing this upset from affecting Q.The voltage at Q drops to a lowest limit of 200 mV, andits level is quickly replenished through P3 and P4. After thisupset event, B would start to charge due to leakage currentsthrough N5, reenabling N1 and N2 to keep QB1 and QB2discharged. A is not affected during this upset.

C. Recovery Time and Critical Charge

Two important parameters to evaluate the tolerance of abitcell for particle strikes when operating in a high-radiationenvironment are recovery time and critical charge. The recov-ery time is the time it takes Q to return to its correct readabledata value following a particle strike, while critical charge, aspreviously defined, is the minimum charge required to causea bit flip. Whereas a particle strike of a magnitude largerthan the critical charge is destructive and will lead to anincorrectly stored data level, recovery time only characterizes atemporal state, but can lead to an access failure if a subsequentread is performed in close proximity to a disrupt. The jointconsideration of both parameters is essential to ensure reliablefunctionality under SEUs.

The recovery time of the proposed bitcell was extractedfrom the simulations shown in Fig. 9 for each one of thepossible node upsets. The resulting mean recovery time wasfound to be approximately two orders-of-magnitude shorterthan the previously proposed DICE solution under the samesupply voltage [13]. Similarly, Qcrit was extracted for eachnode and disrupt polarity, as shown in Table I. Accordingly,Qcrit of the bitcell can be defined as 500 fC, the minimumextracted value. In comparison with other bitcell solutions,designed in the same 0.18-µm CMOS process, Qcrit of theproposed circuit is two orders-of-magnitude larger than otherSRAM solutions [24]–[27], and is at the same order-of-magnitude as the DICE solution operated at a 500-mV supplyvoltage.

To demonstrate the reaction to various induced chargemagnitudes, Fig. 10 shows positive strikes at node Q with

Fig. 10. Bitcell behavior under 1 to 0 SEUs at node Q with varying chargedeposits under (VDD = 500 mV).

Fig. 11. Behavior of node Q under a particle strike on node QB2 in 65-nmtechnology. Results of 1000 MC simulations.

several particle energies, showing tolerance to charge depositsas high as 1 pC under a 500-mV supply. This plot also showsthat the recovery time increases with the particle energy. Fig. 8also shows the reaction to a 1-pC positive strike—first atnode Q, and subsequently at node QB . This example clearlyshows the quick recovery of the cell, enabling a correct readoutduring the following cycle. Note that the cell is not sensitiveto SEUs during a write operation, since at this time, the accesstransistors are conducting and the values at A and B arestrongly held by the bit lines, as described in Section III.

The process technology node of the proposed cell waschosen according to the specifications and requirements ofthe targeted space and military applications, which mostoften require very mature technologies. However, the proposedbitcell architecture is fully compatible with technology scaling,as shown in Fig. 11 for a 65-nm CMOS technology. Fig. 11shows the recovery of node Q in the worst case scenariosof a particle strike on node QB2. The robustness of the cellunder process variations, demonstrated through statistical MCsimulations, suggests that its radiation hardening capabilitiesare maintained under technology scaling.



Fig. 12. Bitcell layout.

V. LAYOUT CONSIDERATIONS

Standard SRAM bitcells, intended for high-density integra-tion, give the highest priority to minimum area layout, oftentrading off size for stability and performance. However, whendesigning a cell for high-radiation environments, silicon areaoften takes a step back in favor of stability and soft-errorsuppression. Accordingly, one of the most simple and efficientsolutions that has been proposed to mitigate SEUs is the TMRsolution, which utilizes three identical memory arrays and avoting circuit to decide on the correct readout. This solutionclearly comes at a high area penalty—at least tripling the sizeof a standard SRAM block. Ultimately, such a heavy areaoverhead limits the memory integration density. Therefore, inthe design of the proposed circuit, one of the goals was toprovide a significant area benefit, as compared with a similarsized TMR block.

The proposed layout for the 13T bitcell is shown in Fig. 12,presenting a unit size of 7.5 µm × 4 µm, which is approxi-mately 2× larger than a standard 6T SRAM cell in the sametechnology process (0.18 µm) designed with standard rules.Note that the majority of industry standard SRAM macros arebased on pushed-rule bitcells, which provide a significantlyreduced cell area. However, this also results in increasedsensitivity to soft errors, including the MNU rate of the cell,making a pushed-rule bitcell a very bad candidate for radiationhardening. Therefore, the vast majority of radiation-hardenedcircuits are designed with standard rules.

The reduced size of the proposed cell in comparison with theTMR solution was achieved by implementing a single n-well

per cell, placing all pMOS devices in a single row and sharingdiffusion through abutment, wherever possible. However, nodepositioning had to be considered, as well, in order to reducethe probability of multiple-node disrupts.

A single high-energy particle strike can disrupt severalnodes simultaneously, especially if the proximity between thenodes is small. However, as previously explained, a transientcurrent pulse will only occur if the particle hits a reverse-biased p-n junction. Therefore, by separating nodes that maybe simultaneously reverse-biased, the probability of a bitcellfailure can be significantly reduced. The layout of the proposedbitcell was designed, such that every pair of these sensitivenodes is separated either by distance or by placing an unbiasedjunction in between them. For example, in a logic 1 state,the two sensitive nodes, QB1 and QB2, in the pMOS row atthe top of the unit cell are equal to 0; hence, both nodes arereverse-biased. Therefore, an unbiased junction was positionedbetween them for protection. If a particle hits the QB1 pMOSjunction (top left in Fig. 12), the unbiased diffusions of transis-tors P3 and P4, connected to VDD and to Q, respectively, willblock this upset from reaching the second sensitive reverse-biased node, QB2. The same separation was also implementedfor the sensitive nodes in the nMOS row at the bottom of thecell, since at any given time, only one of the storage nodes,Q or QB1/QB2, will be reverse-biased. As such, for any holdstate of the cell, a sensitive node is protected by an unsensitivenode. In addition, nodes A and B are separated by distancefrom the storage nodes.

While the cell functionality and radiation hardeningdescribed in Section IV can be achieved with minimum-sizedtransistors, the layout considerations and design, describedabove, leave room for slight increases in transistor widthswithout resulting in an overall increase in a cell area. Thisfeature was exploited to reduce the cell recovery time byupsizing transistors P3 and N2, as shown in Fig. 12.

VI. TEST CHIP IMPLEMENTATION AND MEASUREMENTS

A 32 × 32 bit (1 kb) memory macro based on the proposedcell was designed and integrated into a 0.18-µm test chip.All devices were implemented with standard VT transistors toprovide complete logic process compatibility. The test chipwas designed to enable three primary test modes: 1) full,at speed testing using an integrated built-in-self-test (BIST);2) complete array control through a serial scan chain config-uration; and 3) single-cycle external direct access to a portionof the array. The test chip also included a 2-kb compiledSRAM for data comparison and several other test components.The BIST incorporates a finite-state machine for rigorous,at-speed testing, utilizing an on-chip SRAM for comparisonof the data written to the custom array with the subsequentreadout values. These three test configurations were used totest the functionality of the array and provide the presentedmeasurement data.

A micrograph of the bonded test chip is shown in Fig. 13along with the layout of the entire chip and an enlarged imageof the 13T array layout. In order to test the cell’s functionalityunder scaled voltage supplies, the radiation-hardened SRAM



Fig. 13. Full chip layout and the 13T cell memory array.

Fig. 14. Combined shmoo plot of the minimal memory supply voltage as afunction of the maximal operating frequency, for 12 measured chips.

array was biased by a separate, low-voltage supply, (MVDD),keeping the digital voltage supply (VDD) at a nominal levelto ensure proper functionality of the BIST, compiled SRAM,and other digital peripheral circuits of the test chip. In order totest the impact of process variations, 12 dies were measured,all of which were operated successfully over the full range ofsupply voltages, from 300 mV to 1.8 V.

Fig. 14 shows the maximum measured frequency of thetest chips across the range of supply voltages. This resultis emphasized in Fig. 15, showing the average measuredfrequency for each supply voltage in black. All measurementswere taken at room temperature. As expected, the performanceexponentially degrades as the voltage is scaled. However,the array maintains functionality for write and read atVDD = 300 mV for all packaged test chips. The measurementof maximum frequency was limited by the test setup andperiphery, which was designed for low-frequency ULPapplications and not optimized for high-speed measurements.

In addition to the area savings of the proposed topology,as compared with an alternative TMR solution, a significantimprovement is also achieved in static power consumption.Fig. 16 shows the average leakage power per bit for eachof the packaged test chips with the average consumptionemphasized in black. For comparison, the leakage of a TMRbit is displayed as a dashed line, consuming approximately

Fig. 15. Measured frequency versus VDD.

Fig. 16. Measured hold leakage power versus MVDD.

3× higher power than the proposed bitcell across the entireoperating range. This is without taking into consideration thepower of the specialized peripheral circuits that the TMRsolution would require in order to continue to function at sucha low operating voltage.

VII. CONCLUSION

This paper proposed a 13T SRAM bitcell, designed forrobust, low-voltage, ULP operation in high-radiation envi-ronments, such as those encountered by space applications.The proposed circuit displays a novel dual-driven separated-feedback mechanism to achieve high soft-error tolerance, forrobust operation down to 300 mV. Particle strike suppressionaccording to the double-exponential model was tested acrossstatistical MC simulations on a postlayout netlist for everytype of disrupt event, showing tolerance to upsets with themagnitudes of up to 500 fC at a scaled, 500-mV operatingvoltage. Layout techniques were implemented in order todecrease SEU probability, while maintaining a bitcell areamuch smaller than alternative solutions, such as the previouslyproposed TMR, resulting in a unit cell area only 2× largerthan a standard 6T bitcell in the same process. A 1-kb test chipwas designed, fabricated, and tested, showing full functionalityover a large range of operating voltages, providing averageleakage power consumption of less than 5 pW per bit at300 mV—over 3× lower than alternative proposals.



REFERENCES

[1] A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-ThresholdDesign for Ultra Low-Power Systems (Series on Integrated Circuits andSystems). Secaucus, NJ, USA: Springer-Verlag, 2006.

[2] S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht, andA. Fish, “Digital subthreshold logic design—Motivation and challenges,”in Proc. IEEE Conv. Elect. Electron. Eng. Israel (IEEEI), Dec. 2008,pp. 702–706.

[3] T. Heijmen, D. Giot, and P. Roche, “Factors that impact the criti-cal charge of memory elements,” in Proc. IEEE Int. On-Line Test.Symp. (IOLTS), Jul. 2006, pp. 1–6.

[4] R. C. Baumann, “Radiation-induced soft errors in advanced semicon-ductor technologies,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3,pp. 305–316, Sep. 2005.

[5] T. Karnik and P. Hazucha, “Characterization of soft errors caused bysingle event upsets in CMOS processes,” IEEE Trans. DependableSecure Comput., vol. 1, no. 2, pp. 128–143, Apr./Jun. 2004.

[6] P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling ofsingle-event upset in digital microelectronics,” IEEE Trans. Nucl. Sci.,vol. 50, no. 3, pp. 583–602, Jun. 2003.

[7] P. E. Dodd and F. W. Sexton, “Critical charge concepts for CMOSSRAMs,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1764–1771,Dec. 1995.

[8] C. Detcheverry et al., “SEU critical charge and sensitive area in asubmicron CMOS technology,” IEEE Trans. Nucl. Sci., vol. 44, no. 6,pp. 2266–2273, Dec. 1997.

[9] J. L. Barth, C. S. Dyer, and E. G. Stassinopoulos, “Space, atmospheric,and terrestrial radiation environments,” IEEE Trans. Nucl. Sci., vol. 50,no. 3, pp. 466–482, Jun. 2003.

[10] M. A. Bajura et al., “Models and algorithmic limits for an ECC-basedapproach to hardening sub-100-nm SRAMs,” IEEE Trans. Nucl. Sci.,vol. 54, no. 4, pp. 935–945, Aug. 2007.

[11] L. Sterpone and M. Violante, “Analysis of the robustness of the TMRarchitecture in SRAM-based FPGAs,” IEEE Trans. Nucl. Sci., vol. 52,no. 5, pp. 1545–1549, Oct. 2005.

[12] E. H. Cannon, D. D. Reinhardt, M. S. Gordon, and P. S. Makowenskyj,“SRAM SER in 90, 130 and 180 nm bulk and SOI technologies,” inProc. IEEE Int. Rel. Phys. Symp., Apr. 2004, pp. 300–304.

[13] T. Calin, M. Nicolaidis, and R. Velazco, “Upset hardened memory designfor submicron CMOS technology,” IEEE Trans. Nucl. Sci., vol. 43, no. 6,pp. 2874–2878, Dec. 1996.

[14] ITRS. (2013). International Technology Roadmap for Semiconductors—2013 Edition. [Online]. Available: http://www.itrs.net

[15] B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm sub-thresholdSRAM design for ultra-low-voltage operation,” IEEE J. Solid-StateCircuits, vol. 42, no. 3, pp. 680–688, Mar. 2007.

[16] B. H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling andsizing for minimum energy operation in subthreshold circuits,” IEEEJ. Solid-State Circuits, vol. 40, no. 9, pp. 1778–1786, Sep. 2005.

[17] E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysisof MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. 22, no. 5,pp. 748–754, Oct. 1987.

[18] A. Teman, L. Pergament, O. Cohen, and A. Fish, “A 250 mV 8 kb40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM),” IEEEJ. Solid-State Circuits, vol. 46, no. 11, pp. 2713–2726, Nov. 2011.

[19] J. Mezhibovsky, A. Teman, and A. Fish, “Low voltage SRAMs andthe scalability of the 9T supply feedback SRAM,” in Proc. IEEE Int.Syst.-Chip Conf. (SOCC), Sep. 2011, pp. 136–141.

[20] N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T subthresholdSRAM employing sense-amplifier redundancy,” IEEE J. Solid-StateCircuits, vol. 43, no. 1, pp. 141–149, Jan. 2008.

[21] I. J. Chang, J.-J. Kim, S. P. Park, and K. Roy, “A 32 kb 10Tsub-threshold SRAM array with bit-interleaving and differential readscheme in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 2,pp. 650–658, Feb. 2009.

[22] J. Wang, S. Nalam, and B. H. Calhoun, “Analyzing static and dynamicwrite margin for nanometer SRAMs,” in Proc. ACM/IEEE Int. Symp.Low Power Electron. Design (ISLPED), Aug. 2008, pp. 129–134.

[23] G. R. Srinivasan, P. C. Murley, and H. K. Tang, “Accurate, predictivemodeling of soft error rate due to cosmic rays and chip alpha radiation,”in Proc. IEEE Int. Rel. Phys. Symp., Apr. 1994, pp. 12–16.

[24] S. M. Jahinuzzaman, D. J. Rennie, and M. Sachdev, “A soft error tolerant10T SRAM bit-cell with differential read capability,” IEEE Trans. Nucl.Sci., vol. 56, no. 6, pp. 3768–3773, Dec. 2009.

[25] J. S. Shah, D. Nairn, and M. Sachdev, “A soft error robust 32 kbSRAM macro featuring access transistor-less 8T cell in 65-nm,” inProc. IEEE/IFIP Int. Conf. VLSI Syst.-Chip (VLSI-SoC), Oct. 2012,pp. 275–278.

[26] Y. Shiyanovskii, F. Wolff, and C. Papachristou, “SRAM cell design usingtri-state devices for SEU protection,” in Proc. IEEE Int. On-Line Test.Symp. (IOLTS), Jun. 2009, pp. 114–119.

[27] N. Axelos, K. Pekmestzi, and N. Moschopoulos, “A new low-powersoft-error tolerant SRAM cell,” in Proc. IEEE Comput. Soc. Annu. Symp.VLSI (ISVLSI), Jul. 2010, pp. 399–404.

Lior Atias received the B.Sc. (magna cum laude)degree in electrical engineering from Ben-GurionUniversity, Be’er Sheva, Israel, in 2013, and theM.Sc. degree from Ben-Gurion University, in 2014,as part of a fast-track program for outstanding stu-dents.

He is currently a Design and Verification Engi-neer with Mellanox Technologies, Tel Aviv, Israel.His current research interests include digital radia-tion hardened circuits design for low-power spaceapplications, low-voltage embedded memories, and

SRAM design with an emphasis on improved stability.

Adam Teman received the B.Sc. degree in electricalengineering and the M.Sc. degree from Ben-GurionUniversity (BGU), Be’er Sheva, Israel, in 2006 and2011, respectively, and the Ph.D. degree from theVLSI Systems Center, BGU, in 2014, under Prof.A. Fish, as a part of the Low Power Circuits andSystems Laboratory.

He was a Design Engineer with Marvell Semicon-ductors, Petah Tikva, Israel, from 2006 to 2007, withan emphasis on physical implementation. From 2014to 2015, he was a Post-Doctoral Researcher with

the Telecommunications Circuits Laboratory, École Polytechnique Fédéralede Lausanne, Lausanne, Switzerland, under a Swiss Government ExcellenceScholarship. In 2015, he joined the Faculty of Engineering, Bar-Ilan Uni-versity, Ramat Gan, Israel, in 2015, as a Tenure Track Researcher with theDepartment of Electrical Engineering and as a Partner with the EmergingNanoscaled Integrated Circuits and Systems Laboratories Research Center.His current research interests include low-voltage digital design, energy-efficient SRAM, NVM, and eDRAM memory arrays, low-power CMOS imagesensors and low-power design techniques for digital and analog VLSI chips,energy-efficient digital system implementation, approximate computing, andsignificance driven computing for reliability and power optimization. He hasauthored over 40 scientific papers and three patent applications, and haspresented excerpts from his research at a number of international conferences.

Dr. Teman was honored with the Electrical Engineering Department’sTeaching Excellence recognition at Ben-Gurion University in 2010-2012,and in 2011, he received the Outstanding Project Award at BGU. Hereceived the Yizhak Ben-Ya’akov HaCohen Prize in 2010, the BGU Rector’sPrize for Outstanding Academic Achievement in 2012, the Wolf FoundationScholarship for Excellence of 2012, and the Intel Prize for Ph.D. Studentsin 2013. His doctoral studies were conducted under a Kreitman FoundationFellowship. He is also an Associate Editor of the Microelectronics Journaland a member of the technical and review boards of several conferences andjournals.

Robert Giterman received the B.Sc. degree inelectrical engineering from Ben-Gurion University,Be’er Sheva, Israel, in 2013, and the M.Sc. degreefrom Ben-Gurion University, in 2014, as a partof a fast-track program for outstanding students.He is currently pursuing the Ph.D. degree, underProf. A. Fish, as part of the Emerging NanoscaledIntergrated Circuits and Systems Laboratory at Bar-Ilan University, Ramat Gan, Israel.

His current research interests include embeddedDRAM design and optimization for low-power and

high-performance operation, SRAM design with an emphasis on improvedstability, error-correction and fault-tolerant circuits, and development of mul-tilevel embedded memories for use in low-power applications and high-endprocessors.



Pascal Meinerzhagen received the B.Sc., M.Sc.,and Ph.D. degrees from the École PolytechniqueFédérale de Lausanne (EPFL), Lausanne, Switzer-land, in 2014, 2008, and 2006, respectively, all inelectrical engineering, and the joint M.Sc. degree inmicro and nanotechnologies for integrated systemsfrom Grenoble INP, Grenoble, France, Politecnico diTorino, Turin, Italy, and EPFL, in 2008.

He was a Post-Doctoral Fellow and a Lecturerwith Bar-Ilan University, Ramat Gan, Israel, in 2014,where he established the Advanced Digital VLSI

Design course. He is currently a Senior Research Scientist with Intel Laborato-ries, Intel Corporation, Hillsboro, OR, USA, and a Visiting Lecturer with Bar-Ilan University. His current research interests are broad, ranging from energy-efficient and error-resilient circuits and systems in high-performance FinFETCMOS technologies, to power delivery and power management techniques, toconventional and emerging memory circuits, to ultralow power VLSI. He hasauthored or co-authored two invited book chapters, 27 peer-reviewed journalarticles, and international conference papers, and holds four pending patents.

Dr. Meinerzhagen received an Intel Ph.D. Fellowship and two best papernominations. He is a Reviewer of 16 international journals and conferences,including the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART

I, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II, theIEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS ANDSYSTEMS, and the IEEE Symposia on VLSI Technology and Circuits.

Alexander Fish received the B.Sc. degree in elec-trical engineering from Technion–Israel Institute ofTechnology, Haifa, Israel, in 1999, and the M.Sc. andPh.D. (summa cum laude) degrees from Ben-GurionUniversity (BGU), Be’er Sheva, Israel, in 2002 and2006, respectively.

He was a Post-Doctoral Fellow with the ATIPSLaboratory, University of Calgary, Calgary, AB,Canada, from 2006 to 2008. In 2008, he againjoined BGU, as a Faculty Member with the Electricaland Computer Engineering Department, where he

founded the Low Power Circuits and Systems Laboratory, specializing in low-power circuits and systems. In 2011, he was appointed as a Head of the VLSISystems Center at BGU. In 2012, he joined Faculty of Engineering, Bar-IlanUniversity, as an Associate Professor, and the Head of the NanoelectronicsTrack. He also leads new Emerging Nanoscaled Integrated Circuits andSystems Laboratories. His current research interests include development ofsecured hardware, ultralow-power embedded memory arrays, CMOS imagesensors, and high-speed and energy-efficient design techniques. He hasauthored over 100 scientific papers in journals and conferences, includingthe IEEE JOURNAL OF SOLID STATE CIRCUITS, the IEEE TRANSACTIONSON ELECTRON DEVICES, the IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS, and many others. He also submitted 22 patent applications. Hehas authored two book chapters.

Prof. Fish is a member of Sensory, VLSI Systems and Applications, andBio-medical Systems Technical Committees of the IEEE Circuits and SystemsSociety. He was a co-author of papers that won the best paper finalist awardsat the IEEE ISCAS and ICECS conferences. He serves as the Editor in Chieffor the MDPI Journal of Low Power Electronics and Applications and anAssociate Editor of the IEEE SENSORS, IEEE ACCESS, Microelectronicsand Integration (Elseiver), and VLSI Journals. He also served as a Chairof different tracks of various IEEE conferences. He was a Co-Organizer ofmany special sessions at the IEEE conferences, including IEEE ISCAS, IEEESENSORS, and IEEE conferences.

Documents

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI ... · OWER dissipation is one of the most important aspects of current nanoscale VLSI design. Ultralow power (ULP) operation