Ultralow-Voltage Process-Variation-TolerantSchmitt-Trigger-Based SRAM Design

Abstract

• Portable electronic devices have extremely low power requirement to maximize the battery lifetime.

• Various architectural-level techniques have been implemented to minimize the power consumption in SRAMs .

• We propose a Schmitt-Trigger (ST)-SRAM cell to increase the read/write stability under large variations.

Introduction • SRAM is an important part of modern microprocessor design,

taking a large portion of the total chip area and power. • Increasing the density of SRAM caches provides an affective

method to enhance system performance.• Several SRAM bitcells have been proposed having different

design goals such as bit density, bitcell area, low voltage operation and architectural timing specifications.

• In all of the previously reported bitcells, the basic element for the data storage is a cross-coupled inverter pair.

• Extra transistors are added to decouple the read and write operations.

introduction• There are many reasons to use an SRAM or a DRAM in a

system design. • Design tradeoffs include density, speed, volatility, cost, and

features. • All of these factors should be considered before you select a

RAM for your system design.• Speed The primary advantage of an SRAM over a DRAM is

its speed. • Different SRAM designs have previously been presented that

use from 6 to 10 transistors to provide reliable and/or low power operation.

Nmos

• N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits.

• NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation.

• The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage.

Nmos

• The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.

Symbol:

Pmos

• P-type metal-oxide-semiconductor logic uses p-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation.

• The p-type MOSFETs are arranged in a so-called "pull-up network" (PUN) between the logic gate output and positive supply voltage, while a resistor is placed between the logic gate output and the negative supply voltage.

• The circuit is designed such that if the desired output is high, then the PUN will be active, creating a current path between the positive supply and the output.

Pmos

• The circuit is designed such that if the desired output is high, then the PUN will be active, creating a current path between the positive supply and the output.

Symbol:

DCSH

• DSCH is software for logic design. Based on primitives, a hierarchical circuit can be built and simulated. It also includes delay and power consumption evaluation.

• Silicon is for 3D display of the atomic structure

of silicon, with emphasis on the silicon lattice, the dopants, and the silicon dioxide.

Microwind

• Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator.

• The Microwind program allows designing and simulating an integrated circuit at physical description level.

• The package contains a library of common logic and analog ICs to view and simulate. Microwind includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, Verilog compiler, tutorial on MOS devices).

Conti……

• None of the previously reported bitcells incorporate process variation tolerance for improving the stability of the cross coupled inverter pair of an SRAM bitcell operating at ultralow supply voltage

• Hence, we need a different design approach for successful low voltage SRAM design in nanoscaled technologies

• we propose Schmitt Trigger based SRAM bitcell having built-in feedback mechanism that exhibits the process variatio

tolerance.This robust process tolerance can be an essential attribute for

SRAM scaling into future nanoscaled technology nodes

Conventional 6T-SRAM cell

Cont…• It consists of a cross-coupled inverter pair that does data

storage• Two access transistors to load/retrieve data on bit lines, BL and

BLB.• basic operations that one can perform on SRAM cell 1. read, 2. write 3. hold.Hold operation • When the cell is not selected(wl=0) for read or write, it is

expected to hold the data stored in it.

Cont…..

Read operation.• cell is selected by raising WL to high• both bitlines are first precharged high. • Based on the data stored in the cell, one of the bitlines is• discharged.• This change is detected by a sense amplifier (which is not

part of the cell) to determine the value stored in the cell.

Write operation• cell is selected by raising WL to high• depending on the value to be written to the cell one of the

bitlines is raised high and the other is lowered. .

drawback• In existing system a conventional 6T-SRAM has a poor read

stability due to constraint design requirements, and can suffer functional failures due to high threshold voltage variations

• Statistical variability arising from the discreteness of charge and matter is a major source of threshold variation that degrades the reliability of conventional SRAM design.

• A conventional 6T-SRAM cell provides poor read stability since the access transistors provide direct access to the cell storage during a read operation.

 

PROPOSED SYSTEM

SCHMITTTRIGGER (ST) SRAM BITCELLS• In order to resolve the conflicting read versus write design

requirements in the conventional 6T bitcell, we apply the Schmitt Trigger (ST) principle for the cross-coupled inverter pair

• Schmitt trigger is used to modulate the switching threshold of an inverter depending on the direction of the input transition

• In the proposed ST SRAM bitcells, the feedback mechanism is used only in the pull-down path.

Conceptual ST schematics

Cont…..

During 0 1 input transition• Here feedback transistor (NF) tries to preserve the logic “1” at

output (Vout ) node by raising the source voltage of pull-down nMOS (N1).

• This results in higher switching threshold of the inverter with very sharp transfer characteristics

• Since a read-failure is initiated by a 0 1 input transition for the inverter storing logic “1,” higher switching threshold with sharp transfer characteristics of the Schmitt trigger gives robust read operation

CONT………

• 1 0 input transition• Here Feedback mechanism is not present• This results in smooth transfer characteristics that are

essential for easy write operation.• Thus, input-dependent transfer characteristics of the Schmitt

trigger improves both read-stability as well as write-ability of the SRAM bitcell

ST-1 Bitcell

Cont.• The 10T bitcell uses Schmitt Trigger (ST) inverters to help

improve the read static noise margin (RSNM). • The NR2/NFR feedback transistors weaken the pull down

network when VR is high, increasing the switching threshold of the right inverter.

• This means that the VL node would have to pull up much higher during a read in order to flip the cell, resulting in higher read stability.

• This bitcell has been shown to have 1.56× higher read SNM compared to the conventional 6T bitcell.