IEEE TRANSACTIONS ON MICROWAVE THEORY AND …kentesar/Kamran_J14.pdf · The transceiver is based on a direct conversion re-ceiver architecture along with a dual-band LNA and frequency

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010 2717

A Millimeter-Wave (24/31-GHz) Dual-Band Switchable Harmonic Receiver in

0.18-�m SiGe ProcessMohamed El-Nozahi, Student Member, IEEE, Ahmed Amer, Student Member, IEEE,

Edgar Sánchez-Sinencio, Fellow, IEEE, and Kamran Entesari, Member, IEEE

Abstract—A dual-band switchable harmonic receiver fordownconverting the industrial-scientific-medical and local-mul-tipoint-distribution-service bands at 24 and 31 GHz is proposedin this paper. The front end utilizes a new technique for bandselection. Mathematical formulation, including the effect of mis-matches, for the new switchable harmonic receiver is provided inthis paper. In addition, new circuit techniques for the low-noiseamplifier and millimeter-wave mixer implementations are pre-sented. The receiver is implemented using 0.18- m BiCMOStechnology with a total power consumption of 60 mW. Measure-ments show a band rejection higher than 43 dB, gain of 21 and 18dB, NF lower than 8 and 9.5 dB, and third-order intercept pointof 18 and 17 dBm for the 24- and 31-GHz frequency bands,respectively.

Index Terms—BiCMOS, dual band, millimeter wave, receiver,switchable harmonic, wideband.

I. INTRODUCTION

T HE GROWING number of wireless applications inthe communication market is one of the main drivers

of the semiconductor industry. With the increasing demandfor high-data-rate communication, and the congestion of thelow-gigahertz frequency bands, moving to the largely unusedspectrum at millimeter-wave (mm-wave) frequencies is nec-essary. Some system applications include the IEEE 802.16wireless metropolitan-area network (WiMAN) for point-pointwireless communications at the 10–66 GHz frequency range,automotive short-range and long-range radars for collisionavoidance at 22–29 and 77 GHz, and cognitive radios. Severalcomplementary metal–oxide semiconductor (CMOS)/BiCMOSsingle-band transceivers are reported for mm-wave applications[1]–[11]. The idea of combining multiple bands is also veryappealing for mm-wave transceivers on silicon to increase theversatility and save the chip area.

Single-band receivers at mm-wave frequencies have been themain focus of a lot of literature until now. The first 24–GHz

Manuscript received February 03, 2010; accepted July 01, 2010. Date of pub-lication October 25, 2010; date of current version November 12, 2010. Thiswork was supported in part by the Semiconductor Research Corporation (SRC)and in part by the Semiconductor Industry Association (SIA).

M. El-Nozahi is with Marvell Semiconductor, Santa Clara, CA 95054 USA.A. Amer, E. Sánchez-Sinencio, and K. Entesari are with the Department of

Electrical and Computer Engineering, Texas A&M University, College Station,TX 77843 USA (e-mail: [email protected]; [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2010.2077530

CMOS front end in a 0.18- m process was reported in [1]. Areceiver front end that incorporated a folded microstrip geom-etry to create resonance at the 60-GHz band in a common-gatelow-noise amplifier (LNA) and active quadrature mixers was re-alized in 0.13- m CMOS technology [2]. Guan et al. [3] re-ported a fully integrated 8-channel phased-array heterodyne re-ceiver at the 24-GHz industrial-scientific-medical (ISM) band inBiCMOS technology. Receiver chip sets for gigabit per secondwireless communications in the 60-GHz ISM band in BiCOMSand CMOS technologies were demonstrated in [5]–[9]. A fullyintegrated phased-array receiver with integrated dipole antennasfor long-range automotive radar applications at 77 GHz was de-signed and fabricated in a 0.12- m BiCMOS process in [11]. Ascan be seen, most of the efforts have concentrated on developingthe first generation of single-band commercial silicon receiversat 24, 60, and 77 GHz.

A mm-wave dual/multiband silicon-based receiver is neces-sary to reduce the size and cost of the transceiver to avoid severalfront ends for each band. These receivers will be necessary tocover the 10–66 GHz frequency range for many applications oc-cupying different bands, such as wireless applications. A similarrequirement exists for low-gigahertz applications, such as WiFiat 2.4 GHz and 5.2 GHz.

Dual/multiband receivers’ design poses many challengingproblems at mm-wave frequencies as follows: 1) Frequencysynthesizers need to span over a very wide frequency range tocover the entire band of interest. As a result, they are powerhungry or very hard to implement due to the wide tuningrange of a voltage-controlled oscillator (VCO) and 2) front-endbuilding blocks including LNA and mm-wave mixers haveto support a very wide frequency range. Hence, receiver ar-chitectures, which rely on frequency synthesizers running atlower frequencies and new front-end topologies, which supportthe multi-gigahertz frequency range need to be developed toovercome the aforementioned challenges.

The first dual-band 22–29/77–81 GHz transceiver for auto-motive radars have been recently reported using BiCMOS tech-nology [12]. The transceiver is based on a direct conversion re-ceiver architecture along with a dual-band LNA and frequencysynthesizer. To avoid having a very wide tuning range of theVCO, this receiver architecture uses two local oscillators (LOs)for each separate band. In addition, these LOs have to run at22 and 77 GHz, which result in high power consumption. Thisreceiver shows that direct conversion receivers are not suitablefor multiband operation at mm-wave frequencies because of thelimited tuning range of the LO. To the best of our knowledge,

0018-9480/$26.00 © 2010 IEEE

2718 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 11, NOVEMBER 2010

Fig. 1. Proposed switchable harmonic receiver architecture.

there is no other reported dual/multiband silicon-based radio atmm-wave frequencies.

In this paper, a new dual-band receiver architecture isproposed to downconvert the ISM and local multipoint-dis-tribution system (LMDS) bands at 24 and 31 GHz, respec-tively. The receiver is targeted for the single carrier wirelessmetropolitan-area network standard (IEEE 802.16). The IEEE802.16-SC is specified for the 10–66 GHz applications. Thisstandard supports channel bandwidths of 20, 25, and 28 MHz,with quadrature phase-shift keying (QPSK), 16-quadrature am-plitude modulation (QAM) and 64-QAM modulation schemesfor bit rates up to 134 Mb/s [13]. In the proposed architecture,each of the 24- and 31-GHz bands has a bandwidth of 250MHz, including 9 channels with 25-MHz bandwidth and QPSKmodulation. The receiver relies on a switchable harmonic mixerfor band selection. The switchable harmonic mixer allows theLO to run at a lower frequency, hence eliminating the needfor a wideband VCO (challenge 1). In addition, new circuittechniques for a wideband LNA and wideband mm-wave mixerare employed to cover the frequency band of interest andto further reduce the power consumption (challenge 2). Thereceiver is implemented using 0.18- m SiGe BiCMOS tech-nology 70/170 GHz/GHz). The paperis organized as follows: In Section II, the proposed switchableharmonic receiver architecture is presented. Different buildingblocks of the receiver, including the wideband LNA, the wide-band mm-wave mixer, and the switchable harmonic mixer,and their implementation are discussed in Section III. Themeasurement results are then shown in Section IV. Finally, theconclusion is presented in Section V.

II. PROPOSED RECEIVER ARCHITECTURE

A. Basic Idea

The proposed receiver architecture and its frequency plan-ning are demonstrated in Figs. 1 and 2, respectively. Similarto the heterodyne receiver, the desired band is downconvertedto baseband through an intermediate frequency . The two

Fig. 2. Frequency planning of the proposed switchable harmonic receiver(Channel bandwidth � 25 MHz, total RF band –Bandwidth � 250 MHz).

frequency bands, at 24 and 31 GHz, are initially amplified usinga two-stage wideband LNA. Then, a wideband mm-wave mixerand a LO (LO1) running at 10.25 GHz (effective mixingfrequency is 20.5 GHz) is used to downconvert the 24- and31-GHz bands to intermediate frequencies of 3.5 and 10.5 GHz,respectively. The second mixing stage is a switchable harmonicmixer (SWHM) for band selection and final downconversion ofsignals to baseband. The second LO (LO2) operates at a fre-quency of 3.5 GHz and the band selection is achievedby either mixing the input signal with the fundamental or third-order harmonic component of LO2. The IF amplifier is used tofilter out higher unwanted frequency components, drive the highinput capacitance of the switchable harmonic mixer, and providehigher gain at the upper band to compensate the 9-dB system-atic gain difference between the lower and upper bands due toSWHM as discussed later in this section.

The basic idea of the band selection is to adjust the harmonicsof the second mixing stage. If the 24-GHz band is desired, thesecond mixing stage mixes the input signal with the 3.5-GHzfundamental component, and the third-order harmonic compo-nent at 10.5 GHz is suppressed. On the other hand, if the 31-GHz

EL-NOZAHI et al.: MM-WAVE (24/31-GHZ) DUAL-BAND SWITCHABLE HARMONIC RECEIVER 2719

band is desired, the fundamental component of the second os-cillator is suppressed and the third harmonic component, at 10.5GHz, is amplified. Since the architecture is based on a het-erodyne scheme, the LNA should provide image rejection toachieve a high signal-to-noise ratio (SNR) from the receiveddata. If the image rejection provided by the LNA is not sufficientfor the necessary rejection, an external bandpass filter (such asa switchable RF microelectromechanical-system (MEMS) filterat 24–31 GHz similar to the one reported in [15]) can be addedin front of the receiver to remove unwanted image signals thatare placed at 17 and 10 GHz for the 24- and 31-GHz frequencybands, respectively.

To demonstrate the advantage of the proposed receiver archi-tecture, it is compared to one of the existing Weaver-based dual-band receivers [14]. The Weaver-based architecture requires aLO running at 27.5 GHz compared to one running at 20.5 GHzin the proposed architecture. Having a lower oscillating fre-quency reduces the power consumption while achieving betterphase noise. For the second mixing stage, both architectures areusing the same LO frequency. Another advantage is that theWeaver architecture requires two mixers operating at 27 GHzcompared to a single mixer operating at 20.5 GHz, thus reducingthe power consumption as well as the complexity in the layoutdue to the coupling among various components. It is importantto mention that both architectures require a tuning scheme, suchas least mean square (LMS), to efficiently reject one of the bandsand receive the desired one [14]. In this implementation, twocontrol lines are used for external tuning (Fig. 1). The first oneadjusts the phase error, while the other one adjusts the gain error.

B. Switchable Harmonic Mixer Mathematical Analysis

The switchable mixer mixes the input signal at 3.5 or 10.5GHz with either or , respectively. Fig. 3 demon-strates the basic idea of the switchable mixer, where a single LOsource with three different phases is required to mix the inputsignal with the fundamental or the third-order harmonic, andsuppress unwanted components. The three waveforms are con-sidered square waves because this is the effective signal seenby any Gilbert-cell-based mixer. The fundamental or third har-monic components cancellation is achieved by summing thethree LO signals , with proper phase and amplitudescaling. Using Fourier series analysis, the three waveforms arewritten in terms of their first five harmonics as follows:

(1)

Fig. 3. Basic idea of the switchable harmonic mixer.

where , , and are the amplitudes of the three differentwaveforms, and and are phase shifts. In these equations,

is selected as the reference signal and, therefore, 0. Theeffective mixing signal is generated by summing the threewaveforms as follows:

(2)

With assumptions of and , the effectivemixing signal can be written as follows:

(3)

The fundamental or the third harmonic component in (3) areeliminated by adjusting the values of amplitudes and phases ofthree waveforms – . Several amplitudes and phases can per-form this functionality. Fig. 4 shows the required amplitude ratio

for each value of to cancel either the fundamentalor the third harmonic component. Among these solutions, threepractical sets are selected. Table I summarizes coefficients andcomponent values for these sets. For the proposed receiver, thefirst set is selected because it reduces thehardware complexity. For this set, only the phase of controlsthe band selection by changing its polarity. The lower frequencyband is selected by tuning the switchable harmonic mixer for

, and the upper frequency band is selectedby adjusting the mixer to . On the otherhand, Sets 2 and 3 require a polarity and amplitude change of

to perform the band selection, and add to the complexityof the receiver implementation. Another advantage of selectingthe 45 phase shift is in the Q-mixer implementation shown inFig. 1. Only an additional 90 phase shift is required for the

signal. The 90 is inherently generated for the and sig-nals. This is because shifting by 90 provides the invertedsignal of , which is already used to drive the I-mixer. This


TABLE ICOEFFICIENTS VALUES OF THE SWITCHABLE HARMONIC MIXER FOR TWO POSSIBLE COMBINATIONS ��

Fig. 4. Phase and amplitude conditions for the fundamental or third harmoniccomponent cancellation.

Fig. 5. Simulated spectrum of � using Simulink when the third harmoniccomponent (top) or fundamental component (bottom) is cancelled using the in-formation of Set 1 in Table I.

is not the case for Sets 2 and 3 and, therefore, the 45 phase shiftrelaxes the receiver complexity.

Table I also shows the conversion gain of the mixer foreach frequency component. For Set 1, there is a systematic

gain difference of 9 dB between the fundamental and thethird harmonic component. This systematic gain difference isadjusted by using the IF amplifier, to provide a flat gain forboth frequency bands. Having an almost constant gain for bothbands reduces the overall power consumption by relaxing thenoise figure and IIP3 requirements of the following blocks[16]. The idea of harmonic rejection/selection is verified usingSIMULINK1 simulations and results are shown in Fig. 5. Asdepicted, the third and fundamental components are suppressedby adjusting the proper values of coefficients. Higher orderharmonics are easily filtered out by using a low-pass filter in thebaseband section. The proposed switchable harmonic receiveris not limited to the fundamental or the third-order harmoniccomponents, and can be applied to higher order harmonics.

C. Frequency Planning

The proposed dual-band switchable harmonic receiver archi-tecture can be employed to downconvert any arbitrary pair offrequency bands by properly selecting the frequencies of theLOs. A general approach to determine the operating frequen-cies of the two LOs is derived, and the resulting equations areas follows:

(4)

where and are frequencies of the LO shown in Fig. 1,and and are the lower and upper frequencies ofthe two desired bands. For the 24- and 31-GHz bands, and

are 20.5 and 3.5 GHz, respectively. In this architecture,is further reduced to 10.25 GHz by using a frequency dou-

bler to reduce the power consumption of the LO generation cir-cuitry. In this receiver, the total RF band bandwidth is less than250 MHz and, therefore, the third harmonic of LO1 at 30.75GHz is not important. However, if the targeted application band-width is higher than 250 MHz, then the frequency doubler maynot be used and, hence, has to be 20.5 GHz.

Another example for the frequency planning is the WiFi stan-dards at 2.4 and 5.2 GHz. In this case, and have tobe 1 and 1.4 GHz, respectively.

D. Sensitivity to Parameter Mismatch

The amount of the undesired harmonic rejection depends onthe matching between various parameters in Table I. A mis-match analysis is performed to investigate the effect of process

1SIMULINK: www.mathworks.com


variations on the amount of rejection, and shows the importanceof having an automatic tuning scheme for this architecture. Bothamplitude and phase mismatches are considered. The amount ofrejection is defined as the ratio of the unwanted harmonic of

to the desired one. Assuming that the third harmonic com-ponent is rejected, the unwanted component is given by

(5)

where and are amplitude mismatches, and andare phase mismatches of and . In (5), the component

of is selected as the reference, and mismatch variations areassumed to happen to the components of and . In theideal case of infinite rejection, should be zero, and thisis achieved if , , , and

. By applying the condition of ideal rejectionto (5) and after some mathematical simplifications, isapproximated as follows:

(6)

The total power of is obtained by summing the squarevalue of coefficients of sine and cosine functions in (6) as fol-lows:

(7)

Finally, the rejection ratio of the unwanted third har-monic component to the fundamental one is given by

(8)

where is the amplitude of the fundamental component.A similar analysis can be performed for the case of the funda-mental component cancellation to find . Equations (6)–(8)indicate that the amount of the rejection is a function of ampli-tudes and phases of the original waveform. In addition, thesemismatches can add together to worsen the amount of rejection.Fig. 6 shows the worst-case rejection versus the value of for

and using system-level simulations. The worst-caserejection is when all mismatches are added coherently. In thissimulation, an amplitude mismatch of 2% for and ,and a phase mismatch of 2 for and are considered.The simulations in Fig. 6 indicate that the worst-case rejectiondepends on the selected value of amplitudes and phases, whichare determined from Fig. 4. The lowest value of is for

, while the lowest value of is for . In thisimplementation, is selected to be 45 because it reduces thereceiver complexity as mentioned earlier in Section II-C. The

Fig. 6. Worst-case rejection for amplitude and phase mismatches of 2% and2 , respectively.

worst-case rejection in this case is higher than 28 dB. Phase andamplitude tuning schemes can increase the amount of rejectionto values higher than 55 dB, similar to the tuning scheme usedin the Weaver architecture [14]. In addition, the external 24–31GHz RF MEMS-switchable bandpass filter provides part of therejection. Combining both rejection values results in high rejec-tion that is sufficient to obtain the required high signal-to-noiseratio (SNR).

III. CIRCUIT IMPLEMENTATION

A. Wideband LNA

A two-stage wideband low-noise amplifier (LNA) is used toamplify both bands at 24 and 31 GHz. The wideband LNA ar-chitecture is shown in Fig. 7 and the circuit element values aresummarized in Table II [17]. In this architecture, a widebandinput-matching network is designed using inductors and .The input-matching network is similar to the narrowband ap-proach at the low-gigahertz range [18]; however, the same com-ponents can be used for wideband matching at mm-wave fre-quencies using BiCMOS technology. This is because the qualityfactor of the input-matching network decreases at higher fre-quencies, hence allowing for wider matching at the input. Thewideband gain is obtained by using a coupled resonator as theload of each amplifier stage. Coupled resonators can result intwo peaks depending on their coupling coefficient. Cascadingtwo of these coupled resonators ( , , , and , ,and ) with unequal peaking frequencies, results in a wide-band response [17].

Two gain stages with two different coupled-resonator loadsare implemented to provide the wideband response for the pro-posed LNA. In addition, these two stages increase the voltagegain across the desired wideband frequency range. The loadingeffect of the second stage and the routing parasitics, includingcapacitance and inductance, are considered during the design ofthe first stage. This concept is verified using postlayout simu-lations and the results are shown in Fig. 8 for the voltage gainand reflection coefficient. The LNA has a voltage gain of 12 and11 dB for 24- and 31-GHz frequency bands, respectively. Also,simulations show a reflection coefficient better than 12 dB forboth frequency bands. The LNA provides an image rejection of


Fig. 7. Schematic of the wideband mm-wave LNA.

TABLE IICIRCUIT ELEMENT VALUES FOR THE IMPLEMENTED LNA

Fig. 8. Postlayout simulated gain and an input reflection coefficient of a wide-band LNA.

22 and 47 dB for the image frequencies at 10 and 17 GHz, re-spectively. The noise due to the cascode transistor is reducedby adding the inductor to resonate with the parasitic capaci-tance at the emitter of [6], [8], [19]. Hence, the emitter ofis degenerated with high impedance, and the noise current ofis not injected to the output of the first stage. Instead, the noisecurrent will circulate within . is added to decrease the dccurrent through ; hence reducing its size and associated para-sitics. This technique results in a worst-case noise figure of 6 dBat the 31-GHz frequency band. The IIP3 of this architecture isbetter than 6 dBm. All of the aforementioned techniques en-able the design of an LNA with a large and high gain, lowwideband input-referred noise, and low power consumption of15 mW from a 1.8-V supply.

Fig. 9. Schematic of the wideband mm-wave mixer.

B. Wideband MM-Wave Mixer

The mm-wave mixer downconverts the 24- and 31-GHzbands to 3.5 and 10.5 GHz intermediate-frequency (IF) fre-quency, respectively. This mixer should provide a constant gainfor the two bands to relax the noise figure and IIP3 requirementsof the following blocks [16]. As a result, the mixer should haveat least 7 GHz of 3-dB IF-bandwidth. All of the reported mixersin the literature have an IF bandwidth not more than 3.5 GHzwithin the -band [21]–[26]. Implementing the mm-wavemixer using a conventional mixer is not possible because of theinternal parasitics that limit the IF-bandwidth to few gigahertz.To increase the IF-bandwidth of the conventional mixer, thesize of LO switches and the value of load resistance have to bereduced to push the parasitic poles to higher frequencies. Thiscomes at the cost of reducing the conversion gain and increasingthe noise figure. In addition, the conventional mixer requiresan LO running at 20.5 GHz, which means increasing the powerconsumption of the LO and degrading its phase noise.

In this receiver, the frequency doublers are used to reduce theoperating frequency of LO to 10.25 GHz. This approach reducesthe power consumption of the LO, and provides better isolationin addition to reducing the LO self-mixing problem [20]. Fig. 9shows the proposed wideband mm-wave mixer and the circuitelement values are summarized in Table III. The mixer consistsof two frequency doublers and a mixing stage ( and ).The LO signal, running at 10.25 GHz, with four phases (0 , 90 ,180 , and 270 ) is injected into the gate of frequency doublers.The required four phases are generated from an external differ-ential LO signal using an on-chip LC phase shifter. Twice theLO frequency (20.5 GHz) appears at the source of (and ). Both signals at and are out of phase. The in-ductor is added to resonate with the parasitic capacitance forincreasing the swing at and . As a result, increases theconversion gain and lowers the noise figure of the mixer. Fig. 10shows and of the doubler versus the injected . To fullyswitch the BJT transistors, and have to be around 100 mV,which is adjusted by applying a 300-mV LO signal at the dou-bler input according to Fig. 10.

To extend the IF bandwidth, the pi-network consisting of ( ,, and ) is introduced. Without the pi-network, the mixing

stage is similar to the conventional active mixer. For the conven-tional mixer, the gain drops by 40 dB/dec for high IF frequenciesbecause of internal parasitic capacitance. These parasitic capac-itances result in two real poles—one at the emitter of and


Fig. 10. Simulated output swing versus the input voltage amplitude of the dou-bler �� 1 mA).

TABLE IIICIRCUIT-ELEMENT VALUES FOR THE IMPLEMENTED

WIDEBAND mm-WAVE MIXER

the other at the output node; hence, the IF bandwidth is limited.The pi-network results in two complex poles that are adjusted toproduce peaking. This peaking is aligned with the output pole

to extend the operating bandwidth. Extending thebandwidth using this approach introduces inband ripples, whichare adjusted using the quality factor of the complex pole. Thequality factor and the location of the two poles are specifiedby the component values of the pi-network ( , , and ).Reducing , , or increases the bandwidth and inbandripples and lowers the conversion gain. In this design, inbandripples of 0.3 dB are considered and the IF bandwidth is ad-justed to 13 GHz through . The IF bandwidth is limited to13 GHz to avoid downconverting the noise at higher frequenciesin the second mixing stage. Table III summarizes the componentvalues for the mixer including the pi-network. Depending on theparasitic of and in Fig. 9 is not enough to implementthe required quality factor of the complex poles and, therefore,

and are implemented using MOM capacitors.This idea of extending the bandwidth is demonstrated through

postlayout simulations, and Fig. 11 shows the overall conver-sion gain and gains of the RF and IF sections in the mixer. Asdepicted, input signals above the mixing frequency (20.5 GHz)exhibit a peaking of 10 dB at 31 GHz. After the mixing opera-tion, this peaking appears at an IF frequency of 10.5 GHz, andit cancels the degradation in conversion gain due to the outputpole. In this design, the output pole appears at 5 GHz. This ap-proach shows a simulated 3-dB IF bandwidth of 13 GHz with aconversion gain of 4 dB, which is difficult to achieve without thepi-network. Another important feature of the pi-network is thatit does not amplify the image frequencies at 17 and 10 GHz bythe same amount as the required bands at 24 and 31 GHz. This

Fig. 11. Postlayout simulations of the conversion gain and gains of RF and IFsections in the wideband mm-wave mixer.

Fig. 12. Postlayout simulations of noise figure versus the output IF frequencyof the wideband mm-wave mixer.

is because the peaking occurs mainly in the upper side of the LOfrequency. The image signals at 17 and 10 GHz are downcon-verted with a conversion gain of 1 and 6 dB, respectively.Combined with the image rejection (IR) provided by the LNA,the total IR is 27 dB and 57 dB for 17 and 10-GHz image fre-quencies without the effect of the external mm-wave filter. Fi-nally, the size of main transistor is maximized based onthe maximum capacitance that can be loaded by the LNA. BJTswitches are used because they require an LO with lower voltageswing. The mixer shows a simulated noise figure of 12.7 dB and10.4 dB for the 24-GHz and 31-GHz bands as shown in Fig. 12.Simulated LO-to-RF (20.5 GHz to RF) isolation is higher than45 dB. The mixer and the frequency doublers consume 10 mAfrom a 1.8-V supply.

C. Switchable Harmonic Mixer and IF Amplifier

This section discusses the implementation of the switchableharmonic mixer and its supporting circuits, including the IF am-plifier and polyphase generation circuitry.

1) Switchable Harmonic Mixer: Fig. 13 shows the imple-mentation of the switchable harmonic mixer, which is similar tothe implementation in [27] used in a highly linear transmitter.The mixer in Fig. 13 consists of three Gilbert-cell mixers eachdriven with an LO signal having a different phase. According toTable I, the middle mixer provides a conversion gain timeshigher than the other two mixers. This is achieved by scaling the


Fig. 13. Architecture of the switchable harmonic mixer. The selection of either the fundamental or the third-order harmonic component is achieved by changingthe phase of the middle mixing stage.

transconductance value of to a value of times higher thanthe transconductance value of and . This is achieved byincreasing the biasing current through the transistor andits size. Only increasing the size of increases the parasiticcapacitance at its drain and, hence, attenuates the signal closeto 10.5 GHz. The current of the middle mixing stage can be ad-justed in an automatic tuning scheme, which is not implementedin this receiver, to overcome the finite amount of rejection ofthe unwanted band due to process mismatches and variations.NMOS RF transistors are chosen for the RF input stage to min-imize the loading on the preceding stage in the receiver. Also,they have the advantage of better linearity compared to bipolarjunction transistors (BJTs), which need some linearization tech-nique and make the matching between the three mixing cells aharder design problem. The biasing transistors , , and

are designed to be large enough to reduce the overdrivevoltage for higher voltage headroom, and to help increase thematching between the devices. BJTs are used for the LO inputstage to minimize the flicker noise of the switches. In addition,bipolar transistors require a small LO signal amplitude 100mV) for switching. The number of base fingers of each bipolartransistor is increased to reduce its generated output noise.

The PMOS current steering technique is used to increase theconversion gain and available headroom as shown in Fig. 13.Current steering is implemented through the transistor andresistor . This is because the output dc voltage is determinedby the gate overdrive voltage of PMOS devices. During ac op-eration, the passive resistor appears and controls the con-version gain. This technique does not require a common-modefeedback circuit since provides a local feedback to stabilizethe output dc voltage. The area of PMOS transistors is increasedto minimize their flicker noise contribution at the output. Theflicker noise of , , and will be upconverted to[28]. Slight degradation in the linearity is observed due to thenonlinear output resistance of PMOS transistors.

The LO signals are driven from the same source, and theyhave the same frequency of 3.5 GHz but are different in phase,according to Table I. This mixer provides downconversion ofthe signals at 3.5 and 10.5 GHz, which are the IF frequencies of24- and 31-GHz frequency bands. The fundamental (3.5 GHz)/

third-order harmonic (10.5 GHz) selection is achieved by con-trolling the phase of the input LO signal of the middle mixer inFig. 13. If the phase of LO signal is 0 , then the fundamentalcomponent is selected while the third harmonic component isrejected. On the other hand, if the phase is 180 , then the thirdharmonic component is selected and the fundamental one is re-jected. This approach enables the use of a single switch to con-trol the required band selection.

2) IF Amplifier: The proposed switchable harmonic mixerhas a high input capacitance due to employing three mixingstages. This input capacitance can limit the performance of theprevious stage (mm-wave mixer) at higher frequencies. Re-ducing the input capacitance comes at the cost of reducing theconversion gain and increasing the noise figure. To overcomethis problem, an IF amplifier is located between the mm-waveand switchable harmonic mixers as a buffer. This amplifier,shown in Fig. 14, employs shunt peaking to provide higher gainat the 10.5-GHz band. Fig. 15 shows the simulated gain andnoise figure of the IF amplifier. The IF amplifier provides gainof 6 dB and 7.7 dB, and a noise figure of 12.3 dB and 10.5 dBfor 3.5 GHz and 10.5 GHz, respectively. The higher gain at the10.5-GHz band is necessary to compensate for the systematicgain difference of 9 dB between the two bands as pointed out inTable I and the gain reduction due to the parasitic capacitances.The 6-dB loss at 3.5 GHz is not problematic because the mixerhas higher gain at this band. Increasing the size of the inputtransistor in Fig. 14 to avoid the 6-dB loss is not possiblebecause it would lower the gain of the previous stage. Thecascode architecture is used to ensure stability of the amplifier.

3) Polyphase Shifter: A two-stage polyphase shifter, shownin Fig. 16, is used to generate the required phase shifts pre-cisely with the drawback of 3-dB loss [29]. Simulations acrossthe process corners show a precise phase shift of 90 betweennodes and in Fig. 16 as long as nodes 1 and 2are not loaded. The 0 /180 phase shifts are taken from the mainLO input signal ( , ) to reduce the loading onnodes 1 and 2, and they are injected to a multiplexer. The con-trol line of this multiplexer determines the desired band. Due tothe additional multiplexer, the phase shift is not 0 /180 , and anadditional RC phase shifter, shown in Fig. 17, is added to reduce


Fig. 14. IF amplifier with shunt peaking (�� 27/0.18, ��

19/0.18, � � �� , � � 1.1 nH}).

Fig. 15. Post-layout simulations of the conversion gain and noise figure of IFamplifier.

the amount of phase mismatch. The resistance is externallycontrolled through the transistor to account for the phasemismatch between and that are gener-ated due to process variations. In addition, this phase shifter re-duces the amplitude of , so that the driving amplitude ofthe switches is the same for the three mixers for better matching.The capacitor is chosen to double the value of the capacitor

of the polyphase filter to almost have the same amplitudefor all LO output signals. The phase control voltagein Fig. 17 can be used in an automatic tuning scheme to providethe necessary phase correction and, hence, increase the amountof rejection of the unwanted band. Fig. 18 shows the variationof the output phase of versus .

4) Possible Automatic Tuning Implementations: Manualtuning is used for the implemented-switchable harmonic mixer.However, possible implementations of the phase and amplitudeautomatic tuning circuits are demonstrated. An implementationfor automatic phase tuning is shown in Fig. 19. In this scheme,

and are sensed and multiplied separately with, yielding a dc component proportional to the phase

shift. The difference between the two multiplication operationsis then integrated and the output of the amplifier holds thevoltage required for . At steady-state condition, bothmultiplications lead to the same output and, therefore, theintegrator holds the required voltage for tuning. This schemeadjusts exactly in between and . The 90

Fig. 16. Two-stage polyphase shifter (� � �� , � � 230 fF).

Fig. 17. RC phase shifter with electronic tuning (� � �� , � � 260 fF,including loading parasitics).

Fig. 18. Output phase variation of �� versus � of the circuit inFig. 17.

phase shift between and is guaranteed by thepolyphase shifter.

For amplitude tuning, the calibration loop in Fig. 20 could beused. Considering the rejection of the 3.5-GHz band, a low-fre-quency test tone , less than 10 MHz, is upconverted usingthe 3.5-GHz LO2 signal, yielding a tone at 3.5 GHz . Thissignal is injected to the SWHM which downconverts it backto baseband. In this case, the SWHM is tuned to downconvertthe 10.5-GHz band, and ideally, no signal should appear at theoutput. A bandpass filter tuned at filters out the downcon-verted signal, which is mixed with the original tone, re-sulting in a dc level proportional to the finite rejection. The dclevel is compared to zero, which is the level corresponding to


Fig. 19. Possible implementation of the automatic phase-tuning control cir-cuitry.

Fig. 20. Possible implementation of an automatic calibration loop for ampli-tude tuning.

Fig. 21. Postlayout simulations of the switchable harmonic mixer and IF am-plifier conversion gain for the 3.5- and 10.5-GHz frequency bands versus the�� voltage amplitude.

infinite rejection. Finally, a successive approximation algorithmadjusts the amplitude control signal to the required level.

In the case of the 10.5-GHz signal, a frequency tripler is usedto generate a 10.5 GHz tone. The SWHM is adjustedfor the 3.5-GHz band, and the bandpass filter is tuned at .Mixing the downconverted tone with the originaltone also produces a dc level that is proportional to the finiterejection, which is used by the successive approximation algo-rithm to adjust the amplitude control signal.

5) IF Amplifier and Switchable Harmonic Mixer SimulationResults: The postlayout simulation results for the conversiongain, noise figure, and IIP3 of the combined switchable har-monic mixer and IF amplifier versus the amplitude of LO2 areshown in Figs. 21–23, respectively. In this design, the voltageof is adjusted to 100 mV to provide sufficient gain andreduce the noise figure of the 10.5-GHz band. At this am-plitude, there is degradation of IIP3 at the 3.5-GHz band; how-ever, it is higher than the one at 10.5 GHz. Also, simulations

Fig. 22. Postlayout simulations of the switchable harmonic mixer and IF am-plifier noise figure for the 3.5- and 10.5-GHz frequency bands versus the ��voltage amplitude.

Fig. 23. Postlayout simulations of the switchable harmonic mixer and IF am-plifier IIP3 for the 3.5- and 10.5-GHz frequency bands versus the �� voltageamplitude.

show LO-to-RF and 3LO-to-RF isolations of SWHM higherthan 100 dB, which is expected due to the differential natureof the SWHM mixer.

The conversion gain versus the baseband frequency for the3.5- and 10.5-GHz frequency bands is shown in Fig. 24. Themixer has a conversion gain of 6.7 and 5.2 dB for the 3.5- and10.5-GHz bands, respectively. Only 1.5-dB difference in gainis achieved due to the effect of the gain peaking introduced bythe IF amplifier. The conversion gain varies by 1 dB acrossthe amplitude tuning range. Simulations also showed a rejectionhigher than 60 dB. This value is hard to achieve without a tuningscheme in the measurement as mentioned in Section II-D andwill be shown in Section IV.

A simulated noise figure of 17.1 and 18 dB at baseband areobtained for the 3.5- and 10.5-GHz frequency bands, respec-tively. The 10.5-GHz band has slightly higher noise figure dueto the additional losses. The IIP3 of the mixer and IF ampli-fier is 7 and 1 dBm for the 3.5- and 10.5-GHz band, respec-tively. Simulations are performed with a two-tone separation of10 MHz. The IIP3 at 10.5 GHz is lower due to the effect of thehigher gain introduced by the shunt peaking IF amplifier. How-ever, the 1 dBm IIP3 is still within the required specification.


Fig. 24. Post-layout simulations of switchable harmonic mixer and IF amplifierconversion gain for the 3.5- and 10.5-GHz frequency bands versus the basebandfrequency.

Fig. 25. Die photo of the switchable harmonic receiver.

Fig. 26. PCB for the switchable harmonic receiver.

The total current consumptions of the SWHM and IF amplifierare 8 mA and 7 mA from a 1.8-V supply, respectively.

IV. EXPERIMENTAL RESULTS

The switchable harmonic receiver is fabricated using 0.18m BiCMOS technology provided by Jazz Semiconductor. The

cutoff frequency of this technology is 70 and 50 GHz for theBJT and MOS transistors, respectively. The die micrograph is

Fig. 27. Measured and simulated � for the dual-band receiver.

Fig. 28. Measured conversion gain and rejection of the proposed switchableharmonic receiver �� 0.25 V).

shown in Fig. 25, where the total area is 0.7 mm , excludingpads. An FR-4 printed-circuit board (PCB), shown in Fig. 26, isdesigned to test the dual-band receiver. The PCB is used to applythe dc signals, monitor the low-frequency output, and apply theLO signals. The chip is packaged in a quad flat-no-lead (QFN)package. The input signal is injected using a GSG RF probeto avoid degrading the performance of the receiver. The outputof the receiver is applied to an off-chip instrumentation ampli-fier for the differential-to-single-ended conversion necessary forthe measurements. The 3.5- and 10.25-GHz LO signals are ap-plied externally and injected to the chip through SMA connec-tors. An Agilent N5230A network analyzer is used to inject themm-wave signal and to measure the reflection coefficient of theLNA. LO signals are applied using the HP-8673C signal gener-ator and HP 8719ES network analyzer.


Fig. 29. Measured rejection in the baseband when (a) the 24-GHz band or (b)the 31-GHz band is selected.

The measured reflection coefficient of the receiver is shownin Fig. 27. A reflection coefficient of better than 12 dB is ob-tained for the two frequency bands. The overall measured con-version gain versus the baseband frequency (dc-15 MHz) for 24-and 31-GHz frequency bands is shown in Fig. 28. These plotsare obtained by measuring the output signal using the HP 3588Aspectrum analyzer and substracting the gain of the instrumenta-tion amplifier. An overall conversion gain of 21 and 18 dB is mea-sured for the 24- and 31-GHz frequency bands, respectively.

Fig. 29 shows the spectrum of the output signal for variousconditions. Fig. 29(a) demonstrates the case where the 24-GHzband is selected and the 31-GHz band is rejected, while Fig.29(b) presents the opposite scenario. In this measurement, the24- and 31-GHz input signals are adjusted to have the same am-plitude. Measurements show a rejection of the unwanted signalbetter than 43 dB for two different cases after manual tuning ofthe phase and amplitude mismatches 1.26 V). Thewidening in the downconverted 31 GHz is due to the AgilentN5230A network analyzer that is used to generate the 31-GHzinput signal. This network analyzer generates the widened spec-trum shown in Fig. 29(b) at the input of the receiver and, there-fore, the same shape appears at the output. The simulation re-sults show a rejection of better than 60 dB. The discrepancy

Fig. 30. Measured rejection versus phase control voltage � when the31- or 24-GHz band is rejected.

TABLE IVCIRCUIT ELEMENT VALUES FOR THE IMPLEMENTED-SWITCHABLE

HARMONIC MIXER

is mainly due to mismatches, inaccurate models, and substratecoupling. Automatic tuning schemes can be applied later for thisdual-band receiver to increase the amount of rejection. Fig. 30shows the measured rejection versus the phase control voltage

when the amplitude control (Fig. 13) is kept at itsdefault value. As depicted, optimum values of phase controlvoltage for maximum rejection of 24- and 31-GHz bands are1.3 and 1.24 V, respectively. Optimum values are different forthe two bands because the mismatches and process variationshave a different impact on the rejection for the fundamental andthird-order harmonic components. This optimum value can beobtained by using an automatic tuning scheme.

Nonlinearity measurements are performed for the 24- and31-GHz frequency bands. The dc-40 GHz Agilent N5230A net-work analyzer and 60-GHz Anritsu MG3696 signal generatorare used as the input sources. The two input signal tones areapplied with a separation of 1.2 MHz. The main output sig-nals tones are at 7 and 8.2 MHz and the third-order interme-diation signal appears at 5.8 and 9.4 MHz. For the input signalat 24 GHz, the measured output spectrum shows a differencebetween the main tones ( 19-dBm output) and the third-orderintermodulation tone of 44 dB. This results in an output-referredthird-order intercept point (OIP3) of 3 dBm equivalent to aninput-referred IIP3 of 18 dBm. Similar steps are performedfor the 31-GHz input signal, and an IIP3 of 17 dBm is ob-tained. The noise figure of the implemented receiver front endis obtained by measuring the output noise level using a spec-trum analyzer and, hence, estimating the input-referred noise.A measured noise figure of 8 and 9.5 dB is obtained for the24- and 31-GHz band, respectively. The complete dual-band re-ceiver consumes 60 mW from a 1.8 V. Finally, the measuredperformance summary of the switchable harmonic receiver andits building blocks is shown in Table V.


TABLE VDUAL-BAND-SWITCHABLE HARMONIC RECEIVER MEASURED PERFORMANCE SUMMARY

V. CONCLUSION

A dual-band-switchable harmonic receiver architecture is in-troduced in this paper. Mathematical formulation and frequencyplanning of the receiver are provided. Mismatch analysis showsthat a 2% variation in the amplitude and a phase shift of 2reduces the amount of rejection of the unwanted band to 28 dB.However, automatic tuning can increase the amount of rejection.A prototype is fabricated using 0.18- m BiCMOS technologywith 0.7 mm of chip area. The receiver is implemented for theISM and LMDS bands at 24 and 31 GHz, targeting the IEEE802.16 standard. Measurements show a band rejection higherthan 43 dB, gain higher than 18 dB, NF lower than 9.5 dB, andan IIP3 higher than 19 dBm. The receiver consumed 60 mWfrom a 1.8-V supply.

ACKNOWLEDGMENT

The authors would like to thank Jazz Semicondutor for chipfabrication.

REFERENCES

[1] X. Guan and A. Hajimiri, “A 24-GHz CMOS front-end,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 368–373, Feb. 2004.

[2] B. Razavi, “A 60 GHz CMOS receiver front-end,” IEEE J. Solid-StateCircuits, vol. 41, no. 1, pp. 17–22, Jan. 2006.

[3] X. Guan, H. Hashemi, and A. Hajimiri, “A fully integrated 24-GHzeight-element phased array receiver in silicon,” IEEE J. Solid-State Cir-cuits, vol. 39, no. 12, pp. 2311–2320, Dec. 2004.

[4] E. Ragonese, A. Scuderi, V. Giammello, E. Messina, and G. Palmisano,“A fully integrated 24 GHz UWB radar sensor for automotive applica-tions,” in Proc. IEEE Intl. Solid-State Circuits Conf. Dig., Feb. 2009,pp. 306–307.

[5] B. Floyd, S. Reynolds, U. Pfifer, T. Beukema, J. Gryzb, and C. Haymes,“A silicon 60 GHz receiver and transmitter chipset for broadband com-munications,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig., Feb.2006, pp. 184–185.

[6] B. Razavi, “A millimeter-wave CMOS heterodyne receiver withon-chip LO and divider,” IEEE J. Solid-State Circuits, vol. 43, no. 2,pp. 477–485, Feb. 2008.

[7] C. Marcus et al., “A 90 nm low-power 60 GHz transceiver with inte-grated baseband circuitry,” in Proc. IEEE Int. Solid-State Circuits Conf.Dig., Feb. 2009, pp. 314–315.

[8] B. Afshar, Y. Wang, and A. Niknejad, “A robust 24 mW 60 GHz re-ceiver in 90 nm standard CMOS,” in Proc. IEEE Int. Solid-State Cir-cuits Conf. Dig., Feb. 2008, pp. 182–183.

[9] A. Parsa and B. Razavi, “A 60 GHz receiver using 30 GHz LO,” in Proc.IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2008, pp. 190–191.

[10] Y. Kawano, T. Suzuki, M. Sato, T. Hirose, and K. Joshin, “A 77 GHztransceiver in 90 nm CMOS,” in Proc. IEEE Int. Solid-State CircuitsConf. Dig., Feb. 2009, pp. 310–311.

[11] A. Babakkhani, X. Guan, A. Komijani, A. Natarajan, and A. Hajimiri,“A 77 GHz 4-Element phased array receiver with on-chip dipole an-tenna in silicon,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig.,Dec. 2006, pp. 180–181.

[12] V. Jain, F. Taeng, and P. Heydari, “A single-chip dual-band 22–29GHz/77–81 GHz BiCMOS transceiver for automotive radars,” in Proc.IEEE Intl. Solid-State Circuits Conf. Dig., Feb. 2009, pp. 308–309.

[13] IEEE Standard for Local and Metropolitan Area Networks, Part 16: AirInterface for Fixed Broadband Wireless Access Systems, IEEE Stan-dard 802.16, 2004.

[14] L. Der and B. Razavi, “A 2-GHz CMOS image-reject receiver withLMS calibration,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp.167–175, Feb. 2003.

[15] K. Entesari and G. M. Rebeiz, “A 12–18 GHz 3-Pole RF MEMStunable filter,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 8, pp.2566–2571, Aug. 2005.

[16] M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, “Power awaremulti-band/multi-standard CMOS receiver system-level budgeting,”IEEE Trans. Circuits Syst.. II, Exp. Briefs, vol. 56, no. 7, pp. 570–574,Jul. 2007.

[17] M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, “A millimeter-wave (23–32 GHz) wideband BiCMOS low noise amplifier,” IEEE J.Solid-State Circuits, vol. 45, no. 2, pp. 289–299, Feb. 2010.

[18] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noiseamplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759,May 1997.

[19] M. Zargari, S. Jen, B. Kaczynski, M. Lee, M. Mack, S. Mehta, S.Mendis, K. Onodera, H. Samavati, W. Si, K. Singh, A. Tabatabaei, M.Terrovitis, D. Weber, D. Su, and B. Wooley, “A single-chip dual-bandtri-mode CMOS transceiver for ieee 802.11a/b/g wireless LAN,” IEEEJ. Solid-State Circuits, vol. 37, no. 12, pp. 2239–2249, Dec. 2004.

[20] T.-Y. Yang and H.-K. Chiou, “A 28 GHz sub-harmonic mixer usingLO doubler in 0.18-�� CMOS technology,” in Proc. Radio FrequencyIntegrated Circuit Symp., San Francisco, CA, Jun. 2006.

[21] A. Verma, L. Gao, and K. K. O. J. Lin, “A K-band down-conversionmixer with 1.4-GHz bandwidth in 0.13-�� CMOS technology,” IEEEMicrow. Wireless Compon. Lett., vol. 15, no. 8, pp. 493–495, Aug.2005.

[22] C.-S. Lin, P.-S. Wu, H.-Y. Chang, and H. Wang, “A 9–50-GHz Gilbert-cell down-conversion mixer in 0.13-��CMOS technology,” IEEE Mi-crow. Wireless Compon. Lett., vol. 16, no. 5, pp. 293–295, May 2006.

[23] F. Ellinger, “26–34 GHz CMOS mixer,” Electron. Lett., vol. 40, no. 22,pp. 1417–1419, Oct. 2004.

[24] F. Ellinger, “26.5–30-GHz resistive mixer in 90-nm VLSI SOI CMOStechnology with high linearity for WLAN,” IEEE Trans. Microw.Theory Tech., vol. 53, no. 8, pp. 2559–2565, Aug. 2005.


[25] M. Bao, H. Jacobsson, L. Aspemyr, G. Carchon, and X. Sun, “A9–31-GHz subharmonic passive mixer in 90-nm CMOS technology,”IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2257–2264, Oct.2006.

[26] T.-Y. Yang and H.-K. Chiou, “A 16–46 GHz mixer using broadbandmultilayer balun in 0.18-�� CMOS technology,” IEEE Microw. Wire-less Compon. Lett., vol. 17, no. 7, pp. 534–536, Jul. 2007.

[27] J. A. Weldon, R. S. Narayanaswami, J. C. Rudell, L. Lin, M. Ot-suka, S. Dedieu, L. Tee, K.-C. Tsai, C.-W. Lee, and P. R. Gray, “A1.75-GHz highly integrated narrow-band CMOS transmitter withharmonic-rejection mixers,” IEEE J. Solid-State Circuits, vol. 36, no.12, pp. 2003–2015, Dec. 2001.

[28] H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: a simple phys-ical model,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 15–25, Jan.2000.

[29] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixersand polyphase filters for large image rejection,” IEEE J. Solid-StateCircuits, vol. 36, no. 6, pp. 873–887, Jun. 2001.

Mohamed El-Nozahi (S’00) received the B.Sc. andM.Sc. degrees in electrical engineering from AinShams University, Cairo, Egypt, in 2000 and 2004,respectively, and the Ph.D. degree from Texas A&MUniversity, College Station, TX, in 2010.

From 2000 to 2004, he was a Teaching and Re-search Assistant with the Electronics and Communi-cations Engineering Department, Ain Shams Univer-sity. In 2007, he was a Design Intern with Texas In-strument Incorporated, Dallas, TX. In 2009, he wasa Design Intern with Qualcomm Inc., San Diego CA.

Since 2006, he has been with Marvell Semiconductor Inc., Santa Clara, CA,where he is a Senior RF Design Engineer. His research interests include trans-ceivers system and circuit design at millimeter-wave frequencies and powermanagement integrated circuits.

Mr. El-Nozahi was the co-recipient of the 2009 Semiconductor Research Cor-poration (SRC) Design Challenge Award, and TI Excellence Fellowship from2006 to 2009.

Ahmed Amer (S’05) received the B.Sc. degreein electronics and communications (Hons.), andthe M.Sc. degree in electronic engineering fromAin Shams University, Cairo, Egypt, in 2002 and2006, respectively, and is currently pursuing thePh.D. degree from Texas A&M University, CollegeStation.

From 2002 to 2006, he was a Teaching and Re-search Assistant in the Electronics and Communica-tions Engineering Department at Ain Shams Univer-sity. From 2004 to 2006 he was an RFIC design en-

gineer with SysDSoft Inc., Cairo. During 2008 and 2009, he was an Intern inthe medical group at Texas Instruments Incorporated, Dallas, TX.

Mr. Amer was the co-recipient of the SRC/SIA Design Challenge Award in2009, the Fouraker/Ebensberger Fellowship in 2007, and Texas Instruments Ex-

cellence Fellowship in 2008 and 2009. His research interests include power-management electronics, biomedical electronics, and wideband/multiband RFreceivers design.

Edgar Sánchez-Sinencio (F’92) was born in MexicoCity, Mexico. He received the degree in commu-nications and electronic engineering (Professionaldegree) from the National Polytechnic Institute ofMexico, Mexico City, in 1966, the M.S.E.E. degreefrom Stanford University, Stanford, CA, in 1970,and the Ph.D. degree from the University of Illinoisat Champaign-Urbana in 1973.

His research work has more than 2650 citations ac-cording to the Thomson Reuters Scientific CitationIndex. He has graduated 42 M.Sc. and 34 Ph.D. stu-

dents. He is a coauthor of six books on different topics, such as RF circuits,low-voltage low-power analog circuits, and neural networks. Currently, he isthe TI J. Kilby Chair Professor and Director of the Analog and Mixed-SignalCenter at Texas A&M University. His research interests are in the area of powermanagement, RF communication circuits, as well as analog and medical elec-tronics circuit design. Dr. Sánchez-Sinencio is a former Editor-in-Chief of IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS II.

Dr. Sánchez-Sinencio received the Honoris Causa Doctorate from the Na-tional Institute for Astrophysics, Optics and Electronics, Mexico, in 1995. Thisdegree was the first honorary degree awarded for microelectronic circuit-de-sign contributions. He is a Co-Recipient of the 1995 Guillemin-Cauer Awardfor his work on cellular networks. He was also the Co-Recipient of the 1997Darlington Award for his work on high-frequency filters. He received the IEEECircuits and Systems Society Golden Jubilee Medal in 1999. He also receivedthe prestigious IEEE Circuits and Systems Society 2008 Technical AchievementAward. He was the IEEE Circuits and Systems Society’s Representative to theIEEE Solid-State Circuits Society during 2000–2002. He was a member of theIEEE Solid-State Circuits Society Fellow Award Committee from 2002 to 2004.He is a former IEEE Circuits and Systems Vice President-Publications.

Kamran Entesari (S’03–M’06) received the B.S.degree in electrical engineering from Sharif Uni-versity of Technology, Tehran, Iran, in 1995, theM.S. degree in electrical engineering from TehranPolytechnic University, Tehran, in 1999, and thePh.D. degree from the University of Michigan, AnnArbor, in 2005.

In 2006, he joined the Department of Electricaland Computer Engineering at Texas A&M Uni-versity, College Station, where he is currently anAssistant Professor. His research interests include

the design of radio-frequency/microwave/millimeter-wave integrated circuitsand systems, RF microelectromechanical systems, related front-end analogelectronic circuits, and medical electronics.

Dr. Entesari was the Co-Recipient of the 2009 Semiconductor Research Cor-poration (SRC) Design Contest Second Project Award for his work on dual-bandmillimeter-wave receivers on silicon.

Documents

IEEE TRANSACTIONS ON MICROWAVE THEORY AND …kentesar/Kamran_J14.pdf · The transceiver is based on a direct conversion re-ceiver architecture along with a dual-band LNA and frequency