Poster Session 111 : Low Power & High Performances Approaches

Design Guidelines for Leakage Control Transistor Farzan Farbiz', Mohammad Emadi', Behjat Foruzandehl

'VLSl Lab., Electrical and Computer Engineering Dept., University of Tehran, Tehran, Iran 'VLSI Lab., Electrical Engineering Dept., Sharif University of Technology, Tehran, lran

f.farhiz@ece.ut.ac.ir, emadi@ee.sharif.edu, foruzandeh@ut.ac.ir

4bsrract- This paper investigates the effects of transistor sizing of the sleep transistor on the power consumption and speed. A method is proposed to handle the power-delay trade off and a new transistor arrangement is proposed. Simulations show how much is the appropriate size of sleep transistor respect to the gate size.

1. INTRODUCTION

Nowadays, demands for low battery supply voltages increased significantly. This, together with aggressive scaling of transistors, seems to he the most challengeable problem of 21" in IC design. Many efforts have been done to demonstrate various components of power consumption and to propose some ways to decrease it. Through these components, the one which is going to dominate other components is the leakage current and especially the sub-threshold current [ I ] . Fig. 1 shows how this component becomes more and more important by shrinking the channel length of transistor [2].

There are a variety of methods for leakage reduction in digital CMOS ICs. Some of them affect on the current by increasing the threshold voltage of some or even all of the transistors in the chip. Dual threshold voltage technique [3], MTCMOS [4], adaptive substrate biasing [5 ] and using dual gate devices [6] are categorized into this group. While they reduce the power consumption effectively, they usually need complicate fabrication process and sometimes, many undesirable extra circuits.

Leakage power usually is dominant component in the stand hy operation i.e. when the circuit is idle. In this mode, the value of the output is not important. There are various proposed methods to decrease the leakage power in this case and among them, stack transistor insertion, is one of the easiest and most effective methods in which addition of limited number of transistor leads to significant power saving [7]. The other benefit is that there is no need for any extra manufacturing process.

The other suitable technique is input vector control method [SI. Taking into account that the output value during the stand by mode is not valuable, one could find an optimum set of input to reduce the power consumption.

This papers deals with the effective combination of stack transistor insertion method and input vector control technique. Section 11 investigates the input vector technique. stack insertion method is explored in Section 111 and the combined method in section IV including proposing a new configuration. Sizing consideration for both of the proposed and conventional methods is examined in section V.

11. INPUT VECTOR CONTROL

The idea is to reduce the sub-threshold current in stand by mode by assigning a set of input values that leads to minimum power consumption. It should he noted that while the circuit is in the stand by mode, its output values are not important and that is why the circuit inputs can be set arbitrary. This optimum selection can he found by excessive simulation or by using some intelligent algorithms [9].

111. STACK TRANSISTOR INSERTION

It was shown in [7] that the insertion of an off transistor below the stack as is shown in Fig. 1, decreases the suh- threshold current. Although the reason can he extracted by mathematical formulas driven by equaling the current of series transistors 191, it can be interpreted that by increasing the number of off transistor in a stack, the equivalent resistor between supply voltage is increased and hence, less amount of current flows through the circuit.

This stack transistor is added to the NMOS network or the PMOS network in each gate according to the stable value of gate output in stand by mode (Fig. 2). If the output of the gate is assumed to he 'l', the sub-threshold current flows toward the NMOS transistors, and adding an off transistor to the NMOS stack, reduces it. On the other hand, if the gate output is 'O', stack transistor must he added to beside the PMOS network.

In both of these cases, the transistor may be added to the top of the stack or at the bottom of other transistors as illustrated in Fig. 3. This proposed placement influences on the power and delay differently. The benefits of each case are shown in the next section.

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Fig. 1. Active and lekage power (constant die area).

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IV. COMBINED METHOD

Simultaneous Combination of the two mentioned methods leads to more amount of power saving in the stand by operation [ 111.

Firstly, the best input vector leading to minimum total leakage current is assigned to the circuit. After that, while the stable values of every node including the gate outputs are known, the appropriate NMOS or PMOS stack transistor is inserted to each gate. During the stand by mode, all of these transistors remain off while for the normal operation of the circuit, they must be turned ON. This is done by a signal called Seep Signa/. This signal simply determines whether the circuit is in the stand by mode or in the normal operation.

Besides benefiting leakage current in the stand by mode, it must be taken into account whether these added transistors affect on the circuit performance or not.

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- - - Fig. 3. Allemalive NMOS (left) and PMOS (right) sleep transislor inserlion methods.

Unfortunately, the answer is true. Without loosing the generality suppose a stack of NMOS transistors (NAND gate). Inserting another series transistor to this stack adds an equivalent resistor and capacitor to the RC chain network. Although this transistor remains always ON in the normal operation, it increases the fall time ('I' to '0' output transmission). This can be interpreted as decreasing speed in the normal operation as a cost of power saving in the stand by mode. The non-surprising speed-power trade off shows itself again in a new way. Now, the delay degradation is affected by the amount of power saving in the stand by mode.

This time, we have to seek for a parameter which is able to control the trade off. The only reasonable factor is the sizing of the inserted transistor which is considered in detail in the next section.

V. SIZING CONSIDERATION

By increasing the size of sleep transistor, its equivalent ON resistor decreases. Hence, the delay is reduced by increasing the size of this transistor. On the contrary, the higher WIL ratio leads to more sub-threshold current. Therefore, the power consumption and delay are affected by modulating the size of sleep transistor.

This trade off can be handled by optimizing energy delay product [9]. The target is to minimize the production of stand by power consumption and the delay. The optimum value of the sleep transistor W/L ratio strongly depends on the size of other transistors in the stack. Fig. 4 shows this dependency for an NAND gate simulated with .25 um technology model. Simulation is down with HSPICE. It is clear that the optimum value of the sleep transistor size is inversely related to the gate sire (NAND in this case). The size of the gate usually is determined in order to satisfy the minimum delay. This figure shows how much must be the size of sleep transistor for the best amount of stand by power saving while maintaining speed.

As mentioned before in section IV, it is possible to add the stack transistor beside the output node. In this way, the output capacitance is reduced and hence the dynamic power and speed are improved. The optimum EDP of the proposed case is better than the traditional method. This benefit was about 50% for a simple NAND configuration. Dependency of gate size to the sleep transistor size is shown in Fig. 5. The optimum sleep transistor width is proportional to the gate size for this case.

On the contrary, addition of the sleep transistor to the bottom of the stack, make it possible to share all of the stack transistors together. This is not possible in the proposed method. Furthermore, adding a shared sleep transistor to all of the gates facilitates wiring of the sleep signal. Otherwise, when each gate needs a stack transistor near the its output; we have to consider more area overhead for the distribution of the sleep signal. Therefore, it is not possible to claim which configuration is the best before doing the post layout simulation.

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Poster Session 111 : Low Power & High Periorrnances Approaches

REFERENCES

Fig. 4. Sleep transistor size respect to gate size for minimum EDP. Transistor is inserted at the bottom of stack.

VI. CONCLUSION

Transistor sizing for combination of input vector control and sleep transistor insertion techniques is considered. A new sleep transistor arrangement is proposed which has its own benefits. Simulation for a .25 um NAND gate is delivered and it was shown that how much is the optimum size of inserted respect to the gate size.

ACKNOWLEDGMENT

The authors would like to thank Mr. Hadi Esmaeelzadeh at University of Tehran, and Mr. Mohammad Farazian at University of California San Diego for their assistances.

[I] 2. Chen. et. al.. "Estimation of standby leakage power ih CMOS circuits considering accurate modeling of transistor Stacks," International Symposium an Low Power Design and Electronics. 1998. D. Duarte, N. Vijayknshnan, M.J. Itwin, H. S . Kim, G. McFarland, "Impact of Scaling on The Effectiveness of Dynamic P o w ~ r Reduction Schemes." Proceedings of the 20th Inter.nariona1 Cotference on ComprrtevDesigm (ICCD), Sep.. 2002. L. Wei, Z. Chen, K. Roy, M. C. Johnson, Y. Ye. and V. De. "Design and optimization of dual threshold circuits for IOW voltage low power app1ications:'lEEE Tron. VLSISvsl., vol. 7, pp. 16-24, Mar. 1999. S . Mutoh et al., "I-V power supply high-speed digital circuit technology with multithreshald-voltage CMOS," IEEE J. Solid-Stale Cirrsits, vol. 30, pp. 847-853, Aug. 1995. T. Kobayashi and T. Sakumi, "Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation," in Pwc. IEEE Custom Integrored Circuit5 CO@, 1994, pp. 271-274. J. Gil. M. le, 1. Lee. and H. Shin, "A high speed and low' power SO1 inverter using active body bias," in Proc. Svnip. Low Power- Electron. Derign, 1998, pp. 59-63. 2. Chen, et. al., "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor Stacks," Inlernorionnl Svmposiun! on LON' Power Design and Electronics, 1998. M. C. Johnson, D. Somasekhar, and K. Roy, "Models and algorithms for bounds an leakage in CMOS circuits," IEEE Trans. On Cmputer-.-Aided Design IntegraiedCiiruilsSvsl., vol. 18, pp. 714-725, June 1999. F. Farbiz, M. Farazian, M. Emadi, K. Sadeghi, "Sizing consideration for leakage control transistor." Proceeding of 17" International Conference on VLSl Desig, pp. 639-641, Jan. 2004.

[IO] KM C. Johnson, D. Somasekhar, and K. Roy, "A model for leakage control by MOS transistor stacking," Technical Report TR-ECE 97-12, Purdue University, School of Electrical and Computer Engineering, 1997.

[ I l l M. C. Johnson et al. "Leakage control with efficient use of transistor stack in single threshold CMOS," IEEE Transaction on VLSl Systems, VOL 10,NO. l.Feb.2002.

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Fig. 5 . Sleep eansistor size respect to gate size for minimum EDP. Transistor is insetted at the too of stack.

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