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Vis i t us at e-GRID.netNovember 2007
CHAPTER MEETINGS
Monterey - 11/1 | Radar History Update - multiple claims of invention, new information now available ... [more]
SCV-CS - 11/3 | One-day Seminar: New Frontiers in Computing Technology - 8 speakers ... [more]
SCV-LEOS - 11/6 | The Intimate Integration of Photonics and Electronics for Computing and Switching Systems ... [more]
SPECTRUM - 11/7 | Portable Designs with High-Power Batteries and Chargers - cell configurations, electrical performance, limits ... [more]
SCV-MTT - 11/8 | Advances in Silicon-on-Insulator Switch Technology for Highly Integrated Cellular Front-ends ... [more]
SCV-SPS - 11/12 | Efficient Techniques for MPEG-2 to H.264 Video Transcoding - same quality with about half the data rate ... [more]
SCV-EMC - 11/13| Experimental and Theoretical Analysis of Electromagnetic Shielding of Cables and Connectors ... [more]
SCV-EDS - 11/13| 450mm Wafers: What will it Cost to Get There? - wafer size transitions, costs, benefits, alternative scenarios ... [more]
SF-EMB - 11/13| Dynamic Contrast-Enhanced MRI of Prostate Cancer - evaluating functional properties of the tissue ... [more]
SCV-Nano - 11/13| Nanotech: Imagine the Possibilities! - half day symposium with 8 talks ... [more]
SCV-CPMT - 11/14 | Robust Electronic Assembly without Solder: Eliminating both Tin-lead and Lead-free... [more]
SCV-ComSoc - 11/14 | Advances in Reliable Information Delivery over Tactical Networks - operation in rugged environments ... [more]
OEB-IAS - 11/15 | Industrial Plant Adaptive Load Shedding: Beyond PLC Control - maintaining critical loads ... [more]
SCV-CAS - 11/19 | China's IC Design Industry Status Today - strengthening design capabilities, reducing reliance on imports... [more]
SCV-RAS - 11/19 | First Steps Towards Community Robotics - CMU's CREATE Lab projects for technology empowerment ... [more]
SCV-Mag - 11/21 | High Magnetic Anisotropy Materials - from bulk through multilayers to nano-scaled particles ... [more]
SF-IAS - 11/27 | Digital Paralleling & System Design - load sharing, synchronization, genset protection issues, system topologies ... [more]
OEB-PES - 11/29 | Selection and Applications Of Power Factor Correction Equipment for Industrial/Commercial Facilities ... [more]
SCV-CE - 12/4 | "TV 2.0" - Digital TV in the Networked Home - commercial and behavioral challenges ... [more]
SF-PES - 12/13 | Electrical Out-of-Step Protection - loss of synchronism during stressed power system conditions ... [more]
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Assoc. Professor position page 7
Professional Skills Courses [more]- Mastering Your Presentation Skills - Breakthrough Project Management - Career Design Workshop - Finance for Non-Finance Professionals - Transitioning from Individual Contributor to Mgr
Technical Skills Courses/Seminars [more]- Digital VLSI Design with Verilog - MATLAB & Simulink for Design &
Digital Signal Processing - Advanced Semiconductor Technology & Fab’n - Practical Considerations for Low Power Design
Implementation in CMOS - ESD Design for Nano-Scale CMOS Technologies
Workshops and Seminars
Building Custom VoIP Applications - Oct 31 - Webinar (5 PM) [more]
Developing and Deploying Advanced Communications over the IP Network - Nov 7 - Santa Clara Marriott [more]
Vibro-Acoustics Simulation Seminar - Dec 13 - Santa Clara Marriott [more]
Upcoming Conferences
Nov 4-8: Int’l Symposium for Testing and Failure Analysis - San Jose Convention Center [more]
Nov 12-15:Printed Electronics USA 2007 - South San Francisco Conference Center [more]
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 2
Your Networking Partner ®
November 2007 • Volume 54 • Number 11
IEEE-SFBAC ©2007
IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs. IEEE GRID is published as the GRID Online Edition
residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.
Editor: Paul Wesling IEEE GRID PO Box 2110 Cupertino CA 95015-2110 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net
From the editor . . . Last weekend, and earlier this week, I was in
Southern California. As the Santa Ana winds picked up, and newscasts relayed breaking news of wildfires in a number of the canyons, it brought back memories of when I was in junior high school, living in San Bernardino. I had a morning paper route, and of course I rode my bicycle to fold and deliver the papers. When the hot Santa Ana winds blew, it was a struggle to keep the bike upright and to peddle it into that strong wind. And I have vivid memories of fires along the mountain ridgetops above Lake Arrowhead and Big Bear Lake, lending an eerie glow to the night sky and raining ashes into the valley.
While the encroachment of suburbia into the foothills and forests has increased the danger and destruction of these wild fires, technology has gone a long way to lessening the damage and loss of life. Last week, satellites relayed information about weather patterns days in advance, allowing forecasters to predict exactly when the Santa Anas would begin blowing. The State was able to pre-position fire-suppression teams a few days before the Malibu outbreak and throughout the three main canyons down which the winds blow – Santa Clara, Cajon, and Banning passes. “Reverse 911” calls to residents allowed for early evacuations of full neighborhoods, while Ham radio backed up the emergency services communications systems.
This was quite an improvement over the situation with the Oakland Hills firestorm of a dozen years ago, and we’ve learned many lessons. Yes, many emergency-services communications systems still don’t interoperate, and a number of counties have too few fire teams. But we’re making progress.
Waking on Monday morning in Long Beach, I could smell the smoke from the Irvine fires, miles away. Soot and fine powder settled on our cars, and the sun rose orange-red above the eastern mountains. On my drive back up to the SF Bay Area on Wednesday, I saw another line of forestry fire trucks making their way down the freeway, to relieve teams already in place.
Paul Wesling, editor
NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net
DIRECTORS
Santa Clara Valley Fred Jones
Tom Coughlin
Oakland East Bay Bill DeHope
Victor Stepanians
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OFFICERS Chair: Tom Coughlin
Secretary: Bill DeHope Treasurer: Dan Sparks
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N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 3
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N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 4
Based on AutoSEA2, the industry standard for mid and high frequency noise and vibration analysis, VA One offers a unique and unprecedented combination of all standard vibro-acoustics simulation methods: Statistical Energy Analysis (SEA), Finite Element Analysis (FEA) and the Boundary Element Method (BEM).
Who Should Attend? • Current AutoSEA2 and SEA users and managers, • Current BEM users and managers, • Current FE acoustic software users and managers, • Vibration, acoustics and dynamics engineers, • Structural Analysts, • CAE professionals
Applications • Vibro-acoustics • Dynamic Environ-ments • Random Vibration Analysis • Structure-borne Vibration • Pre-test Simulation • Mid-Frequency Analysis Co-Sponsor: Santa Clara Valley Section, IEEE
Digital VLSI Design with Verilog 12 week course, M/W 6:00PM-9:00PM (Starts Nov 19) Learning language constructs in a progressively more complex project environment. Synthesis of gate-level netlists from behavioral, RTL, and structural code; constraints most useful for area and speed optimization; partitioning, safe coding styles….
MATLAB & Simulink for Design & Digital Signal Processing 12 week course, M/W 6:00PM-9:00PM (Starts Nov 19) Hands-on, from basic concepts in discrete time systems, filter design and implementation all the way to advanced concepts of multi-rate systems; balanced mix of theory and practice.
PCB Layout Design 12 week course, M/W 6:00PM-9:00PM (Starts: Dec 3) Process, tools, methodology using PADS (Mentor Graphics); schematics, printed circuit board layouts, symbols, and wiring diagrams, design software and techniques.
Discount of $40 for IEEE Members on 12-week courses.
Thursday, December 13
10:00 AM - 2:30 PM
Santa Clara Marriott
No cost – lunch will be provided
9:30AM: Registration Opens 10:00AM: VA One: Introduction & Overview 10:30AM: Low Frequency Deterministic Methods 11:15AM: SEA 12:00PM: Lunch 1:00PM: Hybrid Methods (FE/BEM/SEA) 2:30PM: Close
Discover why, with these latest developments, VA One is the ONE tool you need for full spectrum vibro-acoustic simulation. Please join us for this FREE seminar and automatically enter to win an Apple iPod nano!
Access is limited, and pre-registration is highly recommended. Visit: www.esi-group.com (select “Events”)
Download the Seminar flyer to register by FAX:
www.e-grid.net/docs/0712-esi.pdf Upcoming 1- and 2-day Seminars:
Nov 8-9: Advanced Semiconductor Technology & Fabrication
Nov 13: Design-for-Yield & Design-for-Manufacturing - Principles and Challenges
Nov 15: Practical Considerations for Low Power Design Implementation in CMOS
Nov 16: ESD Design for Nano-Scale CMOS Technologies
Nov 29: Device & Interconnect Reliability in Advanced CMOS
Discount of $30 for IEEE Members on Seminars. Get more information:
www.svtii.com/SVTI-calendar.htm
Review all SVTI offerings: www.svti.org
SILICON VALLEY TECHNICAL INSTITUTE
Autumn Courses with labs
Radiated Sound Power from Desktop Tower
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 5
Join the leader in unified group communications software for a discussion to expand your Integrator and Solution Developer business with WAVE. Twisted Pair Solutions strategically aligns with partners for delivering real-time communications to the growing marketplace.
If you are passionate about developing and deploying advanced communications over the IP network to varied markets – such as energy, federal, financial, military, public safety and transportation – we want to talk.
Partner Connect - Silicon Valley Agenda (free)
Wednesday, November 7, 2007
Santa Clara Marriott, 2700 Mission College Blvd.
9:00 - 10:00: Partner Connect Breakfast followed by breakout sessions for potential defense and government solutions partners
12:00 - 1:00: Partner Connect Lunch followed by breakout sessions for potential commercial solutions partners
Pre-registration for either event is required. Register Now:
www.twistpair.com/connect IEEE Professional Skills Courses
Mastering Your Presentation Skills – Date/Time: Thurs/Fri Nov 8-9, 8:30AM – 4:30PM – Location: – Trimble Navigation, Sunnyvale
Fee: $850 for IEEE Members; $795 non-members
Breakthrough Project Management – Date/Time: Thurs/Fri Nov 8-9, 8:30AM – 4:30PM – Location: – TIBCO Software, Palo Alto
Fee: $600 for IEEE Members; $675 non-members
Career Design Workshop – Date/Time: Tuesday Nov 13, 8:30AM – 4:30PM – Location: – Cypress Semiconductor, San Jose
Fee: $375 for IEEE Members; $450 non-members
Improve your skills – register for one of these classes, or for others coming up this fall and winter. Bring a team!
Integrators Optimal unified group communications is now attainable by all of your customers. Built on open standards, WAVE software removes proprietary hardware barriers and makes voice, data, and video convergence a reality. With tens of thousands of WAVE users worldwide, trusted partners continually reap the benefits of established technology, brand equity, and rapid deployment for improving situational awareness and business continuity.
Solution Developers Technology should not get in the way of creating communications solutions. The Solution Developer Program provides everything needed by ISVs and OEMs to try, build and sell custom applications. Partners customize to differentiate, get to market quickly, and develop on a proven platform. By building your solutions on WAVE, you start off with years of development time, mission critical field testing, and real world optimization.
SCV Chapters, Engineering Management & Components, Packaging and Manufacturing Technology Societies
Finance for Non-Finance Professionals
– Date/Time: Wednesday Dec 5, 8:30AM – 12:30PM – Location: – Cypress Semiconductor, San Jose
Fee: $275 for IEEE Members; $325 non-members
Transitioning from Individual Contributor to Manager
– Date/Time: Thursday Dec 6, 8:30AM – 4:30PM – Location: – Tibco Software, Palo Alto
Fee: $375 for IEEE Members; $450 non-members
For complete course information, schedule, and registration form, see our website:
www.EffectiveTraining.com
Grow Your Unified Group Communications Business with WAVE™
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 6
Short Courses: Saturday, Nov 3 & Friday, Nov 9 Tutorials: Sunday & Monday, Nov 4-5 Sessions: Tuesday-Thursday, Nov 6-8 Exposition: Tuesday-Wednesday, Nov 6-7
Returning to San Jose, the heart of Silicon Valley, ISTFA’07 combines technical sessions, tutorials, an exhibition, and user group meetings with a focus on making the full experience a strong benefit for the attendee. The limited number of selected, high-quality papers only requires two tracks throughout the program, for good access.
16 Technical Sessions & Panel Discussions: • In-line Metrology and Inspection • Emerging Concepts • System Level Analysis • Optical Techniques • Failure Analysis Process • Circuit Edit for FA, FI, and Debug • Case Histories • SPM Techniques • Sample Preparation • Nano Probe • Yield Enhancement • Photon Based Techniques • Package and Assembly • MEMS • Metrology and Materials Analysis • Test • plus Poster Papers
47 Educational Tutorials – 10 All New! We continuously update the tutorial sessions with new and cutting-edge topics related to failure analysis. • Materials Characterization – Surface Analysis in Assembly • Materials Characterization for Failure Analysis • Failure Localization with Active and Passive Voltage Contrast in FIB and SEM • Failure Analysis Flow Decision Tree • The Role of the AFM in Yield and Failure Analysis • The Pivotal Role of AFP Nanoscale Failure Analysis • Introduction to and Reliability in MEMS Packaging • Analog Building Blocks: Circuits and Devices • Diagnosing Analog Circuits • Yield Basics for Failure Analysis including 300mm Water and Cu Technology (and more!)
4 Technology-Specific User Groups User Group meetings on Tuesday evening and Wednesday morning, to provide a convenient forum for users of a specific technique to meet, share ideas, and discuss relevant issues in a non-commercial environment. Planned topics this year:
• Finding the Defect • Getting Inside the Chip • Focused Ion Beam (FIB) Techniques • Characterizing the Defect
5 One-Day Pre- & Post-conference Short Courses: • EOS & ESD Basics: Principles and Applications to
Failure Analysis • Fault Isolation • Finance and Management of Failure Analysis:
Principles and Applications • Focused Ion Beam (FIB) Systems: FAQs,
Principles, and Applications • Scanning Probe Microscopy: Introduction and
Applications
2007 Keynote Address: “New Technology: Silicon Photonics Opportunity, Challenges & Applications,” Dr. Mario Paniccia, Director, Photonics Technology Lab, Corporate Technology Group of Intel Corporation Dr. Paniccia currently directs a research group with activities in the area of Silicon Photonics. The team is focused on developing silicon-based photonic building blocks for future use in enterprise and data center communications.
ISTFA is the best venue for learning new failure analysis techniques, challenges and directions. It also provides ample opportunities for you to participate and network through the question-and-answer periods, the user groups, the panel discussions, the exhibition, and the networking poster luncheon. Additional information is on the ISTFA web site:
www.ISTFA.org
Register online at:
www.istfa.org/registration
Discounted fees for EDFAS and ASM Members. Non-members of EDFAS receive a full year’s membership with their registration. Tutorials and Symposium-only registrations are available. To exhibit at ISTFA, please contact Kelly Thomas at
EDFAS General Membership Meeting Wednesday, November 7, 12:25-1:45 pm
The Electronic Device Failure Analysis Society (EDFAS) annual General Membership Meeting is open to all current members, as well as interested prospective members.
33rd International Symposium for Testing and Failure Analysis
November 4-8, 2007 San Jose Convention Center
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 7
The fourth annual Printed Electronics USA is aimed at product developers, end-users, researchers, scientists and venture capitalists. This event is the only one to cover all of organic and printed inorganic electronics. In particular, we look at routes to commercialization with views from major adopters. Companies from around the world will present their progress in this technology. Over 65 presentations from leading global companies, including Kovio, Hasbro, Sony, Samsung, LG Philips, STMicroelectronics, T-Ink, PARC, Plastic ePrint. Investment Summit: High-quality printed electronics investment opportunities and perspectives Visit the world’s biggest exhibition for printed electronics with 50 exhibition booths showing printed electronics in action. Special tours to see several Bay Area companies including Fujifilm Dimatix, the Organic Electronics Group at the University of California, and other facilities.
Nov 12-15, 2007
South San Francisco Conference Center
Full technological analysis is given on all areas of printed electronics including logic/memory, displays, power, sensors, materials, and manufacturing technologies. Detailed presentations include device roadmaps, performance, precious material supply, costs, and impediments to overcome.
Masterclasses The four optional expert-led masterclasses are interactive consultancy sessions. At each masterclass you will have the chance to handle many samples, and take away printed copies of presentations. They will ensure you get the most from the conference and leave with answers to your questions.
• Introduction to Printed Electronics • Displays & Lighting • Printing Technologies • RFID & Its Progress towards Being Printed
For more information and to register:
www.idtechex.com/printedelectronicsusa07
Printed Electronics USA 2007 Converging Printing with Electronics: Commercializing the Technology Organic & printed inorganic electronics
UNIVERSITY OF CALIFORNIA, SANTA CRUZ COMPUTER ENGINEERING
Associate/Full Professor
The Computer Engineering Department, UC Santa Cruz, invites applications for a faculty position:
Position #808: The Computer Engineering Department invites applications for a tenured (Associate or Full Professor) position in Autonomous Systems. Potential areas of specialization include robotics, control, mechatronics, and assistive technology. The department is launching an initiative in autonomous systems and mechatronic engineering, and seeks an individual to join our core faculty in this area and lead the development of new research and degree programs.
MINIMUM QUALIFICATIONS: Ph.D. in Computer Engineering, Mechanical Engineering, Electrical Engineering, or related field; demonstrated excellence in innovative research; a strong record of publications; proven distinction in university teaching at the graduate and undergraduate levels; and a proven track record for securing extramural funding.
MORE DETAILS: www.soe.ucsc.edu/jobs, Position #808. To ensure full consideration, applications must arrive by Jan. 1, 2008. EEO/AA/IRCA Employer.
Submit: CV, statement of research and teaching plans, URLs of selected reprints, and names of three people who are willing to write letters of recommendation, by Jan. 1, 2008. We prefer electronic applications: www.soe.ucsc.edu/jobs/faculty/apply. Alternatively, applications may be mailed to: Computer Engineering Search Committee, University of California, 1156 High Street MS: SOE3, Santa Cruz, California 95064.
Clearly indicate position: #808 (Associate/Full Professor, Assistive Technology). UCSC is the UC campus nearest to Silicon Valley and has close research ties with the local industry. For
further details about the Baskin School of Engineering at UCSC, see www.soe.ucsc.edu
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 8
Radar History Update - New and Illuminating Information on that
“Bastard Invention” Speaker: Nicholas Willis Time: 3:00 PM Cost: none Place: Spanagel Hall Room 321, Naval
Postgraduate School, Monterey RSVP: required, for access to the NPS campus;
US citizens only; by email to D. Jenn, [email protected]
Web: www.e-grid.net/docs/0711-monterey.pdf
Mr. Nicholas Willis spent his career in the U.S. military-industrial complex, beginning with a NROTC scholarship to Stanford University and graduating with a degree in mathematics in 1956. He spent five years in the U.S. Navy serving on a destroyer and testing naval radars and missiles at White Sands Missile Range. He then joined industry to develop, evaluate and test radars and electronic warfare with Philco-Ford, SRI International and Systems Control, Inc. in Silicon Valley.
In 1976 he rejoined the U.S. Government for a five-year tour at the Defense Advanced Research Projects Agency to develop radars including Pave Mover, the forerunner of JSTARS. He returned to industry for his final 17 years designing and evaluating radars at Technology Service Corp. and Westinghouse Electric Corp., where he designed one of the F-22 radar modes. He also conducted radar and electronic warfare short courses.
Mr. Willis has published two books on bistatic radar and authored three book-chapters, two on bistatic radar and one on electronic warfare, along with two award-winning radar papers in a defense journal. He retired to Carmel Valley and consults for government and industry.
As usually happens during the ongoing development of a major invention, old information is released (or declassified) and new information surfaces. Such is the case with radar, in particular the first radar, Christian Hulsmeyer’s 1904 telemobilskop, and then the “re-discovery” of radar in its bistatic configuration in the 1930s.
This new information is summarized, including the multiple claims of invention, which led the great radar pioneer Lamont Blake to comment that “radar is one of those bastard inventions: one mother, many fathers.” Speculation about the utility of radar had it been embraced earlier closes the brief.
THURSDAY November 1Monterey Bay Subsection
Valon Technology, LLC
valontechnology.com
RF and Wireless Product Design & Development
- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness
Redwood City (650) 369-0575
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 9
One-day Seminar: New Frontiers in Computing Technology
Speakers: Eight academic and industry talks Cost: $50 for IEEE members, $55 non-members
(through Oct. 29) -- includes lunch, breaks Place: The Fremont Marriott, 46100 Landing
Parkway, Fremont RSVP: register from the website Web: www.cs.sjsu.edu/~tylin/ieeesilicon
Top speakers and experts from both Industry and the Research field: Richard M. Karp 1985 Turing Award Recipient. University of California Berkeley Lotfi Zadeh IEEE Medal of Honor, 1995. University of California Berkeley Dieter Fensel University of Innsbruck Yoav Shoham Stanford University Anant Jhingran IBM Silicon Valley Laboratory, USA "Enterprise Information Mashups: Integrating Information, Simply" Eric Brill Microsoft Research Andrew Tomkins Yahoo! Neel Sundaresan eBay Research Labs Registration Fees: IEEE or NATEA Members - On-site Registration = $60 - Online Registration = $50 Non-Members - On-site Registration = $65 - Online Registration = $55 All prices includes lunch and coffee breaks. Please complete online registration by 10/29
SATURDAY November 3SCV Computer
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 10
The Intimate Integration of Photonics and Electronics
for Computing and Switching Systems
Speaker: Ashok Krishnamoorthy, Sun Microsystems,
and IEEE LEOS Distinguished Lecturer Time: Networking and Food: 7:00 PM,
Presentation: 8:00 PM Cost: donation for refreshments Place: National Semiconductor Building E
Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: by email to ieeescvleos-rsvp2007 @yahoo.com
Web: www.ewh.ieee.org/r6/scv/leos Ashok V. Krishnamoorthy currently serves as
Distinguished Engineer & Director with the Sun Microsystems Microelectronics Physical Sciences Center in San Diego. Prior to that he was with AraLight as its President and CTO as part of a Lucent spinout, where he was responsible for leading product design and development for AraLight’s optical interconnect products. He also served as entrepreneur-in-residence at Lucent’s New Venture group, and as a member of technical staff in the Advanced Photonics Research Department of Bell Labs where he investigated methods of integrating optical devices to Silicon VLSI circuits. He received the BS in Engineering (Honors) from the California Institute of Technology, the MS in Electrical Engineering from the University of Southern California, and the Ph.D. in Applied Physics from the University of California, San Diego.
Dr. Krishnamoorthy serves on the technical advisory board for several optical technology start-ups and venture funds, and as a distinguished lecturer for LEOS. He holds 35 US Patents and has contributed 150 technical publications in optoelectronics, 5 book chapters and presented over 45 invited talks at international technical conferences. For his contributions to optoelectronics, and his service to technical societies, the Eta Kappa Nu society named him an Outstanding Young Electrical Engineer in 1999. He was awarded the 2004 International Prize in Optics by the ICO for his technical contributions to optics. He has also won several team awards, including Computerworld’s 2005 Horizon Award for Innovation. Most recently, he received the 2006 Chairman’s award for Innovation by Sun Microsystems for his work on optical interconnects.
In this talk, we review the motivations, challenges,
and potential for achieving “optical-interconnects-to-the-chip” via the intimate integration of photonics components such as lasers, detectors, and modulators with Silicon VLSI electronics. We review the progress made towards developing and commercializing this technology.
TUESDAY November 6SCV Lasers and Electro-Optics
Patent Agent Jay Chesavage, PE
MSEE Stanford 3833 Middlefield Road, Palo Alto 94303
www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 11
Advances in Silicon-on-Insulator Switch Technology for Highly Integrated Cellular Front-ends
Speaker: Tom McKay, RFMD Time: Refreshments and Social: 6:00 PM,
Presentation: 6:30 PM Cost: none Place: National Semiconductor, Bldg #9,
Classroom #4, 2900 Semiconductor Dr, Santa Clara
RSVP: not required Web: www.mtt-scv.org/nov_mtg.html
Since receiving his MSEE from the University of Wisconsin-Madison in 1984, Tom McKay has developed high frequency ICs in both lead and individual contributor roles. In 1997 he received the Samsung Chairman’s Award for contribution in the area of low noise ICs for television. In 1998, as a Principal Engineer at VLSI Technology, Tom led efforts establishing 180 nm generation digital CMOS as a competitive RF technology. In 2000, Tom co-founded Zeevo which by 2002 released the first 180 nm CMOS Bluetooth RF system-on-chip, with volume shipments in the PDA market. Zeevo was acquired by Broadcom in 2005. For the past four years Tom has led technology projects targeting the cellular market, with focus on CMOS synergistic radio techniques. Tom has authored or co-authored several technical journal and conference papers and holds several patents. .Tom McKay is currently working as a principal engineer at RFMD in Scotts Valley.
Silicon-on-insulator (SOI) technology is shipping
into several mainstream consumer markets, such as laptops and game consoles, driving down substrate manufacturing costs. By increasing substrate resistivity, it is possible to achieve multi-watt power handling, low harmonic distortion and robustness in multi-throw RF switch circuits. If the device layer is kept relatively thick, the process and design flow are very similar to bulk, easing integration. Fabricated in a 180 nm generation dual-oxide process, a prototype six-throw antenna switch achieves P-0.1dB of about 40 dBm at 900 MHz and harmonics of 75 dBc at 34 dBm out, results normally attributed to sapphire or GaAs based technologies. While most radio functions can be implemented in standard CMOS, this level of switch performance may differentiate SOI on high-resistivity substrate for RF. Given these and other results, this technology may lower the barrier to low-cost highly integrated RF systems which include the antenna interface.
THURSDAY November 8SCV Microwave Theory and Techniques
M E S OIn t eg r at io n
Let us help you integrate your product and get it into production • MEMS & Sensors Experts • Product Design ▪ R&D ▪ Failure Analysis • Medical Devices ▪ High-Volume Manufacturing • Experienced Consultants www.MesoIntegration.com
[email protected] TEL: 949.278.0275
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Experimental and Theoretical Analysis of Electromagnetic
Shielding of Cables and Connectors
Speaker: Dr. Lothar (Bud) O. Hoeft, Consultant,
Electromagnetic Effects Time: Social and Dinner at 5:30 PM, Presentation:
6:30 PM Cost: none Place: Applied Materials Bowers Cafeteria, 3090
Bowers Ave., Santa Clara RSVP: not required Web: www.scvemc.org
Dr. Bud Hoeft received a B.S. and M.S. in physics from the University of Wisconsin and a PhD in physics and biophysics from Pennsylvania State University. In 1979, he completed a 25-year R&D career in the U.S. Air Force working on acoustical noise control, bionics, nuclear weapon simulation, pulse power technology and international R&D coordination. He joined BDM, where he was primarily concerned with helping designers build and test systems that are hard to electromagnetic effects. In 1994, he retired from BDM and became a private consultant. Dr. Hoeft is a Certified EMC Engineer. He has presented numerous papers and tutorials on shielding and electromagnetic effects at IEEE-EMC, NEM, Zurick-EMC, Wroclaw-EMC, IEE-EMC, Lightning and IICIT symposia. In 2001, he was appointed Distinguished Lecturer of the IEEE EMC Society for 2001 and 2002. In 2007, he received the Richard R. Stoddard Award from the IEEE EMC Society.
Shielded cables and connectors have been
important techniques for keeping voltages and currents from causing problems by radiating from or by upsetting/damaging important electronic systems. The intrinsic electromagnetic property of a cable or connector shield is its surface transfer impedance. This is the ratio of the longitudinal open circuit voltage measured on one side of the shield (normally the inside) to the axial current on the other side (normally the outside). In cases where a high electric field is present at the surface of the shield, the transfer admittance or charge transfer elastance is also important. The surface transfer impedance of typical cables, connectors, backshells and cable terminations has been measured and can be explained by simple models.
TUESDAY November 13SCV Electromagnetic Compatibility
ANSYS Channel Partner
• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses
Ozen Engineering (408) 732-4665
[email protected] www.ozeninc.com
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Efficient Techniques for MPEG-2 to H.264 Video Transcoding
Speaker: Jun Xin, Xilient Inc. Time: Fast food and drinks: 6:30 PM, Presentation:
7:00 PM Cost: $2 donation toward refreshments Place: National Semiconductor, Bldg #E, 2900
Semiconductor Dr, Santa Clara RSVP: not required Web: www.ewh.ieee.org/r6/scv/sps
Jun Xin received his Ph.D. degree from
University of Washington, Seattle, Wash, USA in 2002, in electrical engineering. Since April 2007, he has been with Xilient Inc., Cupertino, CA, USA. Before joining Xilient, he was a principal member of technical staff at Mitsubishi Electric Research Laboratories (MERL), Cambridge, Mass, USA. From 1996 to 1998, he was a software engineer at Motorola-ICT Joint R&D Lab, Beijing, China. His research interests include digital video compression and communication. He has been an IEEE Member since 2003.
MPEG-2 has become the primary format for
broadcast video since being developed in the early 1990's. The new video coding standard, referred to as H.264/AVC, promises the same quality as MPEG-2 with about half the data rate. Since the H.264/AVC format has been adopted into new storage format standards, such as Blu-ray Disc, and HD-DVD, it is expected that H.264/AVC decoders will appear in consumer video recording systems soon. Certainly, as more high-definition contents become available and the desire to store more contents or to record multiple channels simultaneously increases, long recording mode will become a key feature for future consumer video recorders. To satisfy this need, novel techniques have been developed to transcode MPEG-2 broadcast video to the more compact H.264/AVC format with low complexity.
In this talk, transcoding techniques aimed for low-complexity MPEG-2 to H.264/AVC transcoding will be presented. Both intra and inter transcoding architectures and algorithms will be discussed. The key to a successful transcoder design is to take full advantage of the information already available from the MPEG-2 bitstream. Specifically, I am going to talk about efficient motion vector reuse and mode decision algorithms. I will show that the proposed algorithms achieve very good rate-distortion performance with low complexity. Compared with the cascaded decoder-encoder solution, the coding efficiency is maintained while the complexity is significantly reduced.
MONDAY November 12SCV Signal Processing
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450mm Wafers: What will it Cost
to Get There? Speaker: Dan Hutcheson, VLSI Research Inc. Time: Social at 6:00 PM, Presentation: 6:15 PM Cost: none Place: National Semiconductor Corp. Building E-1
- Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required Web: www.ewh.ieee.org/r6/scv/eds
Dan Hutcheson is CEO of VLSI Research Inc. He is a recognized authority and well-known visionary for the semiconductor industry whose career experience spans more than twenty years. Today Dan spends the majority of his time advising companies in strategic and tactical marketing; business management; and manufacturing trends, productivity, and strategy. During his career, Dan has authored numerous publications, developed many industry models, and researched most aspects of the semiconductor industry. Dan is probably best known for being the first to forecast an industry recession and for having developed the industry's first cost-of-ownership model in the early eighties. He also built the first factory cost-optimization model in 1984. Similar models are now the mainstay of capital decision-making. Dan holds a master's degree in Economics from San Jose State University and has completed additional engineering coursework from UC Berkeley.
Tensions are high as the industry confronts the issue of 450mm. Some believe it is absolutely necessary. It was scheduled in the ITRS roadmap to be ready by 2012 and believed essential to keep chip makers on Moore's cost/performance curve. Now it's been pushed out to 2015. Meanwhile, with 300mm just past the toddler stage, others believe 450mm will be a disaster and are fighting tooth and nail behind the scenes to stop it. Today, they represent the majority. It's not just the equipment makers who are in this camp. It is also the majority of chip makers. Many believe Moore's law must slow; that staying on it is unaffordable; that 450mm will lead to even worse scale problems than 300mm; and that if it happens the result will be more consolidation and even harder times.
In favor of the people arguing for it is the fact that every wafer size jump has met with resistance based on the same reasoning. But there are reasons to believe that this time things will be different. The industry's growth has slowed. Plus, 300mm proved to be incredibly painful for the equipment industry. Few argue with these differences.
This talk delves deeply into the history of wafer size transitions, examining their costs and benefits. It then examines alternative scenarios for 450mm. It is based on Dan's Chip Insider® articles.
TUESDAY November 13SCV Electron Devices
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Dynamic Contrast-Enhanced MRI of Prostate Cancer
Speaker: Dr. Susan Moyher Noworolski, Assistant
Professor, Department of Radiology, UC San Francisco
Time: Social at 6:00 PM, Dinner at 7:00 PM, Presentation: 7:30 PM
Cost: $25, $15 for Members, $10 for students Place: Sinbad’s Restaurant, Pier 2 Embarcadero
St., San Francisco RSVP: by Nov 1st to Bob Giebeler,
[email protected], 415-252-7214 Web: www.e-grid.net/docs/0711-sf-emb.pdf
Dr. Susan Moyher Noworolski is currently an Assistant Professor in the Department of Radiology at the University of California, San Francisco (UCSF). She is also a member of the UCSF/ UC Berkeley Joint Graduate Group in Bioengineering. Dr. Noworolski received her B.S. degree in biomedical engineering From the Johns Hopkins University in Baltimore, MD, while also satisfying the requirements for a B.S. in electrical engineering and receiving a minor in Psychology. She received her Ph.D. in bioengineering from the Joint Graduate Group in Bioengineering at UCSF and UC Berkeley.
During this talk, Dr. Noworolski will review the background of using MR imaging to study prostate cancer and will focus on the use of dynamic contrast-enhanced MRI (DCE MRI) to evaluate functional properties of the tissue. DCE MRI can provide information about the amount and permeability of blood vessels and the size of the interstitial space of the tissues. These can help in the identification of cancer and in the assessment of the aggressiveness of the cancer. However, interpretation of this data has some challenging aspects, both technically and biologically. Some of the issues involved in analyzing this data and in evaluating the measurements from patients with varying medical histories will be presented.
TUESDAY November 13SCV Engineering in Medicine and Biology
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Nanotech: Imagine the Possibilities!
Speakers: from IBM, Stanford, UC-Berkeley, SJSU,
Santa Clara U. Time: Light lunch and registration, 12:30 PM;
Symposium from 1:00 - 5:30 PM Cost: $50, $40 for IEEE Members, $20 for
students (by Oct. 30) Place: National Semiconductor Bldg E-1 CMA
Room. 2900 Semiconductor Drive, Santa Clara
RSVP: online registration at www.123signup.com/register?id=xyczq
Web: www.ieee.org/nano
A new symposium model celebrating local university graduate research at which graduate researchers present pre-publication briefs of their work and receive feedback on imagined potential opportunities for applications. Cosponsors: San Francisco Bay Area Nanotechnology Council Santa Clara Valley Section, Electron Devices Society Agenda 12:30 Light Lunch and Networking 1:00 Introduction 1:10 Invited Speaker – Charles Wade, Senior
Manager, Scientific Services Science & Technology, IBM Almaden Research Center
1:30 An Electronically Controlled Release Platform For Studying Cell Behavior
Elizabeth Hager-Barnard, Dept. of Materials Science and Engineering, Stanford
2:00 AFM-Compatible Near-Field Scanning Microwave Microscopy
Keji Lai, Dept of Applied Physics and Gaballe Laboratory, Stanford University
2:30 Simulating Novel EM Effects With TEMPEST Daniel Ceperley, Dept. of Electrical
Engineering & Computer Science, UC Berkeley
3:00 Break 3:20 Invited Speaker - Luis Mejia, Office of
Technology Licensing, Stanford University 3:40 RF Properties Of Carbon Nanofiber
Interconnects Francisco Madriz, Center for Nanostructures,
Santa Clara University 4:10 Hyperbranched Lead Selenide Nanowire
Networks Jia Zhu, Dept. of Electrical Engineering,
Stanford University 4:40 Characterization of sub-lithographic line
patterns from block copolymer self-assembly using X-Ray reflectivity
Lawrence Wang, Dept. of Chemical and Materials Engineering, San Jose State University
5:10 Conclusion & Networking
TUESDAY November 13SCV Nanotechnology and SCV Electron Devices
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Robust Electronic Assembly without Solder: Eliminating both
Tin-lead and Lead-free Speaker: Joseph (Joe) Fjelstad, President, Verdant
Electronics Time: Optional dinner at 6:30 PM, Presentation at
7:30 PM Cost: Dinner $25 (by Nov. 11); no cost for meeting Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101
frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
RSVP: by email to Janis Karklins, [email protected]
Web: www.cpmt.org/scv
Joseph (Joe) Fjelstad is founder and president of
Verdant Electronics. He has more than 35 years of international experience in electronic interconnection and packaging technology in a variety of capacities from chemist to process engineer and from international consultant to CEO. Mr. Fjelstad is also a well known author and magazine columnist writing on the subject of electronic interconnection technologies. Prior to founding Verdant, Mr. Fjelstad co-founded SiliconPipe, a leader in the development of high speed interconnection technologies. He was also formerly with Tessera Technologies, a global leader in chip-scale packaging, where he was appointed to the first corporate fellowship for his packaging innovations.
The electronics industry has assembled electronic components to printed circuit boards for more than 50 years. That relationship has been an enduring one, however with the transition from traditional tin-lead solder to new lead-free solders mandated by European legislation, the industry is being saddled with significant new expenses and plagued with problems not previously encountered. In this environment, an improved approach to electronics assembly without the use of solder is being developed. The process is being called the Occam Process in honor of the 14th century philosopher and logician, William of Occam, who stressed simplicity. The presentation will describe the process, its advantages, its challenges and its future and technology roadmap. The talk will include a review of the developers’ conference that will have been held a few weeks earlier in the month of October.
WEDNESDAY November 14 SCV Components, Packaging and Manufacturing Technology
Bernie Siegal
650-961-5900
[email protected] www.thermengr.com
Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures
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Advances in Reliable Information Delivery over Tactical Networks
Speaker: Shaun Botha, Co-Founder and Chief
Technology Officer, Twisted Pair Solutions Time: 6:00 PM Cost: none Place: National Semiconductor, Building E,
Conference Room, 2900 Semiconductor Dr, Santa Clara
RSVP: not required Web: www.ewh.ieee.org/r6/scv/comsoc
As an expert in interoperable communications infrastructure, Shaun Botha is an original developer of the WAVE(tm) unified group communications software technology used within information critical military, federal, public safety, financial, utility and transportation environments around the world. Prior to co-founding Twisted Pair Solutions, Shaun led Research and Development for Williams Communications, developed financial trading software for IP Blue, and created database applications for Merrill Lynch. He also co-developed the world's first software for reading smart cards. Shaun is a graduate of Cape Technikon in South Africa and holds a graduate degree in Computer Science.
Tactical computer networks are fluid and under
constant threat from physical and electronic dangers. They quickly merge and disengage, change and adapt based on current conditions and the communications needs of operators. In these rugged environments, sensitive and crucial information - often vital to the survival of personnel - still needs to flow no matter what. There are new, relevant lessons learned from in-theater military actions taking place as we speak. The most transferable one to watch for enterprises is the capability to optimize communications over low bandwidth mobile networks around the world. Our discussion will span operational requirements, delivery mechanisms and challenges facing industry for delivering information over tactical networks for unified communications.
WEDNESDAY November 14SCV Communications
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Industrial Plant Adaptive Load Shedding: Beyond PLC Control
Speaker: Greg Rauch, Field Sales Engineer,
Schweitzer Engineering Laboratories, Inc. Time: No-host social at 5:30 PM; Presentation at
6:15 PM; Dinner at 7:15 PM; Presentation continues at 8:00 PM
Cost: dinner is $20 for IEEE members; $25 for non-members
Place: Marie Callender's Restaurant - The Garden Room, 2090 Diamond Blvd, Concord
RSVP: by November 14 to Gregg Boltz, [email protected] or telephone (925) 210-2571
Web: www.e-grid.net/docs/0711-oeb-ias.pdf
Greg Rauch is a Field Sales Engineer with Schweitzer Engineering Laboratories, Inc. He graduated from Brigham Young University with BSEE and Masters of Power Engineering degrees. His professional career includes positions held with General Electric, EPRI, BMI and a consulting research firm. Past assignments include protective relay application engineer, power quality and EMF research project manager, Asia-Pacific regional manager, and international marketing manager. He is a life member of Eta Kappa Nu, Senior Member of IEEE, and California registered professional engineer. On a lighter note, he is an FCC licensed amateur radio operator, callsign N6CK.
Industrial plants with an electric utility interconnection and on-site generation resources include a wide variety of electric loads, ranging from less critical lighting and HVAC, to most critical processes and process controls. When the utility interconnection is compromised, on-site generation is expected to maintain critical loads in order to mitigate economic consequences of loss of finished product, and potentially hazardous environmental impacts. The speed with which the plant system adapts to restricted generation resources is critical to the overall success of maintaining important process loads during a reduction or loss of utility supply.
Protective relays are an absolute necessity in all medium voltage and above power systems. These relays are, therefore, a logical base of electronic devices upon which a power management system can be built. Modern protective relays include all the I/O, programmability, data collection, metering, and power system diagnostics that previously required the integration of RTUs (Remote Terminal Units), PLCs (Programmable Logic Controllers), DFRs (Digital Fault Recorders), transducers, meters, and multiple single-function protective relays.
Modern power management systems are a complete integration of an installed base of protective relays, remote I/O modules, wide area control systems, communications, monitoring, and engineering toolsets. This presentation describes the design of a fully integrated power management system as applied in a large oil refinery.
THURSDAY November 15OEB Industry Applications
MET Laboratories
EMC – Product Safety
US & Canada
• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)
Facilities in Union City and Santa Clara
www.metlabs.com [email protected] 510-489-6300
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First Steps Towards Community Robotics
Speaker: Prof. Illah R. Nourbakhsh, The Robotics
Institute, Carnegie Mellon University Time: 6:30 PM Cost: none Place: Carnegie Mellon University West Coast,
Moffet Field, Mountain View RSVP: not required Web: ewh.ieee.org/r6/scv/ras
Illah R. Nourbakhsh is an Associate Professor of
Robotics and head of the Robotics Masters Program in The Robotics Institute at Carnegie Mellon University. He was on leave for the 2004 calendar year and was at NASA/Ames Research Center serving as Robotics Group lead. He received his Ph.D. in computer science from Stanford University in 1996. He is co-founder of the Toy Robots Initiative at The Robotics Institute, director of the Center for Innovative Robotics and director of the Community Robotics, Education and Technology Empowerment (CREATE) lab. He is also co-PI of the Global Connection Project, home of the Gigapan project. He is also co-PI of the Robot 250 city-wide art+robotics fusion program in Pittsburgh. His current research projects include educational and social robotics and community robotics. His past research has included protein structure prediction under the GENOME project, software reuse, interleaving planning and execution and planning and scheduling algorithms, as well as mobile robot navigation. At the Jet Propulsion Laboratory he was a member of the New Millennium Rapid Prototyping Team for the design of autonomous spacecraft. He is a founder and chief scientist of Blue Pumpkin Software, Inc., which was acquired by Witness Systems, Inc. Illah recently co-authored the MIT Press textbook, Introduction to Autonomous Mobile Robots.
The CREATE lab and the Global Connection Project have embarked on a series of public projects to try to understand how significant scaling may be feasible using robotics for technology empowerment and community-building. Our work is now hybridizing the Global Connection efforts together with our more traditional Telepresence Robot Kit and CMUcam educational tools, and we are carrying out experiments locally in Pittsburgh and internationally in collaboration with UNESCO. I will describe the current status of our community products, describing both our target communities spanning the cognitive pipeline, and the new technologies we are releasing this year – CMUcam3, a fully programmable, public-domain embedded computer vision system; TeRK, a single-box solution for complete I/O control of robots together with a Linux OS and connectivity to the iRobot Create and other robots; Canary, a new embedded environmental sensor and kinetic art controller; and Gigapan, a multi-billion pixel panoramic image capture, display and annotation system. I will end by describing the beginning of our unified effort at large-scale public, activist robotic art across Pittsburgh, called Robot 250, which is funded by a group of five corporations and foundations. The Global Connection Project is hosted by Carnegie Mellon West (Moffett Field, CA) and Carnegie Mellon Robotics Institute (Pittsburgh, PA).
MONDAY November 19SCV Robotics and Automation
VOICE COIL MOTORS Design - Control - Fabricate - Test
J. Arthur Wagner, Ph.D. 1649 Fair Orchard Ave.
San Jose, CA 95125
[email protected] (408) 269-7044 (408) 206-3049 cell
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China's IC Design Industry Status Today
Speaker: Bob Pau, Cadence Design Systems Time: Fast food & drinks at 6:30 PM; Presentation
at 7:00 PM Cost: none Place: Cadence Design Systems, Building 5, 655
Seely Avenue, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/cas
Bob Pau is a Methodology Architect working in Cadence for six plus years now, focused on RF/AMS SOC design. He worked in China for a year in 2005 to support China’s IC design houses, then traveled back to China every quarter since 2006. Before he joined Cadence, he spent 14 years in the semiconductor industry in various design, product definition, consulting, application, sales, and marketing roles at leading companies such as Motorola, Harris, Zilog, Infineon, NEC and National. He holds a First Class Engineering degree in RF Communications from University of Bradford, UK. He is a senior member of IEEE, a reviewer for Trans.MTT and a founding member for CAS Santa Clara Valley Chapter.
The world has been flattened due to out-sourcing and off-shoring. China has already become the largest importer for electronic components now. Of the $247 billion high-tech imports in China in 2006, $130 billion were electronic components and equipment. (China statistics in 2007, reported by MOST.) China is also entering the second year of their 11th 5-year plan. New government policy and financial aid have come out to support the electronics eco-system and several industrialization efforts in some application markets. The electronic design business is heating up in China as domestic companies emerge to take advantage of new Chinese-made standards. Some domestic companies also went public on the NASDAQ, such as ViMicro, Action and Spreadtrum. Chinese domestic IC design houses will continue to strengthen their design capabilities in order to reduce reliance on imported components. Buying from domestic IC houses will help domestic OEMs to reinforce their competitive positions.
In this talk, we will answer many questions raised by you and tackle issues including:
• What is the current status of the IC industry in China?
• What is current china government policy? • What is the strategy for 11-th 5 years plan? • Who are top players now in China? • What are they doing to take advantage of strong
demand? • Who will be the Chinese equivalent Samsung or
Broadcom in the future? • What are hot products in China for IC design? • What is the trend in China on electronic design? • What are the challenges that China’s design
houses are facing? • How can the IC design industry improve its design
capabilities? • Where to set up your own R&D center? • What you can do in Silicon Valley to catch those
opportunities, what role will you play?
No slides will be posted for this talk. You have to attend to learn the news.
MONDAY November 19SCV Circuits and Systems
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High Magnetic Anisotropy Materials: From Bulk through
Multilayers to Nano-scaled Particles
Speaker: Prof. Takao Suzuki, Toyota Technological
Institute, & IEEE 2007 Magnetics Society Distinguished Lecturer
Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM
Cost: none Place: WDC (formerly Komag), 1710 Automation
Parkway, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag
Takao Suzuki received the B.S. and M.S. from Waseda University, Tokyo, in 1962 and 1964, respectively, and the Ph.D. from California Institute of Technology in 1969. He was a postdoctoral fellow at Max-Planck Institute in Stuttgart from 1969 through 1972, and was an associate professor at Tohoku University from 1972 through 1988, where his research interests included magnetic multilayers with high magnetic anisotropy for magneto-optical recording, and magnetic recording applications.
From 1988 through 1995 he worked as a research staff member at IBM Almaden Research Center in San Jose, and was involved with high density magneto-optical and magnetic recording materials developments. In 1995 he joined Toyota Technological Institute in Nagoya, Japan, as a principal professor. Dr. Suzuki is now a vice president and a principal professor of the Institute, and also director of the Academic Frontier Center sponsored by the Japanese Ministry of Education, Science, Sports and Culture. His current research interests include the magnetic anisotropy and structure of ordered alloy thin films and nanoparticles, and high density perpendicular magnetic recording media applications. He has published more than 260 scientific papers, has written four books, and has 17 patents.
Professor Suzuki is Fellow of the IEEE. He has been active in many Intermag and Magnetism and Magnetic Materials conferences, including serving as program co-chair of MMM in 1995, and as treasurer co-chair of Intermag in 2005. He has served as a member of the Administrative Committee of the IEEE Magnetics Society for several terms. He is on the Editorial Board of IEEE TRANSACTIONS ON MAGNETICS and is an advisory editor of the Journal of Magnetism and Magnetic Materials.
Magnetic anisotropy is one of the basic properties of magnetic substances. In particular, magneto-crystalline anisotropy is thought to be intrinsic for bulk materials, but the theoretical understanding is not satisfactory, as is often demonstrated. In multilayers and nanoparticles where surface or interfacial magnetic anisotropy plays a key role, magnetic behavior is significantly influenced by extrinsic or induced magnetic anisotropy. Among many alloy systems, ordered alloys are known to exhibit high magnetic anisotropy; in particular the L10 ordered phase is of great interest because of applications in bit-patterned magnetic data storage. Nanocomposite particles with a high magnetic anisotropy phase, together with other magnetic anisotropies, are the subject of intensive research since they offer potential for various applications such as hybrid data storage, sensors, and bio-devices.
This tutorial lecture addresses the magnetism and structure of thin films and nanocomposite particles with a high magnetic anisotropy ordered phase. An in-depth review of magnetic anisotropy in rep resentative materials is given. Recent developments in high magnetic anisotropy of novel
materials, multilayers, and nanocomposites will be presented. Emphasis is placed on quasi-L12 structured alloy films with very high magnetic anisotropy and on FePt/FeRh nanocomposites of the first-order transition type, in conjunction with possible applications.
WEDNESDAY November 21SCV Magnetics
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Digital Paralleling & System Design: System Topologies,
Design Considerations Speaker: George L. Williams, Cummins Power
Generation Time: Social at 5:30 PM, Presentation at 6:00 PM,
Dinner at 7:00 PM Cost: $20 Place: Sinbad’s Restaurant, Pier 2 The
Embarcadero, San Francisco RSVP: To qualify for drawing, preregister with Jack
Lin, [email protected], 415.551.4894 Web: www.e-grid.net/docs/0711-sf-ias.pdf
Our speaker is George L. Williams, an Associate
Member of the IEEE Power Engineering Society. His 25 years experience in various phases of the power industry includes acting as a trainer for paralleling systems at ASCO Emerson Network Power, and at the Engine Generators Systems Association (EGSA). He also has 13 years at Emerson Network Power / ASCO through various jobs as an application engineer, project manager, marketing manager. He spent 2 Years with GE Zenith as Western Regional Sales Manager. He started with Cummins Power Generation April, 2004 as Western Regional Sales Manager for Power Electronics. George has a BA in Management from St. Mary’s College in Moraga California, 1999, an Associate Of Business North Arkansas Community College, 1979, On-the-Job Training Electrical Power Training AP&L, Alltel, ASCO, and Cummins Power Generation.
Our speaker will review paralleling basics for
gensets, such as, but not limited to, load sharing, synchronization, and genset protection issues. He will then compare the conventional hardware requirements for paralleling with digital control alternatives that include discussion of master control functions. Finally, our speaker will conclude his presentation by describing various system topologies and design considerations, more notably with respect to switchgear vs. switchboards.
Please join us in welcoming our speaker to San Francisco for what is sure to be an interesting and productive session.
TUESDAY November 27SF Industry Applications
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Selection and Applications of Power Factor Correction
Equipment for Industrial and Large Commercial Facilities
Speaker: B. Ben Banerjee, Power Quality Product &
Application Engineer, Square D Company Time: Presentation at 6:00 PM, with snacks and
refreshments Cost: none Place: Square D Company 6160 Stoneridge Mall
Road #200, Pleasanton RSVP: with Diep Nguyen, [email protected], 510-
267-0441 Web: www.e-grid.net/docs/0711-oeb-pes.pdf
B. Ben Banerjee (IEEE M’ 72) holds B.E.E degree
from the University of Calcutta, India and M.E.E degree from the University of South Carolina, Columbia, SC. Presently, he is working as Power Quality Product & Application Engineer in PQ Solution Group of Square D Company, San Francisco Field Office. Prior to that, he worked for 17 years, as a Power Conditioning & Advanced Motor-Drives Manager, in the Power Quality Business Group of Electric Power Research Institute (EPRI), Palo Alto, where he was responsible for technology and application development for power quality mitigation hardware system, advanced energy storage for power quality solutions, and advanced motors and drives system for end-user sectors. Prior to joining EPRI, he was Order Engineering Manager for Square D Company, Columbia, SC. In this position, he was responsible for the design and applications of products such as LV and MV MCCs, motor controllers for material handling, & VFDs. He has participated in NEMA Standards Subcommittees, organized EPRI-sponsored National motors & Drives Steering Committee, and is author/ co-author of several IEEE technical papers. His R& D work at EPRI has generated more than thirty patents for EPRI and about eighty EPRI technical reports.
The vast majority of the total load connected to today’s industrial and commercial distribution systems is inductive in nature and generally has a poor operating power factor. If properly selected and installed, Power Factor Correction Equipment including Capacitors (PFCCs) provides an economical and practical means for improving the system power factor.
PFCCs reduce energy costs, increase electric system capacity, and raise voltage levels intentionally, and can reduce power distribution system losses.
This presentation will focus on the applications of shunt capacitor and will cover topics such as power factor fundamentals including displacement and total power factors, selection and sizing of power factor correction capacitor, cost benefits and utility rate structures. It will also discuss other related application issues like proper location of capacitor in the facility distribution system, effects of harmonics, fixed vs. automatic banks, selection of circuit protection and isolation devices, applicable standards and codes, various considerations for capacitor banks connected at MCC or at motor terminals, PF impact by distributed generation, PF correction benefits using harmonic filters, and certain aspects of storage, maintenance, and installation of the power factor correction equipment.
THURSDAY November 29OEB Power Engineering
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"TV 2.0" - Digital TV in the Networked Home
Speaker: Paolo Siccardo, President, Digital Keystone Time: Refreshments at 6:30 PM; Presentation at
7:00 PM Cost: $5 for IEEE members, and $10 for non-
members Place: Hewlett Packard Oak Room, 19447
Pruneridge Avenue (Building 48), Cupertino RSVP: not required Web: ewh.ieee.org/r6/scv/ce
Paolo Siccardo is the President and Chief Executive Officer of Digital Keystone, a world leader in digital entertainment solutions that bridge the personal computer, consumer electronics and content industries. Paolo Siccardo has over 20 years of experience in General Management and Business Development of high technology products. Prior to the inception of Digital Keystone, Paolo Siccardo was Executive Vice President and General Manager of Digital Television products with SCM Microsystems, a leading OEM supplier of security technology. Previously Paolo Siccardo held positions as Senior Vice President of Marketing and Business Development with SunUp, a leader in content management software for the satellite and cable-TV industry; Vice President of Engineering and then General Manager with Hyundai Electronics, where he launched the world's first Open TV Set Top Box; and Project Manager at Hewlett-Packard, where he managed the development of the world's first Video on Demand Server. With Compression Labs, Paolo Siccardo developed the world's first AT&T videophone and PC video conferencing product. Paolo Siccardo holds a MSEE degree from the University of Genoa, Italy. Several U.S and International patents have been awarded or are pending in his name.
TUESDAY December 4SCV Consumer Electronics
N o v e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 26
Electrical Out-of-Step Protection
Speaker: Demetrios Tziouvaras, Schweitzer
Engineering Laboratories, Inc. Time: Noon (includes lunch) Cost: free for IEEE members;
$5 for non-members Place: Pacific Gas & Electric Office, 245 Market
St., Conference Room 1411, San Francisco RSVP: by Dec. 6th (first 25 people only) to Davis
Erwin, [email protected], 415-973-6010 Web: www.e-grid.net/docs/0712-sf-pes.pdf
Demetrios Tziouvaras is a Senior member of IEEE, a member of the Power System Relaying Committee (PSRC), and a member of CIGRE. He is a Senior Research Engineer with Schweitzer Engineering Laboratories, Inc. (SEL). Prior to joining SEL in 1998, he was a Principal Protection Engineer for Pacific Gas and Electric Company, where he spent 18 years in power system protection and was an important contributor to protection designs that are still in use today.
Demetrios authored more than 35 IEEE and protective relay conference papers and holds three patents in the area of power system protection, with several patents pending. He served as chairman of a PSRC working group that developed an IEEE PES tutorial on “EMTP Applications to Power System Protection” and as vice-chair of a PSRC working group that developed a report on “Power Swing and Out-of-Step Considerations on Transmission Lines.” Currently, Demetrios is the convenor of CIGRE WG B5.15 on “Modern Distance Protection Functions and Applications” and a member of several IEEE PSRC and CIGRE working groups.
Demetrios has taught numerous seminars in digital relaying, protective relaying, and EMTP at the University of Illinois at Urbana-Champaign, the California Polytechnic Institute in San Luis Obispo, IEEE PES, and SEL University.
Alternating current (AC) electrical networks can experience loss of synchronism (out-of-step, OOS) during stressed power system conditions. During an OOS event, large current and voltage excursions develop across the electrical connection between two diverging grid sections. Proper detection of the OOS condition and separation of asynchronous system areas to avoid widespread outages and a potential collapse of the entire electrical grid is imperative. Come to this IEEE SF PES technical presentation to learn conditions that cause electrical OOS and where the grid is most susceptible. Learn how quickly an OOS condition can develop and what existing and future technology is being deployed to detect the OOS phenomenon and mitigate its effects.
THURSDAY December 13SF Power Engineering
