New Insights on Multiphase Synchronous Buck Converter Design: A Comprehensive Consideration

Kejiu Zhang, Shiguo Luo, Lisa Li Enterprise Power Engineering

Dell Inc. Round Rock, TX, U.S.A.

Thomas X. Wu, Issa Batarseh Department of Electrical Engineering and Computer

Science, University of Central Florida,

Orlando, FL, U.S.A

Abstract—This paper comprehensively discusses the

multiphase power converter design and introduces new control schemes in dynamic operations, which are now used to supply the power for modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC). With the aggressive motivation to boost dynamic power efficiency, the design specification of the VR is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and PWM drive interface to achieve phase shedding are first illustrated. Robust driver operation is ensured when exiting the tri-state for long time. Nonlinear control scheme is introduce to minimize the voltage excursion during load transient. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. For experimental verification, a 400 W six phase synchronous buck converter is implemented with the proposed schemes.

Keywords—multiphase; efficiency; transient performance; dynamic VID

I. INTRODUCTION Minimizing power conversion consumption and

maximizing power system reliability in information handling systems has become a critical design consideration [1]-[3]. The multiphase synchronous buck converter is the most popular topology for low voltage and high current DC-DC conversion. Previously, there was a strong emphasis on high efficiency for the mid to high load utilization. Right now industry environmental regulations, such as Energy Star, also specify IDLE power requirements for the platform. Fig. 1 shows the architecture of the multiphase synchronous buck converter which can be working in the bidirectional fashion. Each phase is interleaved by 360/NPHASE to achieve optimal ripple cancellation. In the controller section, the main sub-circuit modules are illustrated. Current ADC module samples and digitizes each phase current, which is the voltage across the cap of inductor DCR the sense network, in the real time manner. Voltage ADCs sense and digitize both the VOUT and VBUS, and the digitized VBUS acts as feed-forward term in the control loop. Adaptive voltage positioning (AVP) module decodes the VID command and generates the reference based the digitized total phase current information with DVID

compensation. Digital compensator filters the error voltage generated by ADC output and AVP blocks and feeds into the DPWM generator block. Current balance module, which is designed as 1/5 of the voltage loop, and Nonlinear PWM generator both modifies DPWM patterns in different fashions. The control outputs of DPWM generators are the PWM and driver enable (DR_EN) signals. In each phase of the multiphase synchronous buck converter, two power MOSFETs are used—a control (HS) field effect transistor (FET) Q1 and a synchronous (LS) FET Q2. A pulse-width modulation (PWM) control IC alternately switches the two MOSFETs Q1 and Q2.

Fig. 1. The architecture of the bidirectional multiphase synchronous

converter.

Dead time tdead−time [9], during which both power MOSFETs (Q1 and Q2) are off, is inserted between the gate

Partially funded through the Florida Energy Systems Consortium (FESC) Program. 978-1-4799-0224-8/13/$31.00 ©2013 IEEE 2447

signal cycle to avoid cross-conduction and guarantee safe operation of the circuitry. There is another dead time which is very critical in the driver IC design for the DVID operation, i.e. watch-dog timer twatch-dog, which is defined as from HS gate signal is low and switch node is still high, after this defined time length, the LS MOSFET is turning on. The detailed analysis of system impact by twatch-dog is in Section II. Moreover, there is always a design trade-off between DVID transition and transient response requirement in the VR design perspective, i.e. to populate the right number of output bulk capacitors. In previous literatures[4], [12], the analysis was only based on the average model. Operation mode, driver dead-times and component stress were not addressed due to the slower slew rate of voltage transition. Objectives of this paper are to present a comprehensive, practical and robust realization of multiphase buck converter design with improved efficiency for the whole load range and optimal responsiveness of the system dynamics.

The rest of the paper is organized as follows.

i) Section II introduces the operation modes, PWM interface definition in the phase shedding control and boost mode operation

ii) Section III presents the in-depth loss analysis and the procedure to achieve optimum static efficiency for the whole load range.

iii) Section IV presents the nonlinear control schemes to improve the transient performance

iv) Nonlinear control schemes and droop (C dV/dt) compensation for DVID transition are presented in section V.

Conclusion is drawn in Section VI.

II. DRIVER OPEREATION

A. HiZ Management The definition of driver parameters and the interface with

PWM controller are the keys to achieve optimal efficiency in the multiphase converter design.

One phase of the multiphase synchronous buck converter with the dead-times control and HiZ management is shown in Fig. 2. The polarity of the output inductor current (iL) is defined as positive when flowing away from the phase node, and defined as negative when sinking towards the phase node. The bootstrap switch between the PVCC and BOOT pins is embedded inside of the driver IC for saving the use of external diodes, reducing the leakage and boosting the efficiency. Anti shoot-through management, monitoring the signals before level shift circuitry, avoids high-side and low-side MOSFET to conduct simultaneously and, combined with Adaptive Dead-Time control, minimizes the LS body diode conduction time. DR_EN toggle is an important feature in the modern driver design because the fast Hi-Z operation can be achieved.

Fig. 2. Driver IC block diagram with power stage.

PWM and DR_EN are both control input signals for driver IC which are generated by the state machine of PWM controller. Fig. 3 shows the timing diagram of driver interface with HiZ management. HiZ is the high-impedance stage by keeping all MOSFETs in off state. HiZ window is defined as voltage range of the PWM between 1.2 V and 2.2 V for a 3.3 V application. t1 and t3 represent propagation delay of LS Gate and HS Gate, respectively. t2 and t4 represent dead times from LS falling and HS falling, respectively. t5 and t8 both represent hold-off times. t6 and t7 represent propagation delay of DR_EN rising and falling.

(a)

(b)

Fig. 3. Timing diagram of driver interface: (a) DR_EN is asserted; (b) DR_EN is toggling during operation.

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(a) (b) (c)

Fig. 4. Operational waveforms with the critical dead times: (a) Buck (Source) CCM; (b) Buck (Source) PFM; (c) Boost (Sink) Mode.

When CPU is in idle state, it is normally the condition of load current less than half of the inductor current ripple. The VR should be operating in PFM to reduce power loss.

For the simplicity, the MOSFETs are assumed to be ON immediately when the gate voltages (VGS) reach the gate threshold value (VGS(th)), and OFF immediately when the gate voltages are zero. The propagation delay from PWM to gate voltage is not marked for the simplicity as well.

As shown in Fig. 4(a), the yellow rectangles represent the dead time, tdead−time. The voltage on phase node becomes negative diode voltage drop (can be Schottky barrier diode) after the LS MOSFET is OFF. The positive inductor current will discharge COSS from VBUS to ground very quickly once the upper MOSFET is turned OFF. Therefore the voltage of the phase node is again clamped by the low side body diode as soon as the upper MOSFET is OFF and the values is minus forward diode drop.

In PFM, as shown in Fig. 4(b), PWM transitions from HiZ to high. Phase node moves from output voltage level to VBUS. To achieve fast HiZ operation as depicted in Fig. 3(b), EN toggle should be utilized in PFM operation. When the inductor current reaches zero, the LS is turning off. The output voltage then decays as a function of load. Power MOSFETs remain HiZ until the output voltage drop below the regulation target to trigger a PWM on pulse.

Under the boost mode, as shown in Fig. 4(c), the phase node voltage is clamped to VBUS plus a diode forward voltage drop after the HS MOSFET is OFF. The red rectangle represents twatch-dog. LS MOSFET is hard switching after twatch-

dog. After LS MOSFET turns on, the current in the HS body diode commutates to the LS, going through the reverse recovery phase.

B. Driver Design Details to Achieve Robust Operation There is no issue when VBOOT-SW is above 3.8 V, which

presents the most operating conditions. With lowering down PVCC and increased VOUT, there is a case that driver can create a GH/GL overlap (shoot-through) scenario if the driver dead-time design is fairly aggressive. When the dropped phase

stays in tri-state in long period of time, the boot capacitor is discharged by the gate driver leakage current (leakage rate: 1 nA/s), and eventually VBOOT-SW is clamped depending on equation (1):

OUTSDSWBOOT VVPVCCV −−=− (1)

where PVCC is the FET drive voltage. VSD is the diode voltage drop across the internal switch.

The level shift circuit, as shown in Fig. 2, takes the GND referenced signals and level shift them to the HDRV “isolated” circuitry (level shift output) which is referenced to SW node and powered from BOOT-SW capacitor voltage. The HS gate falling edge propagation delay gets larger relative to LS rising edge delay. This BOOT-SW bleed depends on variables such as VOUT and length on time in tri-state among other variables. The HS falling prop delay increase occurs regardless of PVCC voltage and can create a GH/GL overlap until BOOT capacitor charges back up from the 2nd LS pulse.

As shown in Fig. 5(a), the red circle highlights the gates overlap when existing long PWM tri-state. The overlap is around 10 nS. There are several methods to eliminate the overlap, as shown in Fig. 5(b) and (c). In Fig. 5(b), the PWM generate by the controller should go to LOW first, which can charge up the voltage on BOOT capacitor, thus can shorten the propagation delay and eliminate the shoot-through. In Fig. 5(c), the anti-shoot protection unit directly monitors HG and LG, which can adaptively prevent the gate overlap phenomenon in this specific scenario.

The avalanche breakdown energy of the power stage devices, from the worst case aspect, is 50 mJ by Cadence Virtuoso Analog Design Environment simulation. The energy during the gate overlap event is under 100 µJ, 1/500th the energy necessary for breakdown. However, from the system robustness point of view, the gate overlap should be prohibited.

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(a)

(b)

(c)

Fig. 5. Operational waveforms of existing long tri-state: (a) around 10 nS of shoot-through; (b) No shoot-through captured by PWM going low first when exiting tri-state. (c) No shoot-through captured with “adaptive” shoot-though protection. Channel 1: Switch node, 5V/div; Channel 2: PWM, 2V/div; Channel 3, LS gate-source, 2V/div; Channel 4: HS gate to source, 2V/div. Time scale is 50 nS/div.

III. DESIGN PROCEDURE FOR OPTIMIZING STATIC EFFICIENCY

To obtain the optimum static efficiency for the whole load range, not only the higher figure of merit (FOM) of power MOSFETs should be employed, the driver capability and the

parameters associated with the power loss should be carefully studied and optimally selected. Finally, phase shedding control needs to be implemented to improve the efficiency in mid-light load, and the control thresholds are the intersection points of adjacent phases in efficiency plot.

TABLE I. DIVER DEFINTION

Upper driver source/sink current 2A / 2A Upper driver source/sink impedance Lower driver source/sink current Lower driver source/sink impedance tdeadtime(f)

0.8 Ohm / 0.6 Ohm 2A / 4A

0.8 Ohm / 0.35 Ohm 8 nS

tdeadtime(r) 15 nS

It’s very important to define and strengthen the driving capability of the power MOSFETs driver to minimize the HS switching loss during commutation. TABLE I shows the definition of driving capability and dead times.

Power loss calculation [7]-[8] and experiment verification should be both carried out with varying switching frequency and PVCC( MOSFET drive voltage). The following equations shows power loss portion when the converter is operating in synchronous buck mode.

The conduction loss is the resistive loss due to current conducted through the channel resistance Rds_ON.

ONdsRMSCOND RIP _2 ×= (2)

Where ( )DI

NII rippleout

LSRMS −

−= 1

12

2

2

2

)( (3)

DI

NII rippleout

HSRMS

+=

12

2

2

2

)( (4)

PCOSS is the power loss due to the output capacitance of MOSFET

SWBUSOSSCOSS fVQP ×××= 5.0 (5)

Pdeadtime represents the body diode conduction loss during tdeadtime.

sw

fdeadtimeripple

OUT

rdeadtimeripple

OUT

SDdeadtime ft

II

tI

IVP ×

++

×

−

×=

)(

)(

2

2 (6)

where VSD is diode forward voltage drop; tdeadtime(r) represents rising edge dead-time between LS turn off and HS turn on; tdeadtime(f) represents rising edge dead-time between HS turn off and LS turn on.

PQRR, the diode reverse-recovery loss, is generated due to the turn off of the LS FET body diode.

SWBUSLSRRQRR fVQP )(= (7)

where QRR is the excess minority carrier charge in the reverse recovery transient.

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Fig. 6. Measured efficiency of multiphase buck converter with operating different number of phases.

In the buck mode operation, the LS MOSFET is considered as soft switching. The HS MOSFET turn on/off loss incorporating common source inductance due to device package can be accurately calculated by:

( ) ( ) ( )

( )( )

××

−×

++++−

×+

−×++

−×

×

−××=

2)(

)(

)(_22

)()(

)(

)(2)(

)(_

)(2

)(

2

4

5.0

2

5.0

2

HSgd

LSOSScis

HSPLDRFETHSgd

LSOSScisdriverHSgdriverHSg

HSgd

HSgs

rippleOUT

csidriverHSg

HSPLDRFET

HSgs

rippleOUTSWBUSONSW

QQL

VVQ

QLRRRR

QQ

II

LRR

VVQ

IIfVP

(8)

( ) ( ) ( )

××

×++++−

×+

+×++

×

×

+××=

2)(

)(

)(2)(

)(2)()(

)(

)(2)(

)(

)(2

)(

2

4

5.0

2

5.0

2

HSgd

LSOSScis

HSPLHSgd

LSOSScisdriverHSgdriverHSg

HSgd

HSgs

rippleOUT

csidriverHSg

HSPL

HSgs

rippleOUTSWBUSOFFSW

QQL

VQ

QLRRRR

QQ

II

LRR

VQ

IIfVP

(9)

where IOUT, VBUS, VFET_DR, Rg, VPL, Rdriver, Lcis, Qds and Qgd are the output current, Bus voltage, gate drive voltage, gate drive resistance, HS MOSFET plateau voltage, HS common source inductance, current, HS FET Qds and HS FET Qgd, respectively.

The gate charge induced loss:

( ) SWDRFETLSgHSggate fVQQP ××+= _)()( (10)

The switching frequency and VFET_DR should be optimally selected based on the minimum power loss.

It is critical to optimize the static efficiency of power stage first since it is one of the key performance metrics of the VR design. Fig. 6 shows the measured efficiency plot of multiphase buck converter with statically configured operation modes and different number of phases. There are in total seven cases in this plot: one phase PFM and one to six phase CCM. Light load operation, which is less than 10% of utilization, is highlighted in greed. Converter parameters for the efficiency plot are in TABLE II, except for the disabled LL. VOUT is regulating at 1.05 V and measured at the output inductor. A GPIB based automated efficiency program, which communicates to the data acquisition unit (Agilent 3497A) and electric load (Sorensen).is written to record, VBUS, IBUS, VOUT, IOUT, VFET_DR, IFET_DR and plot the efficiency curve. The cross points between adjacent phases operation can be programmed into the non-volatile memory (NVM) for this specific power stage for auto phasing shedding purpose to maximize the efficiency over the whole load range.

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TABLE II. THE CONVERTER PARAMETERS

VBUS 12 V VO 0.7 V~1.2 V

VFET_DRV 6.0 V fSW

Loadline slope 385 kHz 0.8 mΩ

Output inductor per phase L = 230 nH Output capacitor 6×470 µF Panasonic SP-Caps

44×22 µF MLCC

IV. TRANSIENT PERFORMANCE ENHANCEMENT The equation set in represents all operation scenarios or

inductor current slopes in the converter. Equation (11) represents the charging slope when converter is operating is the boost (sink) mode with body diode of HS conducting. Equation (12) represents the charging slope when converter is working is the buck mode. Equation (13) represents the discharging (freewheeling) slope when LS is in asynchronous operation and body diode conducts (body braking). Equation (14) represents the discharging slope when LS is turned on.

( )

( )

( )

( )

( )

−

−−

−

+−

=

14)(

13)(

12)(

11)(

LtV

LVtV

LtVV

LVtVV

tiL

OUT

SDOUT

OUTIN

SDOUTIN

slew

Fig. 7. Inductor current profile and gate-drive signals of synchronous and

asynchronous operations.

A. Nonlinear Control Scheme Transient performance is one of the most performance

metrics for evaluating the multiphase converter. Traditional voltage mode based buck converter is the most widely used topology in the power industry. It is a clock based converter and the VR needs to wait the entire switching cycle to issue the next PWM on pulse no matter when the transient event occurs.

Output voltage deviations or excursions that exceed the pre-defined window thresholds are treated as load transient event [20] and a fast correction signal must be applied accordingly. The fast nonlinear loop includes a programmable multi-threshold window comparator, pulse generation circuitry and interfacing circuitry to the normal PWM. When the sensed voltage is out of the programmable window, the ATR asynchronously signals the modified PWM patterns for compensating the output voltage. There are basically two types of asynchronous response, i.e. Active Load Release Response (ALRR) and Active Load Engage Response (ALER). The nonlinear response essentially extends effective regulation bandwidth while maintain constant output impedance over frequency. The red rectangles represent the time slot in each phase that ALRR event can initiate. The orange and blue rectangles represent ALER event can be triggered and they are threshold 1 and threshold 2, respectively. The internal counter module in each phase is synchronous with switching frequency and points where the nonlinear events should be added. For example in load engage event, the asynchronous pulses in each phase boost the switching frequency to MHz range in the transient event, which effectively pumping the inductor current energy to the output capacitance bank. The extra voltage generated by the nonlinear loop:

( )∫∑

+= = dttiLC

V KKOUT

N

KEX θ1 (15)

where iLK(t) represent the inductor ripple generated by the asynchronous pulse in phase K. θK represents the phase angle difference between phase one. N presents the number of the active phases in the DVID operation. For simplicity COUT represent the total capacitance of bulk and ceramic caps.

Fig. 8. The ATR timing architecture of the multiphase controller.

AVP scheme is to maintain constant output impedance so that less output capacitors can be populated and the output power of VR at full load can be reduced. A mathematical model that describes voltage current relationship given system impedance (RLL) is shown in (4). The nominal loadline equation is:

LLLOADetT RIVIDV ×−=arg (16)

Fig. 9 (a) shows a load engage event with nonlinear response enabled. The VOUT stabilizes well within the AVP

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window as cursors indicate. The digital channels represent the PWM signals and phase 3 to 6 fire up once the VOUT trip the dashed line (ALER1) in Fig. 9 (b).

(a)

(b)

Fig. 9. A load engage response of the 6 phase buck converter: (a)Load engage response: 10A-140A, slew rate: 450 A/µS; (b) Programmable voltage multi-threshold. Channel 1,VOUT, 50 mV/div. Channel 2, load current, 2.5 V/div, 20 mV = 1 A. Time scale is 2 µS/div.

Fig. 10. Load release response: (a) Load release response with 3 different schemes. Channel 3, Reference1 (magenta) &2(cyan): VOUT, 50 mV/div. Time scale is 4 µS/div. Channel 4, load current, 2V/div, 20 mV represents 1 A.

Fig. 10 shows various load release response, once the load release transient is detected, the reactions are LS ON, LS & body diode modulating(pulse control), and body diode on (body brake control).

The body brake control is the most effective way to the VOUT overshoot, however, it generates more heat, and therefore, more power consumption, compared to the rest of the schemes. LS & body diode modulating is a compromised scheme. The slope equations of inductor current profile can be found in (11)-(14).

V. DYNAMIC VID OPERATION Dynamic VID operation is widely used to save power

during light load condition [11]-[12]. The AVP loop should be carefully considered in the DVID design. It uses the total inductor current to represent the load current, however, during VID changes, there is amount of phase current, CdV/dt current to charge or discharge the capacitor. The AVP loop creates the lag in DVID upward transition and generates the issue for Alert timing in the sVID bus.

A. Cdv/dt Compensation

Fig. 11. Architecture of DVID module with compensations.

Fig. 11 illustrated the architecture of DVID compensation in both current and voltage aspects. It is very critical for compensating the droop current, the current for charging the output capacitors during dynamic operation and thus catching the timing of DVID upward transition. It is very critical for the VR to drive the Alert line to low, by which the Processor acknowledge the readiness for the voltage transition. The current compensation digitally subtracts the absolute value of the sensed total current, therefore, the AVP effect is removed in the current loop during DVID. The voltage compensation adds a programmable offset, which reshapes the ramp DAC during the initial and final transitions for speeding up and smoothness purposes. During DVID upward transition, the sensed output voltage is actually the voltage across the capacitor plus the ESR voltage generated by Cdv/dt current. There need to be an offset voltage to compensate the sag of the ESR drop at the end of the transition. Fig. 18(a) and (b) show experimental waveforms of fast DVID transition with CdV/dt compensation (Cyan) and without the compensation (Black). Six digital channels in the scope shots represent the six PWM signals of the VR.

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(a)

(b)

Fig. 12. Experimental waveforms of fast DVID transitions with/without C•dV/dt compensation: (a) Fast DVID upward transition; (b) Fast DVID downward transition. Channel 1 (blue): Alert signal of sVID bus, 2.5 V/div; Channel 2 (cyan): VOUT of the regulator with compensation, 100 mV/div; Reference channel (black): VOUT of the regulator without compensation, 100 mV/div. Time scale is 4 µS/div.

The excessive undershoot of output voltage during DVID transition should be prohibited since it can cause the system hang or blue screen in the server systems. As indicated by the asynchronous pulses (digital channels) in the red rectangles, the reshaped ramp pattern adds an voltage offset at both beginning DVID upward and the end of the DVID downward transaction, which ensures to speed up the DVID upward transition and eliminate the undershoot in the downward transition.

Given the total output capacitance CO, the relationship between the sinking/sourcing current and DVID slew rate can be expressed by

dtdVCI OSOURCESINK =/ (17)

Server processors roughly have about 4000 µF of CO in each VR. At 20mV/µS DVID rate: 80 Amps of source or sink current during DVID.

VI. CONCLUSION In this paper, the comprehensive design consideration for

multiphase synchronous buck converter is presented. The major motivation of this paper is to minimize system power conversion loss, strengthen the overall system reliability and improve the responsiveness of the system dynamics. Phase shedding control through driver interface is proposed to optimize the efficiency of whole load range. The system reliability when exiting tri-state is enhanced by improved driver design. The dynamic operation modes of the multiphase converter are fully analyzed and system dynamic impact is improved by optimizing the proposed CdV/dt compensation and nonlinear control scheme. Both simulation and experimental results have verified the effectiveness of the proposed schemes.

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