1

Sinewave Generation Using Bit-StreamsN. D. Patel Member,IEEE and U. K. Madawala Senior Member,IEEE

Dept. of Electrical and Computer Engineering

University of Auckland, Auckland, New Zealand

Email: nd.patel@auckland.ac.nz, u.madawala@auckland.ac.nz

Abstract—A new method for the generation of high qualitysinusoidal signals is presented. Multi-bit binary signals arerepresented using uniformly weighted single bit-streams whichcan then be processed by digital logic. Building blocks useful forthe construction of the sinusoidal generator are also presented.The bit-stream representation has the advantage of having thecharacteristics of a classical PWM signal and hence can be usedto drive high power switching devices with minimal conditioning.The technique is simple and can be easily implemented usingdigital logic on an field programmable gate array (FPGA). Theoperation of a single phase inverter using the proposed techniqueis demonstrated using an Altera StratixTM FPGA and a custombuilt power stage. The complete digital design uses less than200 logic elements (LE). The performance of this technique isquantified using simulations and practical measurements. Prac-tical implementations lead to total harmonic distortion (THD)measures ranging between 0.75% to 4.92%.

Index Terms—PWM generation, bit-streams, inverter, variablefrequency drives

I. INTRODUCTION

OVER the past several decades PWM techniques have

made significant progress, evolving from their analogue

’naturally sampled’ form into ’regular-sampled’ digital form.

Numerous regular-sampled PWM techniques and its deriva-

tives have been proposed and implemented and they offer

different levels of sophistication and performance to suit a

variety of applications. These PWM techniques, which have

been categorized as either on-line or off-line [1] or either

carrier-based or carrier-less techniques [2], have their own

characteristics. The performance of PWM techniques is usu-

ally evaluated on the basis of current harmonics, harmonic

spectrum, maximum modulation index, switching frequency,

efficiency, switching loss and dynamic performance etc [2].

Amongst the techniques that have been reported, regular

sampling (RS), RS opitimal, RS harmonic elimination (HE),

high frequency and space vector are techniques, which can

be represented by simple equations. Thus they can be im-

plemented with relative ease using a simple microprocessor

or a digital-signal-processor, and are popular. In contrast,

however, the implementation of HE and optimized RS is

relatively complex. This is because they are represented by

non-linear equations and as such require complex ROM based

look-up tables. PWM techniques based on hysteresis bands

have also been reported. They are analogue techniques and

This research is supported by the University of Auckland grant 3609583The authors acknowledge STMicroelectronics for providing the semicon-

ductors used in this project and also thank Mr Howard Lu for developing thepower electronic circuits.

their performance is both switching frequency and hysteresis

band (window) dependent [3]. All the above techniques, their

derivatives, characteristics and various implementations have

been well reported in literature [4]–[13]. Therefore they are

not reproduced in this paper but a comprehensive discussion

with comparisons of these techniques can be found in [14]–

[17].

This paper presents a new PWM technique which is effi-

cient and suitable for high quality sinewave generation. The

proposed technique uses a bit-stream based PWM strategy to

generate sinusoidal waveforms with improved harmonic distor-

tion. According to the literature and to the authors knowledge,

a bit-stream based pulse width modulator (PWM) technique is

yet to be reported. The sinusoidal generation by this technique

is achieved with a varying switching frequency, the implemen-

tation of which is unique to the technique. The bit-streams

consist of uniformly weighted bits. These are processed by

digital logic gates. The bit-streams, being binary in nature,

can be interfaced to gate drivers with minimal conditioning.

The nature of the implementation is concurrent or parallel

and hence multiple instances of sinusoidal generators have no

impact on each other. The digital circuits have been simulated

using very high speed integrated circuits hardware description

language (VHDL) within ModelsimTM and synthesized on a

Stratix field programmable gate array (FPGA) using Altera’s

QuartusTM tool chain. The power circuits have been designed

and constructed in-house. Both experimental and simulated

results are presented to show the viability of the proposed

technique.

II. BIT-STREAM CONCEPTS

The bit-stream technique uses a sequence of two uniformly

weighted quanta, +Q and −Q to represent any analogue or

binary signal. A logical value of ’1’ is assigned a +Q while a

logic ’0’ is assigned a −Q. Thus a digital square wave, which

is an alternating stream of logic 1’s and logic 0’s, will encode a

zero value over a collection of several logic transitions. Signal

z in Fig. 1 shows a zero valued signal.

Over a frame of several quanta, the inversion of a few logic

0’s to logic 1’s will result in a positive valued bit-stream

and similarly the inversion of a few logic 1’s to logic 0’s

into a negative valued bit-stream. Signal S in Fig. 1 shows

an arbitrary bit-stream signal. The magnitude of S can be

extracted by comparing S and the zero valued bit-stream on

a bit-by-bit- basis. For example in Fig. 1, a comparison with

z shows that at bit position 2 and 6 positive quanta are being

2

asserted while at positions 9 and 11 negative quanta are being

asserted. At all other positions there are no additional quanta

are being asserted since S is identical to z. If the bit-stream is

operating at a bit-rate of fB then z oscillates at fB/2. Since

most digital circuits require a clock source, z which is the zero

reference signal can be easily derived from this source.

If a frame of N quanta is considered then, a zero valued

bit-stream will have N/2 positive quanta and N/2 negative

quanta. Consider a frame with N = 8. Fig. 1 shows two

frames with N = 8. If only one positive quantum is inverted

then, the instantaneous change is −1/4. If all the positive

quanta are inverted then the magnitude of the bit-stream (over

a frame of 8 bits) is −4/4 = −1. Thus over a frame of 8 bits

the theoretical precision is one part in 8 and using a bi-polar

representation, the range is ±4. Thus, at bit position 8 (over

frame A) the magnitude being encoded by S is +2/4 while

in frame B the encoded magnitude is −1/4.

The bit-stream signal can be very easily split to drive an

H-bridge. If the DC link voltage is VDC then, a logic 1 and

a logic 0 would impress opposite voltages to the load and

consequently the average voltage applied to the load can be

expressed by

VLOAD(kTB) = VDC

∑k

k−N a(i) −∑k

k−N b(i)

N

VLOAD(k) = VDC

AN (k) − BN (k)

N(1)

Here t = kTB , with k = 0, 1, 2, . . .∞ and TB = 1/fB .

As is the standard practice in sampled data systems, kTB is

written in a brief format so that kTB → k. Also, a(i) and

b(i) represent the positive (+Q) and negative (−Q) quantum,

respectively, and AN (k) and BN (k) are the summations, at

time instant k, of positive and negative quanta over the past

N states. In a normalized analysis, Q = 1.

t

-Q +Q -Q+Q -Q

S

Frame A

Frame B

0 0 00 -Q+Q 0 +Q 0 0 0 -Q 0

1 2 3 4 5 6 7 8 9 10 11 12

z

t

+Q

Fig. 1. Bit-stream signal representation

Bit-streams can be used in a variety of applications. The bit-

stream technique is ideally suited in distributed computational

paradigms like fuzzy and artificial neural systems [18]. In

addition, it has also been applied to classical control systems

which involve proportional, integral and derivative operations.

To speed up the production of controllers and to facilitate

debugging and testing, various bit-stream operations have been

modularized. Functional elements required for the generation

of a sinusoidally varying bit-stream are detailed in this paper.

The digital circuits have been simulated using VHDL within

ModelsimTM and synthesized on a Stratix FPGA using Altera’s

0

A

B B

A So

CLK

BR

M11

vs

AccumulateSum andSum

M2

Fig. 2. Digital bit-stream generator

QuartusTM tool chain. The power circuits have been designed

and constructed in-house.

A. Scaled Fractions

If the resolution is 1 part in N where N = 2R and if a 2’s

complement R bit wide register is used to capture the binary

value, then the minimum and maximum values are −2R−1 and

2R−1 − 1 respectively. To make the subsequent explanations

more general in nature, any integer 2R−1 − 1 ≤ A ≤ 2R−1, is

mapped to −1.0 ≤ asR ≤ +1.0. Here, asR is a scaled fraction.

Note that the superscript sR distinguishes the scaled fraction

from an ordinary fraction. The scaled fraction is defined by

asR =A

2R−1(2)

Thus

0.5s87→ 0.5 × 2R−1 = 64

1.0s77→ 64

−0.25s87→ −32

B. Binary to Bit-Stream

The schematic shown in Fig. 2 will convert a multi-bit (2’s

complement) binary word, BR(k) into a bit-stream, So(k).The thick solid lines show the multi-bit (two’s complement)

data paths. The circuit deploys a feedback loop with a Sum

and Accumulate (SAC), block in the forward loop. The input,

BR is summed with a value fed back based on the sign of the

SAC. M1 and M2 are constants dependent on circuit operation.

M1 is a positive value and for a symmetrical operation,

M2 = −M1. Since the SAC functions as an integrator,

the nature of feedback process tries to maintain vs at zero

by accumulating differing proportions of M1 and M2. To

understand its operation assume BR = 0 and the SAC output

is also zero. Hence at every clock edge the sign of the SAC

oscillates (since the SAC changes from 0 to −M1 and back

to 0). The output at So thus is a square wave (the zero valued

signal).

The circuit is clocked such that the output is updated at the

edges of fB . Thus it behaves like a sampled data system with

3

t = kTB where k = 0, 1, 2, . . .∞ and TB = 1/fB . If BR(k)is assumed to be time invariant then in steady state,

limk→∞

[

kBR(k) −

[

M1

i=k∑

i=0

a(i) + M2

i=k∑

i=0

b(i)

]]

= 0 (3)

Recall that a positive bit-stream is produced by the inversion

of negative quanta i.e. the logic 0’s. The a(i) and b(i) terms

correspond to the positive and negative quanta respectively. If

a resolution of one part in N is required, the word width, R,

of the binary input BR must satisfy N ≤ 2R. Considering the

limiting condition, N = 2R, (3) can be written as

BR(k) =M1

∑kk−N a(i) + M2

∑kk−N b(i)

N(4)

Using the nomenclature of (1)

BR(k) =M1AN (k) + M2BN (k)

N(5)

AN (k) = BR(k)N

M1 − M2

− M2

N

M1 − M2

(6)

The value of the output bit-stream can be obtained by taking

the difference DN (k) = AN (k) − BN (k). After normalizing

this difference to ±1, the bit-stream output is defined by

So(k) =DN (k)

N=

AN (k) − BN (k)

N(7)

Since AN (k) + BN (k) = N and using (6) we get

So(k) = Br(k)2

M1 − M2

−M1 + M2

M1 − M2

(8)

0 4 8 12 16

Clock Instant

Br = 7

zero

Br = 4

Br = 3

Br = 2

Fig. 3. Simulated Waveforms for R=4

It should be noted that So(k) is a single bit-stream and

its average value over the past N clocks (or rather quanta)

is approximately equal to BR. If the distribution of quanta

is not uniform then this approximation also holds true but

the representation exhibits greater deviations around the true

average value and hence is noisier. In (8), the first term is a

gain term while the second term is an offset. Suitable values of

TABLE IEXAMPLE BIT-STREAMS

Clock zero BR = 2 BR = 3 BR = 4 BR = 7

BS Q Q Q Q

0 + + 0 0 0 0

1 - - 0 0 0 0

2 + + 0 0 0 0

3 - - 0 + + +

4 + + 0 - 0 0

5 - + + + 0 +

6 + - - 0 0 0

7 - + + 0 + +

8 + + 0 0 0 0

9 - - 0 + 0 1

10 + + 0 - 0 0

11 - - 0 + + +

12 + + 0 0 0 0

13 - + + 0 0 +

14 + - - 0 0 0

15 - + + + + +

M1 and M2 can be calculated depending on requirements. In

this application a gain of unity without any offset is required

and hence M2 = −M1 and for a gain of one, M1 = N/2.

A binary to bit-stream generator, with R = 4, has been

simulated with different values of BR (Br = 2, 3, 4 and

7). The resulting bit-streams have been shown in Fig. 3 and

also tabulated in Table I. With R = 4 the input range is

−2R−1 ≤ Br ≤ +2R−1 − 1 (which is −8 ≤ Br ≤ +7) over

24 clocks. If BR = 0 the bit-stream must have equal numbers

of positive and negative quanta and a perfectly distributed

sequence will result in a sequence +Q,−Q,+Q · · ·. Since

each quanta is generated at the bit rate, fB , this bit-pattern

has an effective switching frequency of fB/2. This zero signal

is used as the reference bit-stream. If BR = +2, then two

negative quanta must be inverted into positive quanta. Note

that a binary value of 2 should produce a bit-stream which

actually encodes +2/2R−1 = 2/8. A comparison with zero

shows that the first inversion takes place over clock instants

5, 6 and 7 and the second one over instants 13, 14 and 15.

These inversions also lead to a change in the instantaneous

switching frequency from fB/2 to fB/3. Column 3, entitled

BS, in Table I is the actual bit-stream while column 4 shows

the results of a comparison with zero. Thus, the instances

where the bit-stream is identical to zero have entries of ’0’

while the positive and negative differences have ’+’ or ’-’

respectively. If Br = 4, (column 6 in Table I) the positive

quanta are inserted at instants 3, 7, 11 and 15 and the resulting

switching frequency is fB/4. If the input is positive full scale

i.e BR = 7, then 7 of the 8 negative quanta are inverted

(column 7 in Table I) and results in a switching frequency of

fB/8. The behaviour with −7 ≤ BR ≤ −1 are similar to the

7 ≥ BR ≥ 1. If BR = −8, the negative full scale, then the

resulting bit-stream is a continuous stream of −Q which has a

switching frequency of 0.0Hz. Thus the switching frequency

of the bit-stream varies from negative full scale to positive

full scale. Its implications will be explored in the following

sections.

4

III. SINUSOIDAL DRIVES

A. Bit-Stream Integration

A double integrator feedback system will be used to con-

struct the sinusoidal generator and hence a brief analysis of

a bit-stream integrator is necessary. The schematic shown in

Fig. 4(a) functions as an integrator. The input bit-stream,

Si(k), is decoded by the multiplexer and feeds either a

+1,−1 or a 0 to a SAC depending on the state of a locally

generated zero signal. Thus a +1 is fed to the SAC only if

a positive quantum is being asserted by Si(k) with respect

to zero. The SAC by its very nature acts like a discrete time,

digital integrator. The SACs multi-bit output is converted back

into a bit-stream, So(k). For the purpose of this analysis, Si(k)will be interpreted as a stream of regularly spaced quanta with

a rate proportional to the multi-bit value which it represents.

Thus, if Si(k) represents a multi-bit value, BR, then there are

BR quanta in frame which is N bits long. Hence Si(k) is

actually a signal which is asserting BR

Nquanta per frame. In

units of quanta per sec this is equivalent to BR

TBN= BR

fB

N

where fB is the bit-rate of the bit-stream signal.

If the input to a continuous time integrator, I(s) = KI/s is

a constant (DC) input, Vi(t) = V , then dVo

dt= KIV . This

relationship will be used to the characterize the bit-stream

integrator. Assume that the integrator is initialized to zero at

t = 0. If the input Si(k) represents a constant value BR then,

after t = kTB seconds, where k = 0, 1, 2, . . .∞, the SAC will

have accumulated BRfB

N× t quanta. Thus

∆So(k2) = So(k2) − So(k1) = BR

fB

N(k2 − k1)TB = ∆t

∆So(k)

∆t= BR

fB

N(9)

Thus the transfer function of the bit-stream integrator

IBS(s), in continuous time equivalence is given by

IBS(s) =fB

NI(s) =

KI

s(10)

The integrator has been experimentally characterized using

standard time domain measurements. With R = 8 (i.e.

N = 28 = 256) and fB = 512kHz the frequency response

is shown in Fig. 4(b). At lower frequencies, the response is

in good agreement with theoretical expectations. At higher

frequencies, small offsets at the input together with a poor

signal to noise ratio makes the measurement of the open loop

frequency response of an integrator difficult leading to larger

errors. However, simulations with sine and square wave inputs

have accurately verified (10) over a much larger range of

frequencies but these results have been excluded for brevity.

B. PWM and harmonics

Since a switching method is used to produce the required

time varying signal, harmonics will be produced. The power

in the harmonics is usually quantified by the total harmonic

distortion (THD), which quantifies the power in the harmonics

as a proportion of the power in the required signal. It is defined

by

THD =

∑n=∞

n=2Pn

P1

(11)

So

Binary toBit-StreamConvertor

-1

0

+1

Sum andAccumulate

A

B

Si

CLK

(a) Schematic

102

103

104

−20

−15

−10

−5

0

5

10

15

20

frequency, r/s

Gain

, dB

Theoretical Response

(b) Measured Frequency Response

Fig. 4. Bit-Stream Integrator

Here P1, P2, P3 . . . Pn are the powers of the fundamental,

the second, the third harmonics and so on. Usually, the com-

putation of (11) is restricted to a narrower band of pertinent

frequencies or more accurately over a limited number of

harmonics. In this study, an alternative metric which takes

the ratio of powers of all the components (above a specified

threshold) within a band of frequencies to the power of the

fundamental will also used.

C. Sinusoidal Generator

Fig. 5(a) shows a conceptual schematic of the proposed si-

nusoidal generator. The boxed section identifies the bit-stream

sinusoidal generator which will be implemented on an FPGA.

In principle it consists of two cascaded bit-stream integrators

in a negative feedback loop. This system is critically stable

since the phase margin is zero and consequently the closed

loop system will oscillate at the crossover frequency. In the bit-

stream environment the oscillation frequency is determined by

(10) and is precisely fB/N where fB is the bit-rate, N = 2R

and R is the word width of the SACs in the integrators. The

bit-stream output as described by (8) will have the number of

quanta vary in a sinusoidal manner. With (8) in perspective,

this can be effectively summarized by Br(kTB) ∝ sin (ωkTB)where TB = 1/fB and k = 0, 1, 2, . . .∞.

To ensure that the magnitude of S varies between negative

and positive full scale, one of the two integrators must be

initialized to +1.0sR and the other to 0.0sR. This has been

5

Load∫ ∫Init Init

RunRun

0.0sR1.0sR

S

fB

ALTERA STRATIX FPGAL6385

DriverGND

VDC15V-330V

MOSFET

SplitterSignal STW28NK60Z

(a) Sinusoidal Generator Schematic

0.1 0.105 0.11 0.115 0.12 0.125 0.13

0

0.2

0.4

0.6

0.8

1

Time, secs

S

(b) Sinusoidal Bit-Stream

Fig. 5. Sinusoidal Generator

diagrammatically shown using two-pole switches.

Fig. 5(b) shows a 30ms section of the simulated bit-stream

signal at S. As the magnitude goes more positive, the number

of positive quanta increase. Since more positive quanta are

being ’strung’ together, the switching frequency effectively

reduces. At the zero crossing of the sinusoid, the number

of positive and negative quanta are the same and very well

interleaved. Thus the switching frequency is the highest. At

large negative magnitudes there are more negative quanta

which also results in a reduction of the switching frequency.

This variation in switching frequency leads to the spectrum

being spread-spectrum. The bit-stream output at S is ideally

suited to drive a two state power stage provided the switching

frequency is low enough to keep the switching losses within

specifications. According to (10), the crossover frequency

depends on the bit-rate and the word width of integrator and

thus for a given sinusoidal frequency at S, if fB is to be

reduced then R must also be reduced.

The sinusoidal generator has been synthesized on an Altera

Stratix FPGA. The bit-stream at S in Fig. 5(a) has been

analysed on an Agilent 35670A dynamic signal analyser. The

instrument has been set up for an FFT analysis with a Hanning

window and 1600 lines of resolution. A 50 frame average has

been imposed to reduce the measurement noise. The THD

measurement over 63 harmonics (up to 3.2kHz) as determined

by the 35670A are presented in Table II.

With R = 8 the THD is only 0.42% and clearly has the

best performance. However, the switching frequency is 40kHz

which may not be acceptable for particular switching devices.

With R = 6, the switching frequency is 10kHz and produces

a sinusoid with a THD of 3.3%. Although the switching

frequency is acceptable for a larger variety of devices, the

spectra contains harmonics in the 5kHz to 10kHz band. For

TABLE IITOTAL HARMONIC DISTORTION (63 HARMONICS)

R fB (KHz) Measured THD(%)

2 1.257 68224

3 2.513 71.02

4 5.027 21.3

5 10.053 8.9

6 20.106 3.3

7 40.212 1.2

8 80.425 0.42

register widths less than 5 the THD is greater than 21% and

hence these are unacceptable design choices. Based on current

technology, selecting R = 7 may be the best option.

The implementation of this generator (R = 8) on a

StratixTM FPGA consumes only 92 logic elements (LE).

Keeping in perspective the number of LEs available in current

and previous state-of-the-art devices, 92 elements is insignif-

icant. Additional LEs will be required for the generation of

fB and for conditioning the bit-stream output to drive the

power switches. In this study, the total number LEs used for

the production of a sinusoid, at the terminals of the power

switches, is less than 200. If a processor is required for

other purposes i.e. data logging, user interface etc, then a soft

processor could easily co-exist with the generator. Since the

generator is independent of the processor, its operation is also

independent of the state of the processor. Multiple generators

can also co-exist each being independent of the other. The

frequency of the generated sinusoid is fB/N and thus can

be changed, simply, by changing fB . Also, the stability of

the sinusoidal frequency is totally dependent on the stability

of the clock source and this equally affects processor based

techniques.

D. Single Phase Drive

A conceptual schematic of a single phase inverter is shown

in the un-boxed section in Fig. 5(a). The power stage consists

of four n-channel MOSFETS (ST28NK60Z). The bit-stream

is conditioned on the FPGA to drive the MOSFETS appropri-

ately. With a high-side blanking time of 1µs, a load of 10kΩand a DC link voltage of 100V, the spectra, at the mid-point

of one of the legs of the H-bridge, has been obtained using the

Agilent 35670A dynamic signal analyser. The instrument has

been set up for a 50 frame average with a Hanning window

and 1600 lines of resolution. The spectra has been obtained

over two frequency spans: 0 to 3.2kHz and 0 to 51.2kHz. The

normalized spectra (0dB at 50Hz), using linear and decibel

scales, are shown in Fig. 6. The magnitudes of the harmonics

are too small to be visible on a linear scale and hence the

logarithmic scale used in Fig. 6 is more informative. The

switching noise is spread over a wide range of frequencies and,

crucially, it is significantly lower at lower frequencies than at

higher frequencies. This alleviates post-inverter filter design.

The distortion measurements, determined from the 0-3.2kHz

data set, are tabled in Table III. The THDs, determined from 63

harmonics, range from 0.75% to 4.9%. With R = 6 the THD is

comparable to the results published in the literature. However,

with R ≥ 7 the performance of the bit-stream generator

6

TABLE IIIDISTORTION AT INVERTER OUTPUT

R THD(%) Total Distortion (-60dB) Total Distortion (-40dB)

6 4.92 15.72 11.14

7 1.81 5.7 0.0

8 0.75 2.52 0.0

is significantly better. The last two columns in Table III

entitled Total Distortion, account for every component in the

range of 0-3.2kHz with magnitudes above -60dB and -40dB

respectively. These metrics also show that the performance of

the generator with register widths greater than 7 is excellent.

However, with R = 6 the total distortion measure is relatively

poor. This is expected since with R = 6, the maximum noise is

in 5kHz to 10kHz band and hence the frequency components

in lower fringe of this band appear in the measure.

0 500 1000 1500 2000 2500 3000−80

−60

−40

−20

0

Freq,Hz

Ma

g,d

B

0 500 1000 1500 2000 2500 3000−80

−60

−40

−20

0

Freq,Hz

Ma

g,d

B

0 500 1000 1500 2000 2500 3000−80

−60

−40

−20

0

Freq,Hz

Ma

g,d

B

R = 8

R = 7

R = 6

(a) Low Frequency Spectrum

0 0.5 1 1.5 2 2.5 3 3.5 4

x 104

−80−60−40−20

0

Freq,Hz

Mag,d

B

0 0.5 1 1.5 2 2.5 3 3.5 4

x 104

−80−60−40−20

0

Freq,Hz

Mag,d

B

0 0.5 1 1.5 2 2.5 3 3.5 4

x 104

−80−60−40−20

0

Freq,Hz

Mag,d

B

R = 8

R = 7

R = 6

(b) Wide-band Spectrum

Fig. 6. Measured Harmonics at Inverter Output with R = 6, 7, 8

IV. CONCLUSIONS

A simple technique for the generation of high quality

sinusoidal signals has been presented. The technique uses a

bit-stream representation and digital logic hardware on FPGAs

to produce these high quality sinusoidal signals. The technique

is naturally suited to two state power switches. Using this

technique, a single phase inverter has been demonstrated.

The generator requires less 200 LEs on a Stratix FPGA.

The performance of this technique has been experimentally

quantified and shows that a THD between 0.75% to 4.92% can

be obtained with minimal effort. Although, this study focused

on the generation of a 50Hz signal, the sinusoidal frequency

can be easily varied.

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