I

1 A DUAL MEDIA INDUSTRIAL LAN FOR REAL TIME APPLICATIONS

N Ramesh Babu, Shailendra Nigam, KCS Murty Central E lec t ron i cs Engineering Research I n s t i t u t e ,

P i l a n i - 333 031 (Raj) I nd ia . FAX: 0091-15951-2294

Abstract: I n order t o i n teg ra te process con t ro l instrumentation cons is t i ng o f programmable l o g i c c o n t r o l l e r s and PCs, which are already i n s t a l l e d i n a p lan t , an i n d u s t r i a l network i s being designed as a backbone f o r communication. The present paper describes the design and development aspects o f t he network. The design o f hardware and software i s discussed deal ing w i t h the a r b i t r a t i o n , redundancy and in te r face problems. To provide r e a l t ime features, a Min i MAP 3.0 a rch i tec tu re i s decided.

As a p a r t o f t he system, an i n t e l l i g e n t LAN Con t ro l l e r based on 1/0 channel i s developed f o r supervisory computer in ter face. The LAN c o n t r o l l e r uses MC68824 Token Bus Con t ro l l e r (TBC), which implements the Media Access Control (MAC) funct ions o f the data l i n k layer , as spec i f i ed by I E E E 802.4 standard. An onboard processor takes up a l l communication tasks.The main g lobal resource i s a shared memory f o r b u f f e r i n g and processing o f t ransmi t and receive messages. This b u f f e r i s shared by TBC, Host and l o c a l processor(LP). The communication between m u l t i p l e processors i s through a Flag Byte Register and a Command/Response block o f memory. The i n t e r r u p t mechanism between Host and l o c a l processor i s invoked by the Flag Byte Register. Since the re are three bus masters which can access the global memory and request it on asynchronous basis, c o n f l i c t s may occur. To resolve these c o n f l i c t s an A r b i t e r i s designed. The a r b i t e r samples the requests o f three masters and decides t o whom the grant i s t o be given us ing a F i n i t e State Machine (FSM) implemented i n PAL. Dual media redundancy i s designed a t t he phys ica l l e v e l w i t h dup l i ca t i on o f t he medium and the modem. The change over from a f a u l t y medium t o a heal thy one i s through a dec is ion l o g i c which continuously monitors both the media.

I. INTRODUCTION

Though LAN technology has s t a b i l i z e d we l l , there i s s t i l l a quest f o r i n d u s t r i a l LANs w i t h s u f f i c i e n t rea l timeness and f a u l t tolerance. Map compatible i n d u s t r i a l networks provide a standard mechanism o f i n t e g r a t i n g process inst rumentat ion w i th rea l t ime responses needed f o r most o f t he P lan t ' s needs. I n order t o i n teg ra te i so la ted Processes f o r r e a l i s i n g d i s t r i b u t e d con t ro l , a backbone network i s being designed f o r peer t o peer communication.

Min i MAP 3.0 a rch i tec tu re supports media access protocols w i t h de te rm in i s t i c access , upper l aye r

software f o r l o g i c a l l i n k con t ro l and app l i ca t i on l aye r d i r e c t l y u t i l i s i n g these services.System development around t h i s a rch i tec tu re i s chosen. The hardware development invo lves i n t e l l i g e n t network c o n t r o l l e r s w i t h d i f f e r e n t backplane bus in ter faces. A l l communication tasks are taken over by the network c o n t r o l l e r s and in te r face t o phys ica l media on one end and t o host on the other side. The dual media i s chosen so t h a t transmission w i l l always be done on both media and when a cable f a u l t occurs the reception o f data i s switched over from f a u l t y one t o heal thy one. The design o f hardware and software i s discussed below w i t h specia l emphasis on the a r b i t r a t i o n scheme, redundancy and i n t e r f a c i n g problems .

I 1 . CONTROLLER ARCHITECTURE

The block diagram o f t he LAN c o n t r o l l e r i s shown i n Fig.1. The c o n t r o l l e r i s designed around

1: T o * u IUS

FIG4 MAP 3.0 COWATIIKE WTELLIGENT LAN CONTROLLER

MC 68824 Token Bus Con t ro l l e r (TBC), which implements the Media Access Control (MAC) funct ions o f t he data l i n k layer , as spec i f i ed by IEEE 802.4 standard. The onboard processor, SAPx 80186 (Local Processor) re l i eves the Host from the communication overheads and c a r r i e s out a l l t he tasks l i k e TBC i n i t i a l i z a t i o n and creates proper environment f o r Transmission/Reception o f data by TBC. A 16KB RAM i s used as l o c a l memory o f l o c a l processor f o r s t o r i n g and processing o f run t ime variables. A 128KB EPROM

1 This work i s supported i n p a r t by a grant o f M/s Elec t ron i c Corporation o f I n d i a Ltd.

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conta ins 80186 i n i t i a l i z a t i o n , TBC i n i t i a l i z a t i o n and communication software modules. The g lobal memory o f 128KB can be accessed by TBC, HOST and l o c a l processor(LP) asynchronously. I n t e r f a c e l o g i c converts s igna ls o f I n t e l convention t o corresponding s igna ls o f Motorola and vice-versa t o access TBC by the l o c a l processor. The communication between m u l t i p l e processors i s through a Flag Byte Regis ter and a Command/Response b lock o f memory. The i n t e r r u p t mechanism between Host and l o c a l processor i s invoked by t h e Flag Byte Register.The design a l lows t h e l o c a l processor t o access i t s own resources and TBC on i t s l o c a l bus which r e s u l t s i n p a r a l l e l processing fea ture o f t h e design, i .e . , l o c a l processor can access l o c a l devices on l o c a l bus wh i le TBC and Host are a c t i v e on the g lobal bus.

A. Access Cycles :

The g lobal resources are accessed by e i t h e r TBC, l o c a l processor o r host by generating a request t o the a r b i t e r . The a r b i t e r generates grant t o one o f the devices and t h e access cyc le i s i n i t i a t e d . I n a d d i t i o n t o t h e th ree access cyc les generated by the three masters, t h e l o c a l processor generates TBC and l o c a l memory access cycles. Hence t h e system conta ins f o l l o w i n g operat ing cycles.

* LP t o TBC Read/Write cycle. * LP t o Local RAM ,ROM Read/Write Cycle. * LP t o Global RAM Read/Write Cycle. * TBC t o Global RAM Read/Write Cycle. * HOST t o Global RAM Read/Write cyc le .

A f t e r the cyc le i s i n i t i a t e d , the completion o f g lobal access cyc le i s ind ica ted by the same master so t h a t a r b i t e r can grant another pending request. The e n t i r e design i s asynchronous, a l low ing d i f f e r e n t c lock speeds between 80186, TBC and t h e HOST . - B. Arch i tec tu ra l Contrasts :

An important a r c h i t e c t u r a l con t ras t i s the d i f fe rence i n t h e mul t ip lexed ( I n t e l 80186) and non mul t ip lexed (Motorola) buses o f TBC. The second d i f fe rence i s i n the generation o f Read w r i t e signals.Motorola accesses memory by means o f one e a r l y R/W s igna l and a l a t e r CE/ generated from data strobes and memory ch ip s e l e c t decoding. However, I n t e l generates memory se lec ts by d r i v i n g an e a r l y CE/ and then s t a r t s data t r a n s f e r by d r i v i n g RD/ o r WR/ respect ive ly . Another important con t ras t i s t h e byte o rder ing o f memory f o r 16-b i t buses. I n t e l convention places the higher order by te i n t h e h igher (odd) addresses, whereas Motorola places the higher order byte i n the lower (even) addresses. This problem i s solved by the i n t e r n a l byte swapping op t ion o f TBC. Another d i f f e r e n c e i s i n memory access. I n I n t e l convention A0 and BHE/ are used t o enable devices on the lower h a l f and upper h a l f o f data bus respec t ive ly whereas LDS/ and UDS/ are used i n Motorola convention. I n Motorola a rch i tec tu re , R/W* i s v a l i d very e a r l y i n t h e cyc le before UDS/ and LDS/ asser ta t ion. I n order t o ensure t h e t i m i n g spec i f i ca t ion , R/W* o f TBC i s generated us ing the s ta tus l i n e s o f 80186.

- C. A r b i t r a t i o n 1

Since there are th ree bus masters which can access t h e g lobal memory and request t h e bus on asynchronous basis, c o n f l i c t s may occur. To resolve these c o n f l i c t s the a r b i t e r samples t h e requests of three masters and decides t o whom t h e grant i s t o be given by a F i n i t e State Machine (FSM) . Since t h e bus t ransac t ion o f Host can not be extended t o more than 2 . 5 microseconds f o r p red ic tab le performance, Host i s given p r i o r i t y i n such a way t h a t Host need no t wa i t f o r more than one t ransac t ion under most circumstances.The a r b i t e r samples above requests and a l s o the s ta tus o f the cur ren t cyc le (Busy 1 Fig(2) . When cur ren t cyc le i s completed t h e a r b i t e r decides t o whom t h e grant i s t o be given . The grant i s given a f t e r one c lock delay so t h a t necessary se t up t imes are met between two cycles. The p r i o r i t i e s f o r grant are :

1. Host request i f previous memory t ransac t ion i s

2. TBC request 3. HOST request 4. LP request

not t h a t o f Host

Thus e n t i r e design o f t h e c o n t r o l l e r i s asynchronous, a l low ing d i f f e r e n t c lock speeds between l o c a l processor, TBC and Host.

CLK

REQUEST 1/

Wait I/ 2 BUSY -#

GRANT 1

Done h FIG - 2 ARBITRATION LOGIC

D. Global Address/Data Buf fers : _ _ _ The th ree masters access g lobal RAM by g e t t i n g

access t o t h e g lobal address and data buses. The t i m i n g cons t ra in ts i n bus s e t up and ho ld t imings t o be met by each master are taken care by prec ise ly enabl ing the bu f fe rs w i t h synchronised delay with a common c lock w i t h a per iod o f 40 nsec. The th ree masters which generate t h e i r own read and w r i t e s igna ls a t d i f f e r e n t t imings are synchronised t o generate g lobal memory read and w r i t e s ignals . A l l t he three masters map t h e g lobal memory i n t o d i f f e r e n t address ranges. A p o r t i o n o f t h e memory map o f each processor i s windowed i n t o t h e g loba l RAM area. The window area can be f l e x i b l y selected.

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- E. F lag by te r e g i s t e r and Reset l o g i c

I n t e r communication between t h e processors i s by command and response mechanism i n a memory block. A f t e r a command i s w r i t t e n i n shared memory; the other processor has t o be ind icated. This i s done through i n t e r r u p t mechanism between Host and Local processor . Host can cause an i n t e r r u p t t o l o c a l processor by w r i t i n g data 02. Host resets the l o c a l processor by p lac ing 00 I n t h e address bus. S i m i l a r l y , data 02 causes an i n t e r r u p t t o Host. The l o c a l processor can a l s o c l e a r t h e i n t e r r u p t t o Host by w r i t i n g data 00.

_ - F. Bus ExceDtion L

TBC accesses t h e bus asynchronously and expects acknowledgement s igna l f o r each cyc le. The access cyc le o f TBC needs forced te rmina t ion under two events. The f i r s t one i s when TBC i s busy i n accessing g lobal RAM i n l i m i t e d b u r s t mode and host i s ho ld ing t h e request causing it t o be i n w a i t s t a t e f o r more than 2 . 5 microseconds. Such an event i s p red ic ted we l l i n advance and c o r r e c t i v e ac t ion i s appl ied by generating terminate and r e t r y exception t o TBC. The other event i s when address s t robe o f TBC i s he ld low f o r a long t ime and causing bus hog by TBC. Both events are corrected us ing bus exception cond i t ion t o TBC.

111. SOFTWARE IMPLEMENTATION

The software consis ts o f two par ts . One p a r t res ides i n onboard EPROM o f network c o n t r o l l e r performing f o l l o w i n g major funct ions:

-Sel f d iagnost ics . - I n i t i a l i z a t i o n . -Queue management. - I n t e r r u p t handl ing .

The o ther p o r t i o n res ides on t h e host performing f o l l o w i n g func t ions

- Message passing t o network c o n t r o l l e r . - Message recept ion from network c o n t r o l l e r . - Commands t o Network C o n t r o l l e r f o r network

management.

A.Self Diagnostics

A l l t h e hardware sub-systems o f t h e network c o n t r o l l e r can be f u n c t i o n a l l y tes ted l i k e TBC t o memory read/w r i t e , recept ion and t ransmi s s i on o f frames, Global memory access by t h e th ree masters, Local memory access by the l o c a l processor and Modem f u n c t i o n a l i t y .

- B. I n i t i a l i z a t i o n

The l o c a l processor has t o i n i t i a l i z e the var ious operat ing network parameters and p o i n t e r s o f t h e TBC. Some o f them are token r o t a t i o n t imers, var ious po in te rs t o queues, var ious e r r o r counter threshold values etc .

C.Queue management

Smooth operat ion o f Network c o n t r o l l e r requi res meticulous management o f t ransmiss ion and recept ion queues which cons is t o f a l i n k e d l i s t o f frame descr ip to rs (FD), b u f f e r descr ip to rs (BD) and data b u f f e r s (DB). It i s requi red t h a t p r i o r t o sending are i n i t i a l i z e d , re levant parameters p roper ly f i l l e d and then corresponding DB‘s are f i l l e d w i t h t h e data.This FD i s t o be l i n k e d t o the appropr ia te p r i o r i t y queue. S i m i l a r l y FD‘s, BD’s and DB’s o f frames which have been t ransmi t ted are removed from the t ransmiss ion queue,relevant parameters reset , and made ready f o r reuse. The l o c a l processor mainta ins a l i n k e d l i s t o f FD’s and BD’s f o r recept ion o f frames by TBC. The TBC p icks up frames from t h i s f r e e pool queue and uses them t o receive incoming message. Messages received i n t h e Rx-queue are passed on t o t h e host. A f t e r they have been processed by host they are c leared and made ready f o r reuse.

D.InterrUDt Handling

There are th ree sources o f i n t e r r u p t s one from host t o l o c a l processor,the o ther from l o c a l processor t o host and l a s t l y from TBC t o l o c a l processor. TBC can generate i n t e r r u p t s f o r var ious reasons r e f l e c t i n g t h e var ious cond i t ions occur r ing i n the system. But mainly i n t e r r u p t s in forming recept ion o f a frame o r t ransmiss ion o f frame occur very f requent ly . I n case o f recept ion o f a frame l o c a l processor passes t h e p o i n t e r t o t h e received message t o host t o read t h e message. I n case o f transmission i n t e r r u p t s , l o c a l processor c lears t h e frame descr ip to r and b u f f e r descr ip to r f o r reuse.

For o ther cond i t ions such as BD pool empty o r FD pool empty l o c a l processor makes BD’s and FD’s and l i n k s them t o t h e queue. Local processor and host processor communicate t o each o ther through i n t e r r u p t s generated by f lag-by te r e g i s t e r . Local processor mainly generates i n t e r r u p t s t o host whenever i t receives a message, o r when it passes t h e r e s u l t s o f d iagnost ics o r any o ther abnormal cond i t ion occur r ing i n the system. The i n t e r r u p t s are c leared a f t e r appropr ia te a c t i o n has been taken by t h e invoked.

E.Host Software

a message one FD and one o r more BD‘s

-~ Host has t h e bas ic r e s p o n s i b i l i t y o f submi t t ing

messages t o t h e Network c o n t r o l l e r and rece iv ing the messages from t h e Network c o n t r o l l e r . Host accesses t h e g lobal RAM ,places t h e message i n a data b u f f e r and generates a comnand t o l o c a l processor. The s ta tus o f t ransmiss ion i s read by the host through t h e response b lock .

Local processor generates an i n t e r r u p t t o the host which i n t u r n invokes t h e receive i n t e r r u p t subroutine t o read t h e message and c l e a r t h e b u f f e r memory .

The t h i r d task i s t o s e t t h e operat ing environment o f TBC by s e t t i n g and reading var ious

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network and TBC parameters . Host a lso d i r e c t s the loca l processor t o car ry out d iagnost ics and repor t the resu l ts . Host does not se t the parameters d i r e c t l y but the set and read value commands are given t o l o c a l processor ,which i n t u r n c a r r i e s them out.

I V . PHYSICAL LAYER INTERFACE

The phys ica l i n t e r f a c e i s a s i n g l e channel phase coherent c a r r i e r band FSK modem a t 5 Mbps. Fau l t to lerance has been introduced a t t h e phys ica l l e v e l f o r more r e l i a b i l i t y as the phys ica l medium running through the whole f a c t o r y i s most suscept ib le t o damages.In t h e present scheme modem as wel l as medium are dupl icated . F i g (3 )

FIG - 3 DUAL MEDIA REDUNDANCY LOGIC

Data i s t ransmi t ted simultaneously on both t h e channels. S i m i l a r l y data i s received data on both the modems, but one i s se lected by the channel c o n t r o l l e r f o r inpu t t o TBC. The channel c o n t r o l l e r decides the heal thy o r f a u l t y channel on the bas is o f s i lence and bad data symbols generated by the modems .The channel c o n t r o l l e r a l s o detects frame s t a r t and end s igna ls so t h a t swi tch ing can take p lace dur ing frame t o frame i n t e r v a l s . Now we w i l l consider th ree p o s s i b i l i t i e s t o describe the operat ion o f the channel c o n t r o l l e r .

- Both t h e channels are heal thy and are working

- The working channel goes bad ,whi le o ther l i n e

- The working channel i s heal thy wh i le the other

normally.

i s heal thy.

channel goes bad.

I n the f i r s t case the channel c o n t r o l l e r re ta ins the present ly se lected medium. I n the second case t h e channel c o n t r o l l e r detects t h a t the working channel t o be bad by de tec t ing s i lence symbols f o r abnormally long t ime ,whi le t h e o ther channel does no t i n d i c a t e any abnormal s i lence. A t t h i s p o i n t i t switches over t o heal thy channel dur ing non frame transmission periods. I n case th ree the channel c o n t r o l l e r informs the s ta tus t o the Host so t h a t c o r r e c t i v e measures can be taken and bad channel i s ind icated. Thus,whenever a channel change Over i s Performed the Host i s informed SO t h a t mal funct ion ing channel can be r e c t i f i e d . Apart from these a c t i v i t i e s the channel c o n t r o l l e r

provides the cur ren t s ta tus o f t h e channel t o the Host whenever it so desires. The Host a l s o has the op t ion t o cause channel c o n t r o l l e r t o swi tch t o a p a r t i c u l a r channel. Th is i s use fu l t o t e s t a p a r t i c u l a r channel. The channel change over can a lso be performed manually .

V . CONCLUSIONS

A LAN w i t h above features i s under development a t t h i s i n s t i t u t e which forms a subsystem o f a d i s t r i b u t e d process cont ro l system. The network forms the backbone t o i n t e g r a t e process c o n t r o l l e r s over data highway. An i n t e l l i g e n t c o n t r o l l e r a rch i tec tu re i s chosen so t h a t complete communication tasks are o f f loaded and the host i s l e s s burdened. More over augmentation o f e x i s t i n g systems i s easy due t o modular a rch i tec tu re . B u i l t i n protocols l i k e immediate response mechanisms w i t h RWR frames, dynamic i n s e r t i o n and d e l e t i o n o f nodes w i t h added phys ica l media redundancy he lp i n b u i l d i n g a robust network.

VI. ACKNOWLEDGEMENTS

The authors wish t o thank our d i r e c t o r , D r . W.S. Khokle and Dr.Hausila Singh, Area Chairman f o r t h e i r constant encouragement and f u l l f ledged support f o r car ry ing out t h i s work a t CEERI, P i l a n i .

V I I . REFERENCES

1. Local Area Network 802.4 Token Passing Access Method and phys ica l layer spec i f i ca t ions .

2 . The MAP repor t by Jack Holl ingum

3. TBC Users manual by Motorola Inc .

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