8
Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy 0. van der Sluis', R.A.B. Engelen', W.D. van Driel2, M.A.J. van GiIs2, R.B.R. van Silfhout' 1) Philips Applied Technologies, High Tech Campus 7, 5656 AE Eindhoven, The Netherlands 2) Philips Semiconductors, 6534 AE Nijmegen, The Netherlands e-mail: o1afvan.der.sluisgphilips.com, phone: +31 40 2748778 Abstract studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. For the development of state-of-the-art CMOS The validity and applicability of the method will be technologies, the integration and introduction of low-k demonstrated by considering several Cu/low-k back-end materials are one of the major bottlenecks due to their bad structures. The obtained results are in good agreement thermal and mechanical integrity and the inherited week with experimental observations. interfacial adhesion. The use of Ultra Low-K (ULK) materials, such as porous dielectrics, will require 1. Introduction significant development effort in order to result in reliable Due to the reduced design margins and shorter time- interconnect structures that are able to withstand the IC, to-market in IC back-end process development, trail-and- packaging and assembly related thermo-mechanical and error approaches are not sufficient anymore and a more mechanical forces. Especially the forces resulting from sophisticated methodology based on numerical simulation packaging related processes such as dicing, wire bonding, and optimization techniques is required. With this virtual bumping and molding are critical and can easily result in prototyping and qualification methodology thermo- cracking, delamination and chipping of the IC back-end mechanical reliability issues are already included in the structure if no appropriate measures are taken. design phase rendering proposed design changes more For the thermo-mechanical design of IC back-end efficient and thus cheaper. structures, an experience based/trial-and-error approach The thermo-mechanical reliability of bond pads due to has been mainly used in the past. This is not only time the bad thermal and mechanical integrity of the low-k and money consuming, but also inherently troubles the materials and associated interfaces, is still an important inclusion of packaging requirements in the earlier stages issue in the development of new Cu/low-k CMOS of back-end process development. Due to the reduced technologies [1]. The resulting forces due to the wire design margins and shorter time-to-market, this trail-and- bonding process, qualification tests and packaging error approach is not sufficient anymore and novel processes can easily result in reliability problems like methodology based on advanced simulation and bond pad delamination and low-k cracking. Wire optimization techniques is required. With this virtual associated failures are one of the most common in the prototyping and qualification methodology thermo- industry [2]. A critical qualification test for wire integrity mechanical reliability can be dealt with already in the is the so-called wire pull test. The typical configuration of design phase including the interaction with packaging and this wire pull qualification test where the wire is pulled by qualification processes. a hook is visualized in Figure 1. The wire and the bond This paper presents an efficient method to describe the pad structures should withstand a certain force level damage sensitivity of three-dimensional multi-layered before failure of the wire or the bonds occurs. structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. The method is applied to advanced IC back-end structures, revealing the critical locations at which delamination might occur. In order to bridge the length Figure 1 Schematic of the wire pull test scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in Frtenw lwkpoessti iepl a finite element code. In this way, effects of e.g. qulfcto tes is cicadutohelwsrtrl packaging and wire bond loading at global level can be inertofhelwkmeiasndsoctditrae. 1]-4244-0276-X/06/$20. 00®)2006 IEEE I-4- 7th. Int. Conf: on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006

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Page 1: [IEEE 7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems - Como, Italy (24-26 April 2006)] 7th. Int. Conf. on

Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures UsingArea Release Energy

0. van der Sluis', R.A.B. Engelen', W.D. van Driel2, M.A.J. van GiIs2, R.B.R. van Silfhout'1) Philips Applied Technologies, High Tech Campus 7, 5656 AE Eindhoven, The Netherlands

2) Philips Semiconductors, 6534 AE Nijmegen, The Netherlands

e-mail: o1afvan.der.sluisgphilips.com, phone: +31 40 2748778

Abstract studied while taking into account the possibility ofoccurring failure phenomena at the local, back-end level.For the development of state-of-the-art CMOS The validity and applicability of the method will be

technologies, the integration and introduction of low-k demonstrated by considering several Cu/low-k back-endmaterials are one of the major bottlenecks due to their bad structures. The obtained results are in good agreementthermal and mechanical integrity and the inherited week with experimental observations.interfacial adhesion. The use of Ultra Low-K (ULK)materials, such as porous dielectrics, will require 1. Introductionsignificant development effort in order to result in reliable Due to the reduced design margins and shorter time-interconnect structures that are able to withstand the IC, to-market in IC back-end process development, trail-and-packaging and assembly related thermo-mechanical and error approaches are not sufficient anymore and a moremechanical forces. Especially the forces resulting from sophisticated methodology based on numerical simulationpackaging related processes such as dicing, wire bonding, and optimization techniques is required. With this virtualbumping and molding are critical and can easily result in prototyping and qualification methodology thermo-cracking, delamination and chipping of the IC back-end mechanical reliability issues are already included in thestructure if no appropriate measures are taken. design phase rendering proposed design changes more

For the thermo-mechanical design of IC back-end efficient and thus cheaper.structures, an experience based/trial-and-error approach The thermo-mechanical reliability of bond pads due tohas been mainly used in the past. This is not only time the bad thermal and mechanical integrity of the low-kand money consuming, but also inherently troubles the materials and associated interfaces, is still an importantinclusion of packaging requirements in the earlier stages issue in the development of new Cu/low-k CMOSof back-end process development. Due to the reduced technologies [1]. The resulting forces due to the wiredesign margins and shorter time-to-market, this trail-and- bonding process, qualification tests and packagingerror approach is not sufficient anymore and novel processes can easily result in reliability problems likemethodology based on advanced simulation and bond pad delamination and low-k cracking. Wireoptimization techniques is required. With this virtual associated failures are one of the most common in theprototyping and qualification methodology thermo- industry [2]. A critical qualification test for wire integritymechanical reliability can be dealt with already in the is the so-called wire pull test. The typical configuration ofdesign phase including the interaction with packaging and this wire pull qualification test where the wire is pulled byqualification processes. a hook is visualized in Figure 1. The wire and the bond

This paper presents an efficient method to describe the pad structures should withstand a certain force leveldamage sensitivity of three-dimensional multi-layered before failure of the wire or the bonds occurs.structures. The index that characterizes this failuresensitivity is an energy measure called the Area ReleaseEnergy, which predicts the amount of energy that isreleased upon crack initiation at an arbitrary positionalong an interface. The benefits of the method are: (1) thecriterion can be used as damage sensitivity indicator forcomplex three-dimensional structures; (2) the criterion isenergy based, thus more accurate than stress-basedcriteria; (3) unlike fracture mechanics, no initial defectsize and location has to be assumed a priori.

The method is applied to advanced IC back-endstructures, revealing the critical locations at whichdelamination might occur. In order to bridge the length Figure 1 Schematic of the wire pull testscale difference between the wafer level and the back-endstructures, a multi-scale method has been implemented in Frtenw lwkpoessti iepla finite element code. In this way, effects of e.g. qulfcto tes is cicadutohelwsrtrlpackaging and wire bond loading at global level can be inertofhelwkmeiasndsoctditrae.

1]-4244-0276-X/06/$20. 00®)2006 IEEE I-4-7th. Int. Conf: on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006

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An example of actual bond pad delamination of a initial crack. The ARE value indicates the risk ofCMOS90 Cu/low-k process due to this wire pull delamination of the interfaces without knowing a prioriqualification is given in Figure 2. the exact location of possible failure(s). This method will

be used to study the reliability of several three-dimensional interconnect structures. The obtained resultswill be related to experimental observations.2. Numerical approach

Multi-scale methodTo couple the local level (interconmect level) and the

global level (packaging level), a dedicated three-Figure 2 Bond pad delamination of Cu/low-k process (with dimensional multi-scale method has been developed. Atcourtesy of Philips Semiconductors Kaoshiung) the packaging level, the simulations are perfonned using

homogenised (effective) anisotropic stiffness matricesThe thermo-mechanical reliability of the (low-k) bond obtained from the bond pad level. At the local level,

pads depends strongly on the metal and via layout of the simulations are carried out by applying the global degreesback-end layers beneath this bond pad. The copper metal of freedom on the local models as function of theirlines and vias act as mechanical support in the relatively location.weak low-k matrix. Due to the complex interaction of The effective anisotropic stiffness matrices SUki aremultiple processes, materials and interfaces, however, an obtained by using the constitutive relation in a variationaloptimum metal layout design is difficult to design on format:beforehand. An example of a typical back-end layout isvisualized in Figure 3. %j =SUk/ 'ik' (1)

in which 8%1 is the variation in stresses whereas Asis the variation in strains. The coefficients of the stiffness

Cu matrix are numerically determined by imposing sixindependent deformation modes on the local model, i.e.n fl ii lr ~~~~low-k ,.. ,wvias for each mode (ij): 8e # 0 with i,j=1,2,3. In order to

M _ . J L = _ 3hardmask prescribe these deformation modes on the unit cell it is

common in micromechanics to adopt uniform boundary[_ ~conditions, i.e. either a uniform strain or stress [6].

However, it has been shown that mixed boundaryFigure 3 Cu/low-k back-end structure beneath bond pad conditions, which are a combination of both types(dielectric material is not visible) mentioned above, yield better approximations of the

effective properties compared with the uniform boundaryIn order to investigate the structural integrity of the bond conditions [8]. Moreover, it has been proven that periodicpad, finite element analyses will be used allowing boundary conditions, yield the most accurate results foroptimization of the bond pad structure in the design general heterogeneous materials using a relatively smallphase. The methodology used is based on a three- unit cell size [9,10]. Therefore, periodic boundarydimensionca le sub-modeling approach similartto conditions will be used to prescribe the deformationWang et al [3]. In that approach the multi-scale modes on the unit cell.submodeling technique was combined with the VirtualCrack Closure Technique (VCCT) [3,4,5] in order to In [7], three-dimensional periodicity conditions havepredict energy release rates for interface cracks at specific been derived. Here only the result is given (see alsopositions and with a specified initial length. In this paper, Figure 4)equivalent stiffness matrices representing the mechanicalbehaviour of the back-end structures at the global, Y4378 =Y1265 - YI + Y4, (2)packaging level are calculated using a dedicated Y2376 = Y1485 - YI + Y2, (3)homogenisation procedure. Subsequently, thedisplacements at the global level can be calculated Y5678 =Y1234 - YI + Y5 (4)accurately. Next, the so-called localization step permits to These boundary conditions are applied on the so-determine local field variables by using the global called control vertices 1, 2, 4, and 5, which are present indisplacement solution field [6]. At this level, the Area the right-hand sides of the periodicity equations. ToRelease Energy (ARE) [7] will be calculated as failure prevent rigid body modes, all displacements of vertex 1indicator. Here, the amount of energy is calculated that is have been suppressed. Consequently, the control verticesreleased upon delamination of an area for any position 2, 4 and 5 are used to prescribe the individual deformationalong a critical interface without the need of inserting an modes.

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7 zone models [e.g., 14] can be used to calculate crackinitiation and propagation in an accurate way. However,as reported in [15], the applicability of these models for

4 brittle interface behavior results in numerical difficultiesas a result of snap back behavior. Only when using theproper nonlinear control techniques and a sufficiently finemesh, these problems can be circumvented.

6 For analyzing and comparing different back-end7 ~~~~~~~~~structures, we therefore have developed a different

1l2 method that results in a failure index called the AreaI : > Release Energy [7]. The method does not require any

Figure 4 The unit cell and the definition of the vertices for presupposed position of any initial crack. Instead, at anythe periodic boundary conditions desired plane within the specimen, an ARE value is

calculated which basically results from releasing an area

The resulting forces on the control nodes for each (having a defined dimension) around each point in the

deformation mode are used to calculate the stressesor e plane.Use of this Area Release Energy has some importantand subsequently, the effective anisotropic stiffness advantages compared with traditional approaches: (i) it ismatrix for each unit cell can be uniquely determined using an energy based failure criterion, which is more accurateEquation (1). Please note that our procedure does not for describing delamination damage than stress-basedrequire any assumption about geometric symmetry (e.g., approaches [7]; (ii) it is not required to assume a pre-orthotropy) when determining the effective stiffness existing delamination at a specific location with a specificmatrix. size, as is the case in traditional fracture mechanics based

Applying an arbitrary temperature step /IT on the approaches, such as J-integral and VCCT; (iii) it allowsunit cell and calculating the resulting thermal strains from an instant overview of the critical areas of specificthe displacements of the control nodes while applying the interfaces through a contour map and also makesperiodicity boundary conditions determines the effective comparison between different structures possible.thermal expansion coefficients a, for the unit cell. To explain the Area Release Energy method, a two-

dimensional example is used as depicted in Figure 5.Finally, the localization step consists of prescribing Here, for node i, a set of nodes is depicted that lie within

the displacements that are calculated at the global level on the area that will be released, defined by £.the outer surfaces of the local unit cell (i.e., the global- For each node i, the resulting area release value islocal step). The displacements for the nodes in the local calculated as (using Einstein's summation convention ofmodel that do not coincide with the global nodes, aresimply interpolated from the displacements of the nearest P i )neighboring nodes by using the global-local feature in G F u with j n1*- (5)MSC.Marc. It is thus possible to calculate the local state 2A ' 'variables, such as stresses and damage values, in the unit in which n equals the number of nodes that belong tocell as function of its global position. the released area. For 3D analyses, the released area

In [11], it has been shown that the accuracy of the 2local solution can be improved by using a multi-layer eqal A

isremeana rrhomogenisation step. In this homogenisation procedure, each node iS released.the different layers in the IC structure are homogenisedindividually instead of homogenising the total IC 2tstructure, which yields a multi-layer material model atglobal level.

Area release energy index F uDue to the brittle nature of the dielectric films, it has , 1 =u 3

been assumed that the use of (linear elastic) fracturemechanics is valid for describing the interfaceAreadelamination in Cu/low-k back-end structures [3,12]. Releae E AREdmethodWithin finite element analysis (FEA) the most commonly Release Energy (ARE) methodused methods to predict the crack driving force are J-integral calculations [e.g., 13] and Virtual Crack Closure Clearly, the reason behind the usage of releasing aTechniques (VCCT) [3,4,5]. A disadvantage of using predefined area instead of simply releasing individualthese methods is the need for knowing a priori the exact nodes (c.f., the nodal release energy method) iS to preventlocation of the delamination. As an alternative cohesive mesh dependency of the energy release values in non-

uniform grids. Numerical experiments have revealed that

7th. Int. Conf: on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006

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the corresponding mesh density should obey the The force applied on the global model equals 3 gram,following rule in order to obtain results that are converged which is a typical qualification loading of such a ballwith respect to the mesh density: bond. Further boundary conditions consist of a full

h < 0.25 X, (6) constraint of the bottom on the silicon in z-direction andfull constraints in x-direction on the left side of the model.

inewhichhfiourse,alltesiz theslargeste elemin thepapeThe material models used are linear elastic except for themesh. Of course, all results presented in the paper have auiu ae n h odwr htaemdldabee chce nms eedny

aluminum layer and the gold wire that are modeled asbeen checked on mesh dependency. lsopatcmtras

In [7], the method is validated by means of aelsopatcmerl.

INAFEM[7]teamentho isncvalidte byo mes oappe To illustrate the multi-layer back-end structure in the

NAFEMS delamination benchmark problem. It appears goa oe,Fgr hw h ifrn nstoithat te AREaluesmatch he anlytica ones

global model, Figure 7 shows the different anisotropicthat teRvumahhamaterial layers used in the global back-end model.

3. Application: advanced Cu/low-k back-endstructures

Global modelThe structural integrity of Cu/low-k bond pads during

wire pull test is one of the major reliability concerns dueto the large forces and stresses applied on the wire and theCu/low-k back-end structure. With the developed FEAmethodology the effect of different back-end designsunderneath the bond pad is investigated.

The global model, depicted in Figure 6, consists of abond pad with an opening of 70x70 mm2 that is covered Figure 7 Detail of the global model: the multi-layeredwith an aluminum layer, passivation layers, the ball bond back-end structure (each colour corresponds to a differentand a gold wire of 25 mm diameter. Underneath a back- anisotropic material)end structure is placed in a silicon die. Note that themechanical properties of the back-end structure result Local modelsfrom the application of Equations (1) to (4). In this paper, several bond pad structures are

Due to symmetry only half the bond pad is simulated considered as visualised in Figure 8, Figure 9 and Figureand the wire pull qualification test is simplified by 10. The layout of the unit cells is conform the CMOS090applying a force under an angle of 20 degrees with design rule manual: layers of hard mask, copper andrespect to the z-direction in the (x-z) plane. In reality the dielectric materials. For the sake of clarity, the hard maskwire pull qualification as visualized in Figure 1 results in and dielectric materials are not depicted in the figures. Ina skewed force on the bond ball that depends on the wire addition, the top layer of metal (metal 6) and dielectricgeometry and the position of the hook. layer between metal 5 and metal 6 are also not shown.

The layers of the unit cells include the dielectric layerForce between front-end silicon and metal 1 up till the last

copper metal level (metal 6). The bulk silicon and topaluminum layer are taken into account only in the globalbond pad model.

x Figure 8 Local structure A (hard mask, dielectricummaterials and top metal layer are not shown)

Figure 6 The global model including the loading on thegolden wire representing the wire pull test

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Figure 9 Local structure B (hard mask, dielectricummaterials and top metal layer are not shown)

Figure 11I Deformed global bond pad structure withcontourbands of the equivalent plastic strain (the redvalue corresponds to 3800 plastic strain)

The results for the various back-end structures arecollected in Figure 12. First of all, notice that the

Fiur 0 oclstucue (ad as,dileticmmaximum occurs at interface 3 and 4. ExperimentalFigure 10 Local structure C (hard mask, dielectricum results identify interface 4 as being the most critical

materials and top metal layer are not shown) which confirms our results. Second, it appears that theARE values for local structure C are the highest,

In Table 1, the outer dimensions of these back-end irrespective of the interface. This indicates that thisstructures are given. structure is the least favourable of the considered

Table 1 Outer dimensions of the local back-end structures, which has also been confirmed bystructures (in ftM3) experimental observations.

Structure A Structure B Structure C 1.20E+012.0x12.0x4.7 5.0x.0x4.71 16.0x16.0x4.71

1 .00E+00

~~tm2.~ In loa stutr B, th piclftevasi . t,pitcrehoflte viasin local structure C igs 2. Nimensiose2axim A v s b2 DC~~~~~~~~~~~~~~~~~~~~~~~~~

The displacements are calculated at the global level,

usinga thepicefetiveanistroick vistiffness tmaTries Toilsrt hesrnt fth R ehd

determined from the dlfferent local models (Section 2 1). aeAs~~ ~aneape'nFgr 1 tersligeuvln contourbands of ARE values and peel stresses are given

plastic strains on the deformed geometry as calculated for fothtresruuesiinrac4.Icnbebevd

4.~ ~ ~~ ~ ~ ~ ~ ~~~~~~~oReslt inetucue terface4.Itcambboseve

the wire pull test are given for the global model.ethatithe AR values ar ifr o thE strues (as

' that the AREvaluesareevelfor theodifferentuinterfaces

In the global simulation, the ARE values are already indicated in Figure 12) from which it could becalculated at each hardmaskldielectricum interface (see concluded that structure C is the most sensitive to failure.Figure3)withalength scale I 2.5 rim. In contrast, the peel stress levels show hardly any

difference between the local structures. These resultsclearly indicate the added value of energy based criteriasuch as the ARE methodology compared to a stress-basedapproach.

7th. Int. Conf: on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006

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scale value and at each location. Second, from Figure 14,the ARE values for local structure A increase withincreasing length scale. As no vias are present in thisstruicture, the interface is 'uniform' (hardmask-dielectrics). From te teory of factue mechanics, it isknown that the energy release value increases withincreasing crack length. Due to the aforementioned

(a) ARE - structure A (b) Peel stresses - structure A uniformity of the interface, this phenomenon is alsoapplicable to structure A.

ARE values at low-k interface1.2

m

~,1.0

>0.8

(c) ARE - structure B (d) Peel stresses - structure B 0.6-

*~0.4

o 0.2-

1 .OOE-04 5.OOE-04 1 .OOE-03length scale [mm]

Figure 14 Normalised maximum local ARE values at the(e) ARE - structure C (f) Peel stresses - structure C low-k interface for different length scale values

Figure 13 Global ARE values (a), (c), (e) and peelstresses (b), (d), (f) for the different back-end structures. . . I

| ~~~ARE values at via InterfaceIBased on ARE values, structure 3 is most sensitive to

1.2-failure. Based on peel stresses, no significant difference 1.between the structures is observed. 0

0.8-

Results at the local level < 0.6

Although the global ARE plots of the previous section 0.40.4reveal the critical locations of the bond pad structures, it 0.2does not account for the types of interfaces that areinvolved. This information is, however, important as 1.00E04 5.00E-04 1.00E-03these different interfaces have different interface length scale [mm]characteristics (a maximum value in a strong interface lcould be less critical compared to a non-maximum value Figure 15 Normalised maximum local ARE values at thein a weak interface). Therefore, local ARE simulations via interface for different length scale valueshave been performed in these critical regions as well inorder to determine the exact critical interfaces. Third, the maximum values at the low-k interface are

For the given bond pad structures the ARE values are lower than the values at the via interface (the values arecalculated at interface 4, being the most critical interface normalised with respect to the maximum ARE value,from the global simulations. Several values for the length irrespective of its location). Hence, the loading on the viascale X, defined to prevent mesh dependent results in the interface is higher. However, only if the individualARE values, have been used: 0.1 ptm, 0.5 ptm, and 1.0 interface strengths are known, the ARE values could beptm. The value of 0.1 pIm is about the same size as the weighted with these values. In that way, the predictiondiameter of a typical via: 0.13 ptm, whereas 1.0 ptm is can be made whether failure would occur in the low-k orabout the size of the pitch between the thick vias in local the via interface.structure B. Fourth, in Figure 15, the ARE values of structures B

The results are given in Figure 14 and Figure 15. and C first show a decrease followed by an increase withNotice that a distinction is made between the interfaces at increasing length scale. The decrease can be explained bythe via and low-k locations. Of course, for structure A, the fact that, with = 0.5 pim, more influence of thethere are no vias so this structure is omitted from Figure dielectrics is taken into account. Clearly, the energy14. stored in this material is less than the energy stored in theA number of observations can be made from these vias (due to the displacement constraint caused by the

local ARE simulations. First, it appears that local vias). As a result, theARE value is lower. An even higherstructure C is the most sensitive to failure, for each length value of the length scale, £ 1.0 pim, results in higher

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values of the ARE. This can be explained by the local bond pad structures resulting from the imposedfollowing pictures in Figure 16. For £=0.1 ptm, Figure boundary conditions at the global packaging level is thus16(a), the ARE values are the highest around the vias. In feasible. No initial cracks or imperfections had to becontrast, for £ =1.0 ptm, the highest ARE value appears in inserted in the models. The method thus allows a rankingbetween the via region in the center. As was already between the different three-dimensional bond paddiscussed, the distance between the 'via islands' equals designs. The global results confirmed the experimentally0.85 ptm. Therefore, for the nodes in the center, the ARE observed critical interface location and the most failurevalues are based on all sixteen surrounding vias resulting sensitive local structure. The local models confirmed thein a high value. Thus, by using a larger length scale value, least favourable structure and also details of the differentmore influence of the surrounding is taken into account. interface loading conditions are obtained which facilitatesThis can also be observed when comparing the ARE to take into account the difference in interface strengths ofvalues of structure B from Figure 14 and Figure 15. For the different interfaces.the smallest length scale, the difference in ARE values The influence of the length scale has been shown.between the two interfaces is the largest, i.e. the values This value should either be related to geometrical detailsare 'independent' whereas with increasing length scale, ofthe back-end structures and/or to experimental results.there exists an interaction between the two locations. Acknowledgements

The support and assistance of all the members of theCOPACK project, in particular our colleagues StephaneOrain and Vincent Fiori of the Crolles2 Alliance andTheo Martens of Philips Semiconductors Kaoshiung, isgreatly appreciated. Also the support from the Goudaoffice of MSC Software for the efficient implementationof the Area Release Energy methodology in MSC.Marc isappreciated.References

(a) (b) 1. International Technology Roadmap forFigure 16 ARE values for local structure B, with (a) Semiconductors, 2003 edition, International£=0.1 pIm and (b) £=1.0 pm SEMATECH.

2. Van Driel, W.D., Janssen, J.H.J., Van Silfhout,The question that rises is: What is the appropriate R.B.R., Van Gils, M.A.J., Zhang, G.Q., Ernst, L.J.,

value of £? At the moment, this is still a subject of "On Wire Failures in Micro-electronic Packages",ongoing investigation. One approach would be to link the Proc. EuroSimE 2004, pp. 53-58.calculated ARE values to actual experiments in which 3. Wang, G., Ho, P.S., Groothuis, S. "Chip-packaginginterface strengths are measured. Another approach would interaction: a critical concern for Cu/low-kbe to take it 'as small as possible' (e.g., the dimension of packaging", Microelectronics Reliability, 45, 2005,the smallest geometric entity in the model, say a via), as pp. 1079-1093.to avoid the strong influence of the surrounding materials 4. Krueger, R., "The Virtual Crack Closure Technique:and/or geometries. On the other hand, to avoid mesh History, Approach and Applications", NASA/CR-dependency, the size should not be too small as in that 2002-211628, ICASE Report No. 2002-10.case, from Equation (6), the number of elements in the 5. Zhao, J-H. Application of the virtual crack closuremesh could become too large. integral method for interface cracks in low-k

integrated circuit devices under thermal load.

5. ConclusionsEngineering Fracture Mechanics, 72, 1361-1382,

5.Conclusions 2005.In this paper, a 3D multi-scale method incorporating a 6. Nemat-Nasser, S. and Hor, M. Micromechanics:

novel failure indicator was presented for analyzing Overall Properties of Heterogeneous Materials.delamination in Cu/low-k bond pads. The multi-scale Elsevier, Amsterdam, 1994.methodology, consisting of a homogenization and 7. Van Gils, M.A.J, Van der Sluis, O., Zhang, G.Q.,localization step combined with periodic boundary Janssen, J.H.J., Voncken, R.M.J. "Analysis of Cu/low-conditions, proved to be an efficient and accurate method k bond pad delamination by using a novel failurethat allows to perform numerical simulations at the global index", Proc. EuroSimE 2005, pp. 190-196.level while takinga into account the details of the local ldx' rc uoIE20,p.1016level 8. Hazanov, S. and Huet, C. "Order relationships forleel boundary conditions effect in heterogeneous bodies

The Area Release Energy method showed that the smlethnherrsnaivvou ",Jralffallure sensitivity Of different 3D structures could be...evaluated efficiently by means of the resulting contour the Mehais9ndPysc-o2Slds0ol14,194maps: a qualitative comparison of the integrity of the p.19-01

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Page 8: [IEEE 7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems - Como, Italy (24-26 April 2006)] 7th. Int. Conf. on

9. Terada, K., Hori, M., Kyoya, T., Kikuchi, N."Simulation of the multi-scale convergence incomputational homogenization approaches."International Journal of Solids and Structures, vol. 37,2000, pp. 2285-2311.

10. Van der Sluis, O., Schreurs, P.J.G., Brekelmans,W.A.M., Meijer, H.E.H. "Overall behaviour ofheterogeneous elastoviscoplastic materials: effect ofmicrostructural modelling". Mechanics of Materials,vol. 32, 2000, pp. 449-462.

11. Fiori, V., Orain, S. "A multiscale finite elementmethodology to evaluate wire bond pad architectures".Proc. EuroSimE 2005, pp. 648-655.

12. Hartfield, C.D., Ogawa, E.T., Park, Y-J., Chiu, T-C."Interface Reliability Assessments for Copper/Low-kProducts", IEEE Transactions on Device andMaterials Reliability, vol. 4, no. 2, June 2004, pp.129-141.

13. Kanninen, M. and Popelar, C. Advanced FractureMechanics. Oxford University Press, New York,1985.

14. Xu, X. and Needleman, A. "Numerical simulations offast crack growth in brittle solids". Journal of theMechanics and Physics of Solids, vol. 42, 1994, pp.1397-1434.

15. Van Hal, B., Zhang, G.Q., Van Gils, M. Peerlings, R."Delamination prediction in stacked back-endstructure underneath bond pads". Proc. ICEPT 2005.

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