SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies

Raul Chipana, Fernanda Lima Kastensmidt Instituto de Informática, PGMICRO

UFRGS Porto Alegre, Brazil

{raul.chipana, fglima}@inf.ufrgs.br

Abstract— Clock distribution networks represent one of the most important signals in a synchronous integrated circuit, this signal may be altered by radiation effects and generate an abnormal behavior in the system. In this work we analyzed two types of clock distribution network using the same circuit to know which of one is more sensitive to radiation threats. Using a case study we compare clock tree with clock mesh. Finally we found that clock mesh topology is more sensitive to radiation effects in comparison with traditional tree distribution. This may occur because clock mesh has a uniform distribution of capacitance and this allows a good distribution of the signal even to transient pulse.

Keywords-component;EXT-CLK; SET; Clock Tree; Clock Mesh; Radiation Effect

I. INTRODUCTION In a synchronous circuit digital design, the clock signal is

the most important signal, because this is used as reference time to each data flow through the system in an orderly way. As vital signal, clock signal must usually travel longest distances, and operate at the highest speed of any signal, either control or data [1]. We are interested in understanding how the clock signal behaves in front to the radiation interference in aerospace. The neutrons present in the atmosphere can interact with the circuit generating secondary particles such as alpha particles, and these particles can ionize the silicon provoking transient pulses. As we know, when alpha particles hit the drain of a transistor at off state, the particle loses its energy creating electron-hole pairs path, this effect may charge or discharge that node provoking a transient voltage pulse [2]. Interferences caused by radiation in aerospace are known as Single Event Effects (SEE) [3]. Consequently, if this transient effect occurs inside a storage element like a SRAM memory it is called Single Event Upset (SEU) or bit-flip, and if the transient effect occurs in a combinational logic it is called Single Event Transient (SET). When SET and SEU are not logically masked, they can provoke errors in the circuit operation [4] [5]. In the present work we give special attention to SET, since clock distribution networks are present in the great majority of combinational logic and wire connections.

Clock networks are becoming also vulnerable to radiation effects because SET may occur at the output node of the clock buffers [6]. After generating a SET, the transient pulse can propagate through the clock buffers and clock gates depending on the width, the amplitude [7], and the size of the

transistor [8]. SET effects can perturb the clock signal generating glitches, jitter [9] and clock skew [10] [13]. Finally the SET may reach one or more registers and change the value of stored data, resulting in a SEU or bit-flip.

Some techniques have been proposed about radiation hardening in clock buffers like a Hardened Dual Port Inverter [10], SEU Hardened Clock Leaf Inverter [11], and TMR Clock Regenerator Circuit [9]. However, these related works do not always consider in their SET evaluation analysis the variety of parameters in the clock network, such as sizes and types of buffers, the real fan-out of each buffer, clock gating and the capacitance and resistance of the paths.

In previous work, simulations have shown that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with low fan-out [8]. Also, simulations have shown that the use of different set of constrains in the clock tree network can modify the SET sensitivity, since the buffer size is directly related with the capacitance of the output.

We also investigated recently the soft-error probability due to SET in the clock tree networks [14]. In that work we performed two types of simulation. The first simulation was based on electrical simulation, which allows calculating the probability of a bit-flip in one register of the circuit generated by a SET on the clock tree. The second simulation was at logical level using ModelSim, which allows to calculate the probability of a bit-flip generate an error in the circuit output. This simulation is performed since some applications can mask the bit-flip effect. This experiment resulted in a set of 17 (4.6%) registers of the circuit that are very susceptible to generate error in functional behavior due to single events transient in the clock tree networks.

With this kind of information about the clock networks, designers can select a mitigation technique to reduce the probability of errors, or change some devices using constrains after analyzed. Also, these results can help the selection of the parameters during the clock tree generation and the placement of the registers according to the SET susceptibility and their functionality in the system. In both previous works, we perform simulations only in clock tree networks because our tool of extraction was limited [8] [14]. Now we can simulate soft-errors on clock mesh networks as well.

In the present work, we analyze how to affect a SET in a digital circuit considering two different clock distribution

2014 IEEE Computer Society Annual Symposium on VLSI

978-1-4799-3765-3/14 $31.00 © 2014 IEEE

DOI 10.1109/ISVLSI.2014.33

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networks. One of them using clock tree and the other using clock mesh. After electrical simulations, we finally obtain an important result: the design implemented with clock mesh is more susceptible to SET in comparison with clock tree.

II. PROPOSED METHODOLOGY TO COMPARE CLOCK DISTRIBUTION TOPOLOGY

The topology of the clock distribution network should be considered in the development of a system. Buffered clock tree, H-trees, clock mesh are commonly used topologies, each one with individual features like latency, power dissipation, skew. But until this point, no one has studied these topologies in radiation environments and compared them. Therefore we develop a method to evaluate the topologies of the clock networks under radiation environment. Our methodology, showed in Fig. 1, consists of extracting the clock network from the synchronous digital layout and performing electrical simulations under SET injections. This simulation allows us to create and compare a profile of each circuit.

The first step of methodology takes the layout files from the circuit synthesized and uses these files to extract the clock networks to Hspice model. A preview version of EXT-CLK was limited to extract clock tree networks [8] but a new version that supports clock mesh is available.

The files used to extraction the clock network were the Design Exchange Format (DEF), Library Exchange Format (LEF) and Layout Versus Schematic (LVS).

Figure 1. Flowchart of the methodology.

DEF file contains logical and physical design data to place and route tools. Logic design data include internal connectivity, grouping information, and physical constraints. Physical information includes placement, orientations, and routing geometric data. Within the DEF file, we can find the

wire connection and also the metal layer used in this connection. Practically, all information use coordinates in micrometers.

LEF files contain library information for a class of designs. Library data includes layer, via, placement, and macro cell definitions. The LEF file is in ASCII representation using the syntax conventions. A technology LEF file contains information for layers such as sheet resistance and capacitance per square in a specific unit that helps to calculate the wiring conductor model.

LVS file. Layout vs. Schematic is a class of verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design. LVS checking software recognizes the shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. LVS file contains the netlist of every cell used in the integrated circuit. DEF and LEF are in ASCII form [12].

Clock mesh typically use multilevel structure to drive the clock signal. The multilevel meshes can include top-level chain, global mesh and local distribution as shown in fig. 2. The top-level chain is a cascaded buffer chain from the root to the first level using pre-drivers. The chains can be used to supply a suitable input transition or to pad the mesh with extra insertion delay. The goal of the global mesh is to distribute a signal across the entire clock domain with good insertion delay and skew control. The global mesh consists of zero or more pre-drive stages, followed by a single final-drive stage. The final stage always drives a single final global mesh net. This mesh net can connect directly to the clock input pins, or there can be an additional local distribution. Local distribution is an optional section in which multiple small trees distribute the signal of the mesh net to individual flip-flop or memory inputs. Local distribution significantly reduces the loading in the final mesh stage, allowing to reduce the overall power consumption.

EXT-CLK is a tool that extracts the clock network to netlist HSPICE. This tool was developed in Bash command line in Linux environment. The algorithm used in EXT-CLK identifies paths that belong to clock networks in the DEF file of the design. The pathfinder algorithm starts from the clock source to next cell, through different cut layer connections. When the path splits, the coordinate is saved and the algorithm continues searching through one of the paths. When the algorithm finds a cell, the saved coordinate is recovered and continues the search for another cell. This strategy is used until to find all cells connected by the same net. If there are not split, then we must to see the kind of cell. In clock networks there are only three options of cells: buffer, clock gate or register. If the cell is a register then the search is complete. If the cell is a buffer or clock gate then we going take the output of that cell and start searching cells again in a new path. That was a simple way to explain this algorithm applying for clock tree, but for clock mesh it is not enough.

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Figure 2. Clock Mesh driven by a buffered global clock tree.

The mesh topology is build using horizontal branches and vertical trunks in two adjacent layers. A special algorithm was developed to identify the mesh (grid) inside the DEF file. Then, the algorithm searches the mesh, which is describes by a set of coordinates. With these information we can obtain the CRC model of the entire mesh but it is not suitable because we need to connect others paths related to local tree. Root initiation of local trees is not explicitly connected to the mesh (reading the DEF file) but we know the coordinate of each root. Then the algorithm take each coordinate and calculate if that coordinate is within the rectangle of some branch or trunk of the mesh. Knowing where root are connected we can make the electrical model of each path together with the mesh. For example, Fig. 3 represents the electric model of the mesh (without capacitors for better illustration at right side). CG and FF are clock gates and flip-flop respectively.

Figure 3. Electric model of mesh.

We develop a subroutine to perform the CRC model for each cut metal layer used as wire connection. CRC or pi is an

electrical model of the wire connection. CRC is a capacitor-resistor-capacitor model that simulates basic features of the wire. To calculate the value of the segment resistors and segment capacitors for each segment of wire we need information about cut layer and dimensions of the connection. The segment resistance of a wire can be defined in (1), where RPERSQ value specifies the resistance per square of wire, in ohms per square.

segment resistance =RPERSQ x wire length/wire width (1)

RPERSQ and wire width are taken from the LEF file. The wire length is calculated from the difference between the coordinates of each segment of wire inside DEF file. The segment capacitance is defined in (2)

segment capacitance = (CPERSQDIST x segment width x segment length) + (EDGECAPACITANCE x 2 (segment width + segment length)) (2)

The CPERSQDIST value specifies the capacitance for each square unit. EDGECAPACITANCE value specifies a floating-point value of peripheral capacitance. The EDGECAPACITANCE value is used only if you set layer thickness, or layer height, to 0. CPERSQDIST and EDGECAPACITANCE are features each cut metal layer and are also found in LEF file. These values are in picofarads per square micron. Segment width and segment length represent the wire width and wire length respectively.

The structure of the netlist after extraction start with the statement of logic cell, block 1 in Fig. 4. These statements describe all cells used in the circuit and part of these cells belongs to clock networks (buffers, clock gates, registers). These cells are described at transistor level and are within the LVS file. The second statement is about the net of connections. Layout design has thousands of wiring conductors used to connect different cells. The net consists of several segments of cut layer at different levels. We will

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consider a net like a component, which joins the cells by the same node, as shown in Fig. 5. In the case of clock mesh, we consider the mesh as a single element, which joins others nets. The next part of the netlist is the statement to call logic cells, (block 3 in Fig. 3.) this block calls the cells that belong to clock network. “Call a cell” means to place the cell in specific position towards the network.

Logic cell subcircuits statement

Nets & mesh subcircuit statement

Calling Logic cell

Calling Nets & Grid

Initial condition & measure statement

Defining injection spots &

Type of simulation

1

6

5

4

3

2

Figure 4. Blocks of netlist generated (file format) by EXT-CLK.

Figure 5. Representation of a net.

The nets are elements that have a specific place to connect to cells. The statements to call logic cells and nets are related because logics cells are connected by nets, then each net is placed between two or more cells and each cell is placed between two nets (Fig. 5). Certainly, we consider only the clock pin of the cells to make the connection with the net.

Another consideration from the point of view of simulation, Hspice can take long time to simulate a complex circuit whether no initial condition is used (block 5 in Fig.

4). Initial conditions are values used as part of solution in initial execution. EXT-CLK generates the initial condition value for each node to improve the simulation.

On the other hand, note that circuits have many registers (hundreds). As consequence, the verification of all registers is very complex. Then, EXT-CLK generates the measure statements into the netlist in order to deliver a file with results.

Blocks from the number 1 to 5 will be permanent for all simulations, and only the block 6 in Fig. 4 will change to define the type of simulation and setup the amount of charge to be injected. Also in block 6 we define the spots where the ion impact will be simulated, it can be one or more points.

Figure 6. Sample of netlist HSPICE generated by EXT-CLK.

An example of the result of EXT-CLK is shown in Fig. 6. Where the asterisks are used to comment lines. For example, the first include command set the file of CMOS technology in 65mn, and the second include command is a statement of the subcircuit of cells exactly like a block 1 in Fig. 4.

Our case of study is SRAM arbiter circuit. The SRAM arbiter is the interface between the logic modules of a Gigabit Ethernet Switch and an external zero-bus turn around (ZBT) SRAM memory. SRAM arbiter has been designed in 65 nm process using Encounter (version 8.1) from cadence. We synthesized two designs of the circuit, one of them using clock tree networks and the other using clock mesh networks. Finally, we performed simulations of SET and generated a profile for each one.

III. CLOCK TREE PROFILE After using the tool for extraction, we get the profile of

the clock tree network using Hspice. This profile was created

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by 140 interactions, and we modeled the SET pulse as source of current with a double exponential function [15], where the width of pulse is approximately 70 picoseconds and the current amplitude is swept from 1mA up to 15mA increasing by 100uA. All registers were set to store 1, this means, in eventual SET effect, the register can change the value stored from 1 to 0 and we take this event as a bit-flip. In each interaction we take the percentage of failed registers to create the profile of the clock tree.

The electrical simulations were performed using 65 nm CMOS technology of Predictive Technology Model. The charge produced in the clock tree was computed as the integral of the current over the time, therefore the experimental results are in terms of Coulomb (C). The SET injection is performed in the output of the first buffer from the clock source until it generates a bit-flip in one of the 367 registers. Fig 7 shows the layout design of clock tree networks and, Fig 8 shows the profile resulted from the clock tree simulations.

Figure 7. Clock tree network layout.

Figure 8. Clock tree networks profile.

IV. CLOCK MESH PROFILE Clock mesh typically relies on multiple buffers or

inverters working in parallel to drive a given net in the pre-drive and final-drive stages. Then, implementing a clock mesh involves various tasks, such as inserting drivers, placing and fixing the drivers, creating mesh route, and so on. The Encounter clock mesh includes three major implementations: Synthesis, mesh routing and wire

trimming. The synthesis command implements the clock mesh according to the current specification, by inserting and placing buffers, and creating mesh special routes as needed. The routing command uses the native router (NanoRoute) to complete detailed routing connections for driver and flip-flop inputs, top-level cascade chains, and local trees. Finally, the trimming command removes unused portions of the mesh trunks and branches, and eliminates antenna violations. As consequence, our clock mesh design has a top-level chain with two pre-driver buffers, a global mesh with 4 pre-drive buffers, 16 final-driver buffers and 4 trunks by 4 branches with 22um of pitch. The local trees connected on the grid have 49 clock gates to drive 367 flip-flops.

After the extraction of the clock mesh using EXT-CLK, we generate a profile performing 151 interactions from 1.258 mA up to 1.273 mA increasing by 0.1 uA. The electrical simulation was developed taking the same consideration of the clock tree, i.e., the SET injection is performed in the output of the first buffer from the clock source. Fig. 9 shows the clock mesh layout in encounter environment and, Fig. 10 shows the profile of the simulation.

Figure 9. Clock mesh layout.

Figure 10. Clock mesh profile.

V. COMPARISONS AND DISCUSSION We synthetized two circuits from the same design using

two different clock networks. The first circuit was designed with clock tree network and the second circuit was designed using the clock mesh network. After clock extractions and electrical simulations in both circuits, we finally obtained an

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important result: the design implemented with clock mesh distribution is more susceptible to SET than clock tree. Fig. 11 shows the same distribution of charge for two types of networks in the same scale. Clearly, we can see the difference of profiles, clock mesh reaches the 100% of fails at just 200 fC in almost one step.

Figure 11. Profile comparison between clock tree and clock mesh.

Clock tree has a completely different profile, clock tree starts fails at 620 fC with 9% of fail registers and increase step by step up to 100% of fails with 1100 fC. This means that in an eventual impact of heavy ion, in these circuit, over the first buffer of the clock network, the circuit with clock mesh will fail before the circuit with clock tree. The immediate question is why? Looking inside, the structure of the mesh has a little clock tree (top level chain and global mesh without the grid, Fig. 2) that ends at 16 final-driver buffers with the same properties. Every output of these buffers joint at the mesh as part of clock mesh distribution. Then, the clock signal is radially distributed from the center of the chip die to the periphery of the IC. From the mesh, the signal is distributed to all registers. The mesh, which was usually fairly uniform over the chip, contributes to a grid wire capacitance that is uniform over the chip, but the clock density from the local clock blocks is often larger, and is remarkable non-uniform. On the other hand, clock trees have a non-uniform capacitance, low latency, minimal wiring track usage, and the potential for very low skew.

The mesh has the property to reduce local skew by connecting nearby points directly. Even with large process variations that cause significant skew across the chip, the resulting local skew is relatively small, because it has uniform distribution of capacitance. Then, low interconnect resistance and high capacitance associated with the mesh wire structure allows a perfect propagation of the clock signal but at the same time these features can be turned a great disadvantage when a transient pulse takes this way, as shown in our simulations. Maybe if the clock mesh uses hardened devices can improve the fault tolerance.

We cannot say that this particular result extends to all circuits. But the methodology can easily be applied to other circuits to compare the sensitivity between topologies. This information can help the designer to change some devices or

use selective mitigation techniques before the manufacturing process.

ACKNOWLEDGMENT My sincere thanks to Instituto de Informática. PPGC,

PGMICRO, UFRGS. This work was supported in part by the Brazilian Agencies CNPq and CAPES.

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