Modeling and Analysis of DC-link Voltage for Three-phase Four-wire Two-stage Micro-inverter

Frank Chen Qian Zhang Ahmadreza Amirahmadi Issa Batarseh Department of Electrical Engineering

University of Central Florida Orlando, USA

Frankchen@eecs.ucf.edu

Abstract—DC-link voltage control plays a key role for two-stage micro-inverter application. Modeling &analysis of dc-link voltage is investigated in this paper. The first-stage circuit employs transient maximum power point tracking method to realize fast MPP tracking without causing output distortion and dc-link variation. In order to keep dc-link voltage constant, injecting current to grid varies with the output of a positive feedback of dc-link voltage regulator at steady situation. Two disturbances to cause dc-link constant are investigated and small signal model of dc-link voltage is also built while considering dynamic response. Followed by the small signal model of dc-link voltage, the dc-link capacitance is also calculated. The performance of dc-link voltage control is verified by experimental results based on a 400 watt two-stage three-phase four-wire prototype with grid-connected, the input voltage from 35V to 60V, dc-link voltage 400Vdc and AC output voltage 110V RMS.

I. INTRODUCTION

Due to environmental concerns such as climate change, fossil fuel exhaustion, and carbon dioxide reduction, Photovoltaic (PV) will be played more and more role in renewable energy in recent years [1]. Micro-inverter, directly connecting a single PV panel also called Module Integrated Converter, has been getting more and more attention from government, academia, and industry for future solar PV deployment due to its remarkable merits: (a) Easy modularization and scalability; (b) Elimination of single point failure; (c) Simple installation and maintenance; (d) High efficiency and low cost. The micro-inverter with its high frequency transformer can be grouped into three architectures based on the DC-link configurations: DC-link, pseudo DC-link and high frequency AC [2] [3]. Due to the fact that two-stage micro-inverter can deal with the reactive power in the DC/AC stage, the configuration with dc-link is more popular at the current micro-inverter market. Electrical capacitor is widely used for single phase two-stage micro-inverter to keep the power balance between input and output due to the influence of double line frequency [4]. As we known, reliability is a big issue for micro-inverter application if electrical capacitor is used. Thus, film capacitor is applied to improve the life of the system while three-phase four-wire DC/AC converter is employed in the second stage. This paper focus on the

investigation of dc-link based on two-stage three-phase micro-inverter as shown in Fig.1 while considering two disturbances from PV panel generator and grid side.

Fig.1 Overall diagram for three-phase grid-tied two-stage micro-

inverter

II. DESCRIPTION OF DUAL-STAGE MICRO-INVERTER

A. Description of Dual-stage Architecture In order to provide galvanic isolation, various isolated converters for high step up applications have been proposed. In general, the topologies with galvanic isolation suitable for this application can be categorized into two groups: single switch topologies and multi-switch topologies. Recently, the LLC resonant topology has become attractive due to its desirable characteristics such as high efficiency and natural ZVS/ZCS commutation [5]-[8]. Therefore, a full bridge LLC resonant converter is employed in the first stage to achieve high efficiency and track the maximum power point of each PV panel. The proposed soft switching technique shown in Fig.2 simplifies the inverter topology and reduces the cost since it does not require any auxiliary components [9]. The body capacitors of the main MOSFETs and the output inductor L1 are combined to form a resonant circuit. The inductor current is intentionally bi-directional within a switching cycle to generate ZVS conditions during commutation. Meanwhile the average inductor current is controlled to produce a sinusoidal current in L1. The proposed soft switching technique is suitable for MIC applications where the switching losses are usually dominant. Based on the above, Figure 2 shows the proposed high efficiency MIC architecture with both-stage zero voltage switching consisting

978-1-4799-2325-0/14/$31.00 ©2014 IEEE 3000

of a full bridge LLC resonant dc-dc step up converter and three phase four-wire soft switching dc-ac converter. The detail operating modes in the three-phase four-wire DC/AC converter is presented in [9].

UBus

Lr

Cr

Lm

Np Ns

S1 S2

S3S4

D1

D2

C1

Tr

S7

S8 S10 S12

S9 S11

L1 L2

CaCbCc

UgaUgbUgc

CS8 CS10 CS12

CS11CS9CS7

First Stage: LLC resonant DC-DC Converter Second Stage: Three-Phase ZVS DC-AC Converter

C2

i1a

i1b

i1c

i2a

i2b

i2cc

b

aUa Ub

Uc

UPV

Fig.2 Two-stage three-phase four-wire grid-tie micro-inverter PV system

B. System Control Description An overall control diagram for two-stage three-phase four-wire MIC PV system is shown in Fig. 3. The voltage (Upv) and current (Ipv) of PV panel are both sensed continuously to calculate the instantaneous power. The MPPT algorithm is based on variation of the instantaneous power of PV panel that changes the switching frequency of the LLC resonant DC-DC converter to track the maximum power output. In order to keep power balanced between the generator (PV panel) and the grid for two-stage MIC system, a bus voltage regulator is used to keep the voltage constant. The Bus voltage is regulated by controlling the amount of current injected into the grid. For example, if the irradiance is increasing, the bus voltage increases because the DC-DC stage is running with MPPT. When UBus is greater than U*

Bus, the output value of the DC link regulator (Id

*) increases and the inverter stage injects more current into the grid. Conversely, if the irradiance is decreasing, the inverter stage reduces the amount of current injected into the grid. Low THD is achieved by sensing the injected grid current via d/q transformation and causing it to follow the reference current Id

*. If the power factor is assumed to be unity, the reactive current will be zero after d/q transformation (no phase shift). As described in previous section, the bidirectional current through the high frequency inductor (L1) is also sensed as a part of the internal current loop to achieve ZVS and improve the dynamic response of DC/AC stage.

Fig. 3 Overall control diagram of a two stage three-phase grid-tie

inverter system

III. AVERAGE MODEL OF THREE-PHASE FOUR-WIRE INVERTER WITH LCL FILTER

The schematic of a three-phase four-wire voltage source inverter (VSI) connected to the grid through an LCL filter is shown in Fig. 4. The series resistances of the inductors (L1&L2) have been neglected in order to simplify the derivation of average model. An average model of three-phase four-wire DC/AC converter which may be obtained by neglecting the high frequency components of both the dc voltage and the ac phase currents. According to Kirchhoff’s current &voltage law, the differential equation to illustrate current and voltage as shown in Fig. 4 can be expressed by:

Fig. 4 Three-phase four-wire DC/AC grid-connected converter

I RL I RL I L U UL D U·L Γ (1)

I RL I RL I L U L U (2)

U I I (3)

UB I (4)

Where, I I U U

D= Γ 1 1 1

In the steady state, the grid phase currents i2a, i2b, and i2c are controlled to be sinusoidal and in phase with the corresponding grid phase voltages Uga,Ugb and Ugc which can be expressed as: cos coscos (5)

Where Um and ω are the amplitude of the phase voltage and angular frequency of the power source, respectively. The model in the stationary coordinates can be transformed into a synchronous reference frame by the transformation matrix T (Park’s transformation) as follows:

3001

cos cos cossin sin sin (6)

After transformation into the synchronous three-phase reference frame, the equations of the averaged model of three-phase four-wire grid connected inverter are expressed by (7)-(9) [10]. I WI RL I RL I L U L U (7) I RL I WI RL I L U L U (8) ωU (9)

Where W 0 0 , U UB D

From (7) to (9), combing with the small signal perturbation, the mathematical model can be represented by a linear time invariant state space small signal mode of the form

X(t) A X(t) B U(t) F (t)Y(t) C X(t) D U(t)

δ⎧ = ⋅ + ⋅ + ⋅⎨

= ⋅ + ⋅⎩ (10)

Where T

1d 1q 2d 2q cfd cfqˆ ˆ ˆ ˆ ˆ ˆX i i i i u u⎡ ⎤= ⎣ ⎦

dg dqˆ ˆU u u⎡ ⎤= ⎣ ⎦

gd gqˆ ˆu uδ ⎡ ⎤= ⎣ ⎦

X is the normalized state vector selected as

1d 1q 2d 2q cfd cfqˆ ˆ ˆ ˆ ˆ ˆI , I , I , I , U , U , U is the normalized inverter

output voltage, δ is the normalized grid voltage, and Y is the normalized injected grid current in the dq refrence frame. A,B,C,D and F are matrices with appropriate dimensions given in below.

d d

1 1 1

d d

1 1 1

d d

2 2 2

d d

2 2 2

f f

f f

R R 10 0L L L

R R 10 0L L L

R R 10 0L L L

AR R 10 0L L L

1 10 0 0C C

1 10 0 0C C

ω

ω

ω

ω

ω

ω

⎡ ⎤− −⎢ ⎥⎢ ⎥⎢ ⎥− − −⎢ ⎥⎢ ⎥⎢ ⎥

−⎢ ⎥⎢ ⎥=⎢ ⎥

− −⎢ ⎥⎢ ⎥⎢ ⎥

− −⎢ ⎥⎢ ⎥⎢ ⎥

− −⎢ ⎥⎢ ⎥⎣ ⎦

T0 0 1 0 0 0C

0 0 0 1 0 0⎡ ⎤

= ⎢ ⎥⎣ ⎦

D=0

T

1

1

1 0 0 0 0 0L

B10 0 0 0 0L

⎡ ⎤⎢ ⎥⎢ ⎥=⎢ ⎥⎢ ⎥⎣ ⎦

T

2

2

10 0 0 0 0L

F10 0 0 0 0

L

−⎡ ⎤⎢ ⎥⎢ ⎥=

−⎢ ⎥⎢ ⎥⎣ ⎦

IV. SMALL-SIGNAL MODEL OF DC-LINK CAPACITOR

The system between DC/DC stage and DC/AC stage is decoupling due to the role of DC link capacitor, which simplifies the controller design for both stages. Electrical capacitor is usually used in the dc link, but the life of electrical capacitor is a major concern. Because of three-phase DC/AC converter in the second stage, the value of the dc-link capacitor should not be choosing very large based on the power rating specification of MIC. Thus the reliability of whole system will be significantly improved if the electrical capacitor of DC-link is replaced by a film capacitor. Though the capacitance value of DC-link based on the Qualitative Analysis is not large in three phase balance system, the condition of grid should be analyzed and considered while MIC is connected with grid. How much capacitance does the DC-link capacitor need is determined by many factors, such as the voltage variations of capacitor, grid voltage dips &surges and response time for disturbance? Generally, these factors can be classified into steady conditions and dynamic conditions of MIC according to the specification. Thus, small-signal model of DC-link capacitor and DC-link controller design are discussed in this section.

A. Small-signal Model of the DC-link Voltage Loop with Generator and Grid Disturbances

Considering the instantaneous input-output power balance for the grid converter in a synchronous rotating dq frame under a non-loss condition, the following equation is derived [11]:

(11)

Assuming that DC/DC converter of the previous stage is injecting a current iBus(t). The small-signal linearization leads to

2 2 (12)

If the purpose is to control the DC voltage UBus through the id current component, the transfer function / can be found while the other perturbations have to be considered null.

3002

(13)

Then we get this equation: (14)

In the lapalace domain, , and the steady state equivalent resistance / , thus the equation can be further simplified as(15) if we assume √3 that has been indicated the DC link voltage cannot be lower than than this value in order to allow current controllability.

√ (15)

On the contrary, the influence of a small signal perturbation originated by the power stage connected to the PV panel has to be calculated through .

0 (16) Simplified as

(17)

Finally, the influence of the grid voltage perturbation on the DC link voltage is also investigated, the transfer function / has to be derived, assuming 0 0 and 0

(18)

Where √ √ (19)

The DC voltage loop is described with the two disturbances highlighted from (15) to (19) as shown in Fig.5. The plant of voltage control loop, generator and grid disturbances has a pole in the right side of the s plane and may cause system unstable.

Generator disturbance

iBus

Ugd

Grid disturbance

Dc-voltage loop plantDc-voltage PI Current loop

UBus_ref UBusi2dref

Fig. 5 Small-signal model of the voltage control loop, generator and

grid disturbances

B. DC link controller design

As shown in Fig. 3 about overall control diagram, MPPT algorithm is employed in the first stage which is beyond the scope in this paper, thus we didn’t discuss it [14]. Followed by the illustration of previous sections, Fig.6 shows control block diagram of the multiloop controller in the d-axis according to system control description in the previous section. From Frig. 6, it can be seen that the converter side inductor current (i1d) is controlled by the hybrid current modulator in the inner current loop, which is helpful to achieve fast dynamic response in the whole system. Followed by the inner current loop, grid current i2d is also sensed to tracking the referenc i2dref by PI controller Gc(s). As shown in Fig. 3, the first stage only runs to traching maximum power from PV panel, therefore, the bus voltage (output voltage of first stage DC/DC converter) should be controlled by the second stage (DC/AC stage) to keep bus voltage constant. Bus voltage controller is employed here and contrller design is given in detail.

Fig.6 Block diagram of the multiloop controller

The outer voltage control loop regulates the bus voltage at the reference value by setting the grid current reference as shown in Fig.7. The structure of Fig.7 has an inner current control loop and an outer bus voltage control loop. It is common design to select the current controller which is much faster than the bus voltage controller. Therefore, these two controllers are designed independently and their interaction is neglected, such an assumption is valid and workable for three-phase four-wire system.

Fig.7 Outer bus voltage control loop diagram

As shown in Fig.7, the open loop transfer function of bus voltage loop is expressed by

2dBus _ open V CC v Bus/iG (s) G (s) G (s) H (s) G (s)= ⋅ ⋅ ⋅ (20) Where

CCdelay

1G (s)1 3 T

=+ ⋅

; V

1H (s)200

= ; ivV pv

kG (s) ks

= +

Fig. 8 shows magnitude and phase margin of bode diagram with the open loop transfer function of bus voltage loop. As

3003

shown in Fig.8, the phase margin is more than 800 while the crossover frequency is selected as 100Hz.

Fig. 8. Controller design of bus voltage loop

V. CAPACITANCE CALCULATION OF DC-LINK CAPACITOR

Referring to the small-signal model of the DC-link capacitor shown in Fig. 5, the DC-link capacitance is determined by grid disturbance and generator disturbance. Because the MPPT iteration time is relatively slow, the DC-link capacitance is only calculated based on grid disturbance of an unbalanced three-phase system in this paper. Asymmetrical faults lead to drops in one, two, or three phases with not all phases having the same drop. The resulting voltage drops and phase-angle shifts depend on a number of factors. The different types of voltage sags present in a generic distribution system are summarized in Table I [12], [13].

TABLE I THREE-PHASE UNBALANCED DIPS DUE TO DIFFERENT FAULT TYPES AND TRANSFORMER CONNECTIONS

The voltage variations on the DC-link capacitor with type D dips for a three-phase unbalanced system is investigated as follows: The equation of output voltage and current for each phase can be expressed by: √2 ∆ sin√2 sin √2 sin (21)

√2 sin√2 sin√2 sin (22)

Where Um is the RMS AC output voltage, Im is the RMS AC output current, and ∆U is the voltage dip. From the output

power of the grid side, we can get the instantaneous power of three-phase system:

(23)

Substitute (21), (22) into (23), then simplify it: 3 √ ∆ √ ∆ cos 2 (24)

Assuming no power loss in the DC-DC stage, we get the instantaneous generated power of PV panel that can be expressed by .

Fig.9. Simplified block diagram of two-stage MIC

Then based on Fig.9 we get:

(25)

Combining (24) and (25), the energy stored in DC-link capacitor can be calculated under type D dip condition: 3 √ ∆ √ ∆ cos 2 26

Alternately, the energy stored in DC-link capacitor can also be expressed by (27)

,2 ,22 ∆ (27)

Substitute (26) into (27), and we find 3 for three-phase balanced system, the DC-link capacitance is represented by (28) after simplification: 22 ∆∆ (28)

For a maximum output power of 400 watts, the power rating of each phase is 133 watts. The DC-link voltage (UBus) is selected as 400V with voltage ripple (∆UBus= 20V) and voltage dip (∆ 40 ). The capacitance is 35.3uF based on the calculation in (28) with a line frequency f=60Hz and Im=1.2A.

VI. EXPERIMENTAL RESULTS

A three-phase MIC prototype with two-stage ZVS is built, according to the specification: input voltage from 35V to 60V, maximum out power 400W and AC grid voltage 110Vac. The renewable source is a PV panel, ASP-400M from Advanced Solar Photonics. Because open circuit voltage of ASP-400M is less than 60V, 75V MOSFETs with low Rds (on) is used in full bridge LLC resonant DC-DC converter. The second stage is a three-phase four-wire voltage source inverter that connects the dc bus to the grid through an inductance of 600uH. The dc-bus voltage reference is 400V and the grid voltage peak value is 110√2 . Fig.10 shows the

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dynamic response of the DC/AC stage to the step change in the grid voltage with two-stage operation.

Fig.10. Dynamic response to a step change in the grid voltage from

120V to 80V

Fig.11. Center points iteration MPPT algorithm in the DC-DC stage

Fig.11 shows the CPI MPPT algorithm’s performance in the LLC resonant DC-DC stage [14]. The experimental waveform of overall system connected with grid is shown in Fig.12. The regulator of DC-link is employed to keep bus voltage constant while CPI MPPT algorithm is running in the first stage. As shown in Fig.12, the injecting current (green channel) to grid is gradually increasing with the process to tracking the maximum power of PV panel. As seen in Fig.12, the dc-link voltage ripple is very small while the irradiance of PV panel is increasing.

Fig.12. Experimental waveform of overall system with grid-

connected

VII. CONCLUSIONS A DC-link capacitor plays a key role for the dual stage PV micro-inverter system; the small signal model of dc-link capacitor is derived in this paper while two disturbances are considered. Based the small signal model, the dc-link capacitor’s value is calculated under the condition of voltage dips type D. According to the calculation, the film capacitor (35uF) can be used that will extend its life time, eventually improve the reliability of the whole prototype. A DC link PI controller is employed in the current dual-stage prototype; and experimental results verify the capacitance calculation of dc-link.

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