VerticFabri

Xin Zhao, Jianqiang Lin, ChristoMicrosystems Technology Laborato

Emai

Abstract Vertical In0.53Ga0.47As Gate-all around (

(NW) MOSFETs fabricated by a top-dowdemonstrated experimentally for the fifabrication process features a new III-V dcapable of sub-20 nm diameter NWs withgreater than 10. It also includes a digital econtrollably reduce nanowire diameter and damage. With a channel length Lch=80 nm anwe obtain a transconductance of 730 μS/μmnm diameter NW MOSFET. The digital ettransconductance by 20% and improves tcharacteristics of the devices. In terms transport and short-channel effects, our MOSbest vertical nanowire devices fabricatedtechniques.

Introduction

Recently, InGaAs has emerged as a promaterial candidate for future CMOS appliGAA nanowire MOSFET is the device aultimate scaling potential [2]. A verticstructure uncouples gate length scaling and fAs a result, device density goals can be rbetter short-channel effects and performancMOSFETs, FinFETs or lateral NW-FETvertical channel III-V MOSFETs havdemonstrated through bottom-up fabrica[3-6]. This approach is not considered to beas Au particles are used as seeds [4] or difepitaxial processes are utilized [3, 5]. In thideveloped a top-down fabrication process fvertical channel GAA NW-MOSFETs thatnovel III-V etching technology. We deMOSFETs with diameter (D) down to performance comparable to the best devicebottom-up techniques.

Fabrication Process

Fig. 1 shows a schematic view of thMOSFETs fabricated here. The process flow

cal Nanowire InGaAs MOSFETs icated by a Top-down Approach

opher Heidelberger, Eugene A. Fitzgerald, and Jeories, Massachusetts Institute of Technology, Cambridge, Ml: xinzhao@mit.edu, Phone: 1-857-756-6001

(GAA) nanowire wn approach are first time. The dry etch process h an aspect ratio tch technique to remove dry etch nd EOT=2.2 nm,

m at 0.5 V in a 50 tch increases the the subthreshold

of balance of SFETs match the d by bottom-up

omising channel cations [1]. The

architecture with cal NW device footprint scaling. reached with far ce than in planar s [2]. To date, ve only been

ation techniques e manufacturable fficult to control s work, we have for In0.53Ga0.47As t is based on a emonstrate NW

30 nm and a es fabricated by

he InGaAs NW w is described in

Fig. 2. The starting heterostructugrown by MOCVD on an InP wconsists of 80 nm undoped Inbetween two n+-In0.53Ga0.47As conta

Device fabrication begins withformation by e-beam lithography uRIE process utilizing BCl3/SiCl4/AIndium-containing compounds difficult to etch [7]. This chemistrydevices [7, 8] but its potential for nwith high aspect ratio has not been (a) shows a D=20 nm NW with an by this technique. It features a smovertical in the top ~50 nm. The foocommonly observed in InGaAs drhere. This can be improved t

Fig. 1 Schematic of device structure lististarting heterostructure.

o HSQ mask definition o Nanowire formation bo Digital etch o ALD 4.5 nm Al2O3 gao Sputter 40 nm W gateo Gate metal patterningo Gate/top electrode iso

planarization and etcho Contact via opening bo Sputter Mo as contacto S/G/D pad formation

Fig. 2 Process flow for vertical GAA In

esús A. del Alamo MA 02139, USA

ure (shown in Fig. 1) is wafer. The active channel n0.53Ga0.47As sandwiched act regions.

h mask definition for NW using HSQ. A novel ICP

Ar has been developed for which are notoriously

y has been used for optical nm-scale feature formation

recognized before. Fig. 3 aspect ratio of 10 defined ooth sidewall that is very oting and trenching that is ry etch [9] is also present through further process

ng design parameters and

by EBL by dry etch

ate dielectric e metal g olation by h back (2 times) by dry etch t metal

nGaAs NW MOSFET.

IEDM13-69528.4.1978-1-4799-2306-9/13/$31.00 ©2013 IEEE

optimization. The devices fabricated in this to a depth of 290 nm so as to ensure a unifoover the intrinsic channel region. Althoughused, this dry etch process can be apheterostructures. Fig. 3(b) shows a 20 nm InGaAs/InAlAs/InP heterostructure with no

Our process proceeds with a digital etch the NW sidewalls. This consists of a self-limoxidation/diluted H2SO4 sequence that redunanowire diameter by about 2 nm per cycle.InGaAs NW before and after 10 cycles of dshape is almost unchanged and the sidewdecreased. After H2SO4 cleaning, 4.5 n(EOT=2.2 nm) is deposited on the sidewallsW gate is immediately sputtered. Spin-on applied (1 hr baking at 350oC) and etchedoverlap between the gate and the top n+ regi10 nm. Fig. 5 shows a SEM image of a devin the process (SOG removed). A second etis used to isolate the gate metal from the toAfter vias are opened, 40 nm Mo is sputteremetal. The process ends with lift-off of Ti/A

Fig. 4 D=50 nm InGaAs nanowire (left) reduced tafter 10 cycles of digital etch.

Fig. 3 (a) 20 nm diameter nanowire with an aspect ratfabricated by RIE. (b) Dry etched 20 nm fin structureheterostructure containing InGaAs/InAlAs/InP (right)

work are etched orm cross section h only InGaAs is pplied to III-V fin profile in an notching.

(DE) to smooth miting O2 plasma uces the InGaAs Fig. 4 shows an digital etch. The

wall roughness is nm ALD Al2O3 s. A 40 nm thick

glass (SOG) is d back until the ion is reduced to vice at this stage tch back process

op contact metal. ed as top contact u S/G/D pads.

Results and DiAll devices have a channel len

by the undoped InGaAs layer thickelectrical characteristics of a single As is common, Id and gm are norcircumference (πD). The output chexcellent saturation at low Vds witΩ) at Vgs=1 V. A peak gm of 28Vds=0.5 V. Subthreshold swing of 1200 mV/dec at 0.5 V are obtainewith further surface treatment anDIBL is 195 mV/V. The gate leakagthroughout the measurement rangecurrent measurement are observedsingle nanowire nature of this devic

0.0 0.1 0.2 00

5

10

15

20

I d (μ

A)

Vds (V)

Vgs=-0.6 V to 0.8 V in Ron=759 Ω.μm (at Vgs

Lch=80 nmD=30 nm

Fig. 5 SEM imagafter 1st planarizaand dielectric remregion and the nanowire are wrn+ region is exproughness on ththe erosion of W

Fig. 6 Output characteristics of a DMOSFET.

Fig. 7 Subthreshold characteristics of

-0.6 -0.4 -0.2 0.0

10-8

10-7

10-6

10-5

V

I d (A

)

Vgs(V

Vds=0.5Ig< 10-9 A

DIBL=195 mS(Vds=0.05VS(Vds=0.5V)=

o D=30 nm (right)

tio greater than 10 e (left) in a III-V ).

iscussion ngth of 80 nm. This is set kness. Figs. 6-8 show the D=30 nm NW MOSFET.

rmalized by the nanowire haracteristics demonstrate th Ron = 759 Ω⋅μm (8062 80 μS/μm is extracted at 145 mV/dec at 0.05 V and d. This can be improved d proper annealing [10]. ge current is below 10-9 A . Fluctuations in the drain that are attributed to the ce [11].

0.3 0.4 0.5)

0.1 V step=1 V)

0

50

100

150

200

Nor

mal

ized

I d (μ

A/μm

)

ge of a D=30 nm device ation and etch back (SOG moved in BOE). The intrinsic

bottom n+ region of the apped around by W. The top

posed for ohmic contact. The e ground plane is caused by in BOE.

D= 30 nm InGaAs single NW

f the device shown in Fig. 6.

0.2 0.4 0.6

Vds=0.05V

V)

V

mV/VV)=145 mV/dec=200 mV/dec

10-7

10-6

10-5

10-4

Nor

mal

ized

I d (A

/μm

)

(b) (a)

IEDM13-696 28.4.2

Electrical properties of a single nanowire device with D=

50 nm are shown in Figs. 9-11. The electrostatics are worse than D=30 nm device, as evidenced by increased S (210 mV/dec at Vds=0.05 V) and DIBL (360 mV/V). However, Ron is reduced by a factor of 4 and a high gm,pk of 730 μS/μm at Vds= 0.5 V is achieved. Ron is believed to be dominated by contact resistance of the top n+ region due to the small contact area. The level of current fluctuation is also reduced as the nanowire diameter widens.

The impact of digital etch can be appreciated in Fig. 12

that shows the subthreshold characteristics of D=40 nm devices with and without digital etch (output characteristics of the device without digital etch shown in Fig. 13). The starting NW diameter is different so that after digital etch of one of them, both final diameters are identical. The digital etch improves the interface quality as evidenced by a reduction in S from 220 mV/dec to 180 mV/dec. Interestingly, DIBL is not affected. However, the threshold voltage Vt (defined at 1 μA/μm at Vds=0.05 V) shifts positive by about 0.1 V as a result of digital etch. This could be due to the elimination of B+ ions incorporated at the sidewalls during the RIE process [8]. The digital etch also improves transport, as evidenced by a 25% increase in the peak gm (from 402 to 498 μS/μm at Vds=0.5 V). Fig. 14 shows that gate leakage also significantly decreases by

-0.6 -0.4 -0.2 0.0 0.2 0.4

10-8

10-7

10-6

10-5

w/ digital etchw/o digital etch

Vgs(V)

I d (A

)

Vds=0.5V

Vds=0.05V

10-7

10-6

10-5

10-4

Nor

mal

ized

I d (A

/μm

)

0.0 0.1 0.2 0.3 0.4 0.50

10

20

30

40Vgs=-0.6 V to 0.8 V in 0.1 V stepRon=589 Ω.μm (at Vgs=1 V)LG=80 nmD=40 nm

Vds (V)

I d (μ

A)

0

50

100

150

200

250

300

Nor

mal

ized

I d (μ

A/μm

)

0.0 0.1 0.2 0.3 0.4 0.50

20

40

60

80

100

Vds (V)

I d (μ

A)

Vgs=-0.6 V to 0.8 V in 0.1 V stepRon=310 Ω.μm(at Vgs=1 V)LG=80 nmD=50 nm

0

100

200

300

400

500

600

700

Nor

mal

ized

I d (μ

A/μm

)

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.810-7

10-6

10-5

10-4

I d (A

)

Vgs(V)

DIBL=360 mV/VS(Vds=0.05V)=210 mV/decS(Vds=0.5V)=305 mV/dec

Ig< 10-10 A

Vds=0.5V

Vds=0.05V

10-6

10-5

10-4

Nor

mal

ized

I d (A

/μm

)

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.40

100

200

300

400

500

600

Nor

maz

lied

I d (μ

A/μm

) gm, pk(Vds=0.5 V)

=730 μS/μm

Vds=0.5V

Vgs(V)

0

100

200

300

400

500

600

700

Nor

maz

lied

g m (μ

A/μ

m)

Fig. 12 Impact of digital etch on characteristics of D=40 nm devices. This is the final device diameter.

Fig. 13 Output characteristics of a D= 40 nm InGaAs single NW MOSFET fabricated without digital etch.

Fig. 9 Output characteristics of a D= 50 nm InGaAs single NW MOSFET.

Fig. 11 Transfer and gm characteristics at Vds=0.5 V of the device shown in Figs. 9 and 10.

Fig. 10 Subthreshold characteristics of the device shown in Fig. 9.

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60

50

100

150

200

Vgs(V)

0

50

100

150

200

250

300gm, pk(Vds=0.5 V)

=280 μS/μm

Vds=0.5V

Nor

maz

lied

I d (μ

A/μ

m)

Nor

mal

ized

gm (μ

S/μ

m)

Fig. 8 Transfer and gm characteristics at Vds=0.5 V of the device shown in Figs. 6 and 7.

IEDM13-69728.4.3

digital etch.

Figs. 15 show the evolution of key figur

function of final NW diameter for devicesand without digital etch. S and DIBL greatlyreduced, as expected. Peak normalized gm isdecreased. This is probably due to the stronseries resistance on D that is evident in Figtrade-off between transport (best indicateelectrostatics (measured by S) is obser

InGaAs NW MOSFETs of different diameetch improves S and gm but does not affect D

Fig. 16 benchmarks the transport and recently published vertical III-V single NWplotting gm,pk vs. S, both at VDS=0.5 V. Afabricated through bottom-up techniques.

30 35200

400

600

800

1000

1200

Vgs=1 VNor

mal

ized

Ron

(Ω μ

m)

Nan

30 35

150

200

250

300

350

400

450

Nanow

DIB

L (m

V/V)

Nan

w/o digi w/ digita

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.210-6

10-5

10-4

10-3

I g (A

/cm

2 )

Vgs(V)

w/ digital etch

w/o digital etch

Fig. 14 Impact of digital etch on gate leakage cusingle NW MOSFETs.

Fig. 15 Key device figures of merit vs. final nanowdevices fabricated with and without digital etch (oveach nanowire diameter are measured): (a) Linear saturated (Vds=0.5 V) subthreshold swing, (b) DIBLgm (Vds=0.5 V), and (d) Normalized Ron.

30 35 40 45 50

100200300400500600700800900

w/o digital etch w/ digital etch

Nor

mal

ized

gm (μ

S/μ

m)

Nanowire Diameter (nm)

Vds=0.5 V

(d)

(a)

(c)

30 35 40 45 50

150

200

250

300

350

S (m

V/d

ec)

Nanowire Diameter (nm)

w/ digital etch w/o digital etch

Vds=0.5V

Vds=0.05V

res of merit as a s fabricated with y improve as D is s reduced as D is ng dependence of g. 15(d). Thus, a d by gm,pk) and

rved in vertical

eters. The digital DIBL and Ron.

electrostatics in W MOSFETs by All but ours are

It is clear that

there is a trade-off between traneffects in all NW MOSFETs anddevices perform as well as the bInAs NW transistors fabricated by b

ConclusionWe have demonstrated the first IIwith a vertical channel fabricated Utilizing a novel III-V RIE protechnique, we have obtained a Vds=0.5 V, despite a thick EOT=2D=50 nm. Digital etch improvecharacteristics and the transport proof 20% in the peak gm is observed.a performance in terms of the balaneffects and transport that matchesNW III-V MOSFETs fabricated by

AcknowledgemResearch funded in part by NSFSTC). Devices fabricated at Technology Laboratories and ScLaboratory. The authors thank T. Antoniadis for valuable discussions

Reference[1] J.A. del Alamo, Nature, 2011. 479(73732012. 59(7): p. 1813. [3] K. Tomioka, M. 488(7410): p. 189. [4] K.M. Persson, M.Annual. 2012. [5] K. Tomioka, M. Yoshimu[6] T. Tanaka, K. Tomioka et al., APEX 201E.J. Norberg et al., JVSTB, 2011. 29(1): pLee et al., Appl. Sur. Sci, 1999. 143(1–4): pet al., JKPS, 2007. 50(4): p. 1130-1135. [10102(9): p. 093505-4. [11] K.M. Persson, Ep.428-430.

5 40 45 50

V

nowire Diameter (nm)

w/o digital etch w/ digital etch

40 45 50wire Diameter (nm)

owire Diameter (nm)

ital etchal etch

0.4

urrent of D=40 nm

wire diameter for ver 10 devices for (Vds=0.05 V) and L, (c) Normalized

(b)

Fig. 16 gm,pk vs. S at Vds=0.5 V for indiviNW MOSFETs. A trade-off is evidenfabricated through bottom-up techniques

nsport and short-channel d that our first-generation best vertical InGaAs and bottom-up techniques.

ns II-V GAA NW-MOSFET by a top-down approach.

ocess and a digital etch peak gm=730 μS/μm at

2.2 nm on a device with s both the subthreshold operties. An enhancement Our devices demonstrate

nce between short-channel s that of the best vertical bottom-up techniques. ment Award #0939514 (E3S

MIT’s Microsystems canning Electron Beam Yu, L. Guo, and D. A.

s. es 3): p. 317. [2] K.J. Kuhn, TED, Yoshimura et al., Nature, 2012. . Berg et al., DRC, 2012 70th ura et al., IEDM, 2011, p. 33.3.1 10. 3, p. 025003. [7] J.S. Parker, p. 011016-5. [8] T. Maeda, J.W. p.183. [9] J.W. Bae, C.H. Jeong ] M. Si, J. Gu et al., APL, 2013. . Lind et al., EDL, 2010. 31(5):

idual vertical InGaAs and InAs nt. All devices but ours are .

IEDM13-698 28.4.4