A Novel 6.72GHz Low Phase Noise Voltage-Controlled Oscillator AdoptingMetal-Oxide-Metal Capacitors Using 130nm CMOS Technology

Mohammed Aqeeli, Zhirun Hu, Cahyo Muvianto Microwave and Communication Systems Group School of Electrical and Electronic Engineering The University of Manchester

Manchester, UK mohammed.aqeeli-3@postgrad.manchester.ac.uk , Z.Hu@manchester.ac.uk, cahyo.muvianto@manchester.ac.uk

Abstract—This paper presents a novel Figure of Merit (FOM), low-phase-noise, LC-tank voltage-controlled oscillator (VCO). The work presents a fully integrated 6.72GHz VCO designed and simulated using 130-nm CMOS technology. Instead of using the conventional diode-based varactor in the tank design, a high-performance metal-oxide-metal (MOM) capacitor isemployed as an effective varactor. The proposed VCO-measured results demonstrate a worst case phase noise of -124.13dBc/Hz at 1MHz frequency, offset from a 6.72GHz carrier. An optimization technique is used to design an excellent FOM, which is -193.02dBc/Hz under a power consumption of 2.3mW. The VCO shows a tuning range of approximately 14%. To the best of our knowledge, this VCO presents the highest FOM level and the lowest phase noise compared to prior state-of-the-art solutions for the same frequency range.

Keywords—CMOS; CMOS processes; design method; (MOM) capacitor; figure of merit; low phase noise.

I. INTRODUCTION

The recent exponential growth in the higher integrationand wireless communication has attracted tremendous effort to developing more channels in mobile communication applications. VCOs are considered as one of the most important parameters in analogue and digital systems. Nowadays, the demand for high-performance VCOs has increased; consequently, this demand has imposed stricter requirements on the phase noise of the VCO.

The phase noise of the VCO is used to describe phase fluctuations caused by the random frequency fluctuations of a signal. Phase noise can be triggered by a number of conditions, but it is mostly affected by VCO frequency stability, which is one of the most important parameters for the quality and performance of information transfer and in turn affects reliability in data communication. VCOs are a major design challenge, and thus they have received a great deal of attention in recent years. Recently, many state-of-the-art integrated LC CMOS VCOs have been implemented in different CMOS technologies. Researchers and designershave tried to improve the phase noise performance of LC-VCOs, and therefore new phase noise theories have been proposed [1]-[4].

In this context, this paper presents the design of an original 6.72GHz low-phase-noise high-performance integrated LC-VCO. In this work, the possibility of improving the phase noise property of the VCO, by firstly implementing MOM capacitors in the VCO’s tank and by taking advantage of their high quality factors, high capacitance density, low parasitic capacitance, narrow spacing, and thinner dielectric layers, is presented. MOM capacitors can be a good option for radio frequency (RF) applications in CMOS processes, as they do not require extra process steps and, as a result, they reduce cost. Secondly, square-shaped spiral inductors were adopted to provide a low series resistance value and a high quality factor, 4.16�Q . The proposed VCO was designed using a commercially available UMC-130 nm mixed-mode CMOS process. To the best of our knowledge, we are the first to construct a fully integrated VCO with MOM inductors in this frequency range.

This paper is organized as follows. Section II explains the VCO’s core design and the implementation process, while Section III discusses the LC-tank in 130nm. Section IVpresents the implementation and the measured results, followed by the conclusion in Section V.

II. VCO DESIGN AND IMPLEMENTATION

The schematic for our LC-VCO design is shown in Fig. 1. The implemented VCO uses a complementary cross-coupled topology, and the performance was implemented byemploying a standard 130nm CMOS process. This schematicwas chosen because it can accommodate large signal swings as well as generate symmetric signals. Oscillation frequency was determined through the values of the LC tank.

VCOs are designed generally by considering minimum phase noise under the constraints of D.C. power dissipation, output voltage swing, tuning range, and die area. The topology of this VCO was selected so that the loss of the LC tank can be compensated for by cross-coupled NMOS and PMOS differential pairs, which provide negative resistance and generate symmetric signals [5]. Oscillation frequency was determined by the inductance and capacitance values in the LC tank, following which the targeted centre frequency was chosen as 6.72GHz.

2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks

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Figure 1. Complementary cross-coupled VCO.

Double cross-connect NMOS (MOSFET0- MOSFET1)and PMOS (MOSFET0-MOSFET1) differential pairs provide enough negative resistance to cancel out losses in the LC resonator. For further phase noise reduction, higherinductors Q are inevitable. The VCO circuit should have lower transconductance for minimum phase noise as Q increases [6]. Therefore, the VCO circuit also has to be optimized as Q changes, in order to utilize fully the high Q factors of an LC tank. The CMOS transistors must be biased and laid out in such a way that the required gm is obtained to overcome all losses, including those of the tank and the transistors. The respective transconductance of each pair was kept the same and was equal to gm/2. The total negative transconductance became –gm. As a result, less current was used and the loss of the tank circuit was compensated for,which led to lower power consumption as a result.

The primary challenge in designing VCOs is minimizing phase noise while maintaining the lowest amount of power consumption, which can be achieved by improving the quality of the LC tank. However, in many cases, the dominant noise contributor in VCOs is channel noise for CMOS transistors [3], [4]. To reduce the phase noise of the proposed VCO, some designs and techniques were taken into consideration, in order to obtain the best phase noise. Firstly, it is well known that phase noise decreases inversely proportional to the square of the quality factor (Q) in an LC tank [6]. Therefore, the capacitors in this design consisted of not only the variable capacitor for tuning the oscillator, but also fixed MOM capacitances, the load, and the active elements. Secondly, transistor sizing was used optimally to control the VCO current. In addition, the cross-coupled pair’s areas were kept slightly high to reduce 1/f noise. Thirdly, the inductors turned out to be near optimum for the oscillator design to reduce their series resistors, as will be seen later. Relatively small L and high Q inductor values are the key to a high-performance, low-power and low-noise

oscillator. Finally, keeping the gm of the NMOS and PMOS at the same value helped to reduce the up-conversion of phase noise, so the VCO outputs were buffered using NMOS (MOSFET2-MOSFET3) buffer stages to isolate the LC tank.

High-density 130nm technology by UMC was suggested and implemented in this design to create a generic, low-voltage, high-performance application. It displays superior performance and reliability when compared, for example, with similar CMOS structures, and by using this technology the circuit can be fabricated with standby power that is only 15% of other technologies.

The total capacitor for this design was approximately 280fF. The inductor turned out to be near optimum, which is around 400pH, and the physical W/L dimensions of the MOSFETs were maintained at 6µm/130nm for optimum phase noise. It can be shown that the oscillation frequency of an ideal tank and MOSFETs is given by [7]:

LCR

LC

2

2011��� (1)

For oscillation to occur, the gm of each MOSFET must

be:

LRCgm � (2)

Taking into consideration all of the parasitic capacitance of the VCO’s MOSFETs, the frequency of oscillation can be derived as:

2 02

20

0

)4(1

)4(1

LCCCR

CCCLgdgs

gdgs

���

���� (3)

From this equation it can be seen clearly that transistor capacitance C requires a decrease in the C value compared with the ideal case for a given resonant frequency [6]. Thestart-up gm condition also changes, such that the absolute minimum gm required for oscillation becomes:

L

CCCRd

g gdgs

sm

)4(1 0���� (4)

This equation establishes the importance of MOSFET size, and the result is that the bigger it is, the higher the gmmust be to achieve oscillation. Radio frequency (RF) sources have unwanted amplitude or signal phases [7]. These phase-modulated components, known as “phase noise,” are added to this signal by inserting a random variable (probability). To model the measured phase noise accurately, Leeson’s equation is used, in which an expression describes anoscillator’s phase noise spectrum for single-sideband (SSB) phase noise in dBc/Hz. L(fm) defines the ratio of power in a

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1Hz bandwidth away from the carrier—SSB power—which can be caused by a rise or fall in the amplitude or phase of the source, as well as additive broadband noise. The phase noise of an LC-VCO is described in equation (5) as [8]:

��

���

���

����

����

����

��

��

�

�

��

�

����

�

����

��

sm

c

mm p

FKTff

QffffL 11

221log10)(

2

1

0 (5)

where fo is the output frequency, fm is the offset from the output frequency, Ql is the loaded Q, fc is the 1/f corner frequency, F is the noise factor of the amplifier, k is Boltzmann’s constant, T is absolute temperature in Kelvins, and Ps is the oscillator’s output power. For a CMOS oscillator, noise factor F can be expressed as:

RgKV

RIKF biasbias ��

211 ��� (6)

where K1, K2 are constant, γ is a FET noise factor, gbias refers to the current source’s transconductance, R is tank resistance, and V is the output voltage. According to Leeson, the phase noise of the oscillator could be reduced by increasing the amplitude of the output signal. The power consumption of this VCO is inversely proportional to its phase noise level[7], so if the oscillation amplitude for a given voltage supply is wider, the VCO is more efficient.

It is noticeable that as the Q factor of the tank increases, phase noise decreases. The phase noise of an LC oscillator depends on the Q of the LC tank circuit. The quality factor is an indication of the energy lost as it is transferred from the capacitor to the inductor:

CRL

Rd

dQ pp

00

0

0

)(2

���

���

��

����

(7)

CRL

RQQQ cap

Ind

LcLoad0

0

111 ��

���� (8)

where LoadQ is the total loaded Q, pR is the equivalent parallel resistance of the lossy tank, individual losses and thecapacitor components themselves, cQ and LQ are the component Q of the capacitor and the inductor, respectively,

capR is the series resistance of the capacitor, and IndR is the series resistance of the inductor, which can be defined as:

� ������ /1.. tIndlR ��

� (9)

where

0

2���

� � (10)

The total length of the winding (l), [6] is:

� � )()1(914 swNNrnl ����� (11)

� �

���

�

�

���

�

��

�����

�

0

2

0

1.2.

)()1(914

��������

�

tIndswNNrnR (12)

For the planner inductor, the value L can be given approximately by [6]:

���

����

����

����

��

�� 2.0

)(ln..

20

wtnllL

��

(13)

where ωo is the oscillation frequency, s is the winding spacing, t is the thickness of the material, n is the winding count, w is the winding width, N= integer (n), σ is the conductivity of the interconnect, δ is the skin depth, and

0� is magnetic permeability.

III. LC TANK IN 130-NM CMOS

Integrated inductance-capacitances (LC) are standardcomponents in LC-tank VCO circuits and may become the most important part of a high-performance VCO circuit design. MOM capacitors are designed in this application because of their high density, high quality and low cost. The capacitors used in the proposed CMOS processes for the LC-tank VCO are generally small and usually of the order of 100fF.

Symmetric-type MOM structures could be a viable option for the application of VCOs in CMOS processes without requiring extra process steps; therefore, MOM capacitors for the tank, with capacitances at around 200fF, were designed. They rely on coupling capacitance between metal fingers running in parallel. The metal layers of these capacitors are stacked from Metal 1 to the upper metal layer to increase capacitance density. The lowest metal layer is limited to Metal 1. The metal finger’s width and spacing are fixed at minimum dimensions to achieve maximum capacitance density. The finger width and length of all the capacitors are set to 20μm, respectively, while finger spacing is the minimum allowed by the process. Such a design may

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increase capacitance due to the additional coupling introduced by the vias.

The MOM capacitor depends on coupling capacitance between metal fingers placed parallel to one another. In symmetric-type MOM structures, the architecture consists of two ports, and the number of fingers per layer is limited to even numbers, in order to maintain symmetry. The layout of the designed capacitors is shown in Fig. 2. The number of metal layers is six, finger length (L) is 12, and the area is 424.36μm2.

Figure 2. Layout of a symmetrical-structure MOM capacitor.

A set of inductors was designed and simulated at different frequencies, as shown in Fig. 3, using the 130-nmprocess and taking into consideration the impact of series resistance and the quality factor. The measured quality factor Q for the designed inductors was 16.40 for 895pH inductors, and the area was 27596μm2.

Figure 3. Inductor values and quality factor versus frequency.

IV. SIMULATION RESULTS

The implemented VCO was designed and measured using Cadence Tools. Fig. 4, which shows the transient analyses of the VCO, demonstrates clearly that steady state oscillation starts at approximately 8.5ns. The circuit generates stable periodic signals with a harmonic index, as shown in Fig. 5,and outputs are shown in Fig. 6.

Figure 4. Transient analyses of the VCO.

Figure 5. Harmonic index of the VCO.

Figure 6. Output signals of the VCO.

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The results obtained from simulating the LC-VCO design establish that phase noise has been reduced drastically. Abrief description of the performance summary is illustrated in Table I.

Table I. 6.72-GHZ VCO MEASURED PERFORMANCES.

The phase noise performance improves as the varactor gain decreases [7]. Therefore, the worst phase noise is recorded as shown in Fig. 8.

5.8 6.0 6.2 6.4 6.6 6.80.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

Vco

nt (V

)

Frequency (GHz)

Frequency - Vcontrol

Figure 7. VCO phase noise at 1 MHz offset frequency versus supply voltage.

Figure 8. Simulated phase noise at 1 MHz offset.

Phase noise is automatically decreased, while power consumption is reduced; thus, there is a trade-off between power consumption and phase noise [7]. A phase noise of -

124.13dBc/Hz at a 1MHz frequency offset is obtained at 6.72GHz frequency. To compare the performance of previously published oscillators and the FOM, we used the model adopted by Ham and Hajimiri [9], which normalizes the measured phase noise with respect to center frequency and power consumption. It is defined by equation (14):

� �� !

"#$�

� !

"#$%

�%�mWPd

fffLFOM

1log10log20 0 (14)

where f% is the offset frequency, 0f is the oscillating frequency, � �fL % is the measured phase noise at the offset frequency, and Pd (W) is the power dissipation of the VCO.

A brief description of the performance summary and acomparison with published work are highlighted in Table II,which shows that the design of the proposed VCO proved to be state-of-the-art, as phase noise is considerably good and the FOM is found to be excellent.

Table II. SUMMARY OF MEASUREMENT RESULTS AND PREVIOUSLY-REPORTED VCOS, USING CMOS.

V. CONCLUSIONS

We demonstrated a 6.72GHz low-phase-noise and low-power LC-VCO based on cross-coupled topology using 130nm CMOS technology. The feasibility of a high-performance, high-frequency VCO was demonstrated. The phase noise of the oscillator was optimized and the measured worst-case phase noise was -124.13dBc/Hz at a 1 MHzfrequency offset. As a result, this CMOS VCO achieves abest FOM of -193.02dB. The VCO shows an approximately 14% tuning range and consumes 2.25mW from a 2.3V power supply.

ACKNOWLEDGMENTS

The authors would like to thank Prof. Zhipeng Wu and Prof. Ali Rezazadeh for all their help and support.

REFERENCES

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