Bidirectional High Conversion Ratio DC-DC Converter

Justin K. Reed, Giri Venkataramanan Electrical and Computer Engineering

University of Wisconsin-Madison Madison, WI USA jkreed@ieee.org

Abstract— Recent trends in power conversion indicate a need for dc-dc power conversion at very high power levels and with high voltage buck/boost ratio for transmission/distribution purposes. No single conventional topology is well suited to these constraints. This paper proposes a new buck- or boost-derived multilevel non-isolated converter with superior scaling abilities. The paper derives the dynamic model in state space form, presents a suitable modulation method, and validates findings with computer simulations in MATLAB/Simulink and PLECS.

Keywords-multilevel, dc-dc, buck, boost, non-isolated, high frequency

I. INTRODUCTION

Historically, typical applications of dc-dc power conversion have involved power levels from single or even sub-W to tens of kW. However, emerging applications with dc distribution systems such as wind farms [1], photovoltaic generation, and mass transportation [2] require dc-dc converters well into the MW, which are also capable of high buck or boost ratios. Very few dc-dc converter topologies exist that can handle these constraints. Furthermore, in many cases galvanic isolation may not be required but is provided by the converter due to technological limitations of non-isolated topologies.

One potential topology is the Dual Active Bridge (DAB) converter, of which several variations exist, and which relies upon a medium-frequency transformer for voltage boosting/bucking [3]. This converter has been shown experimentally to tens of kW [4], however its extendibility to the MW range requires extremely challenging transformer designs using latest-generation magnetic materials at a significant expense. Also, galvanic isolation is provided by the transformer regardless of necessity, thereby needlessly increasing the converter cost.

A small number of non-isolated converter topologies exist that have desirable characteristics. Switched capacitor converters are capable of high buck/boost ratios and suitable for high power ratings, however their efficiency varies widely over small changes of duty ratio [5]; in most applications the duty ratio must be continuously variable, and the losses become insurmountable. Watkins-Johnson converters are also capable of high buck/boost ratios, but their reliance on magnetic energy

storage realistically limits their power throughput to a few kW, similar to the flyback converter [6]. Several stacked dc bus topologies have been recently proposed [7, 8], however the diodes must be fully rated for the highest terminal voltage, which realistically limits their use.

This paper introduces a new multilevel non-isolated dc-dc converter topology based on a 3-level buck- or boost-derived converter [9] that is capable of extremely high buck or boost ratios and very high power levels. A state space dynamic model is derived, a 4-level modulation scheme is proposed, and the designs are validated using computer simulations in MATLAB/Simulink and the PLECS blockset.

II. CONVERTER TOPOLOGY

A 3-level bidirectional converter from [9] is shown in Fig. 1. As seen in the figure, the switch positions select which capacitor voltage is applied to the inductor, listed in Table I. In order to minimize the inductor ripple current, the instantaneous inductor voltage is also minimized. Therefore, only switch positions are used where zero or one capacitor voltage is applied to the inductor at a time. The switch positions also determine the capacitor currents. Compared to a 2-level converter with equal ripple current, the 3-level converter

(a)

(b)

Figure 1. 3-level bidirectional dc-dc converter topology from [9] using (a) ideal SPDT switches and (b) IGBTs.

978-1-4577-1683-6/12/$26.00 ©2012 IEEE

(a)

(b)

Figure 2. Converter topologies using ideal SPDT switches for (a) 4-level and (b) 5-level converters.

TABLE I. 3-LEVEL CONVERTER TRUTH TABLE

h1 h2 VL 0 0 VC2 - VLV 0 1 0 1 0 VC1 + VC2 - VLV 1 1 VC1 - VLV

inductance is halved, as well as the switch and diode voltage ratings.

This topology may be extended to any arbitrary number of levels, following the examples of 4- and 5-level converters in Fig. 2. Regardless of the actual number of levels within the converter, however, the inductor voltage is always two levels. This is not a constraint of the topology but rather its proposed implementation; not only does this minimize the ripple current, but it also equally distributes the high-side voltage V1 among the switches to minimize their voltage rating and thus improve switching speed, parasitics, etc.

A. Converter Model Development

A state space converter model may be developed by representing the switching behavior with voltage and current switching matrices Hv and Hi. These matrices relate the switch positions to the voltages and currents within the switching structure. The 3-level converter has the simplest structure, while converters with more levels are straightforward extensions. Each column of the switching structure reduces the number of terminals by one, i.e. 4-to-3 or 3-to-2. When these columns are cascaded into the triangular shapes of Fig. 2, the

Figure 3. Example of switching structure decomposition into columns

for 4-level converter

switch poles of one column become the switch throws of the next. The switching matrices Hv and Hi must therefore represent these relationships. The dynamic model for the capacitor voltages and inductor current then follows by relating the capacitor currents and inductor voltage to the switching structure voltages and currents.

The switching structure for a 4-level converter is shown in Fig. 3, decomposed into its two columns. Starting with the 3-to-2 column on the right side, the following relationships can be found.

= ℎ 1 − ℎ = (1)

= ℎ1 − ℎ − ℎ =

Continuing with the 4-to-3 column on the left side yields

= ℎ 1 − ℎ 00 ℎ 1 − ℎ =

= ℎ 01 − ℎ ℎ−ℎ 1 − ℎ − ℎ =

A pattern emerges in the switching matrices, facilitating extensions to higher numbers of levels. =

ℎ 1 − ℎ 0 ⋯ 0 0 00 ℎ 1 − ℎ ⋯ 0 0 0⋮ ⋮ ⋮ ⋱ ⋮ ⋮ ⋮0 0 0 ⋯ 0 ℎ 1 − ℎ

L

VLVVHV C

C1

C2

C3

=

ℎ 0 ⋯ 0 01 − ℎ ℎ ⋯ 0 00 1 − ℎ ⋯ 0 0⋮ ⋮ ⋱ ⋮ ⋮0 0 ⋯ 1 − ℎ ℎ−ℎ −ℎ ⋯ −ℎ 1 − ℎ − ℎ

These matrices may then be combined to form the switching matrices for the overall n-level converter,

= ∏

= ∏

establishing a compact form for the relationships

= ⋮

⋮ =

where m represents the starting index on the high voltage side of the n-level converter and is given by

= ( )( ). (11)

With the switching structure voltages and currents defined in terms of the capacitor voltages, inductor current and switch states, the dynamic model relating these quantities may now be developed. The inductor voltage is given simply as the difference of the switch structure LV-side voltage (9) and the converter LV terminal voltage,

= − = ⋮ − , (12)

while the capacitor current is determined via Kirchhoff’s Current Law (KCL) from the HV-side current IHV and the switching structure currents,

⋮ = ⋮ = −−⋮− . (13)

Defining more explicitly using (10) yields (14).

⋮ = 1 ⋯ 0⋮ ⋱ ⋮0 ⋯ 1 − 1 ⋯ 0⋮ ⋱ ⋮1 ⋯ 1 . (14)

Equations (12) and (14) may then be reformed into the standard state space representation [10]

= + , (15)

with vectors

= ⋮ , = (16)

and matrices

= 01 ⋯ 0⋮ ⋱ ⋮1 ⋯ 1 0 (17)

= 00 . (18)

B. Modulation

Using the example of the 4-level converter shown in Fig. 2a, a pulse width modulation (PWM) scheme is proposed for selectively applying a maximum of one capacitor voltage to the LV side of the switching structure, and thus to the inductor. As a consequence of this behavior, a 100% duty ratio corresponds to VLV = VHV/3, where each capacitor voltage is connected to vsw for one third of the switching period.

A variety of modulation schemes may be employed in this converter to achieve certain goals, such as distributing losses among the switches in certain ways. The proposed scheme simply seeks to equally distribute the voltage and current stresses throughout the switching structure.

The gate signals h1 through h5 are constructed from 4 separate triangular ramp signals as shown in Fig. 4. Three ramps are separated by 1/3 of a switching period and are used in conjunction with modified duty ratio d’

= (1 + ) 3, (19)

where d may vary between 0 and 1. The fourth ramp signal is used to drive h4, has a fixed 50% duty ratio, and an offset of 1/4 switching period. A detailed view of the ramps, gate signals, and the resulting vsw waveform over one switching period Ts is shown in Fig. 5. Fig. 6 outlines all 6 portions of the switching period, denoted conduction periods.

Figure 4. Modulator implementation.

Figure 5. Triangular ramp waveforms and gate signals for d=0.5,

showing conduction period numbering and resulting Vsw waveform.

III. SIMULATION RESULTS

A 4-level converter was simulated in MATLAB/Simulink with the PLECS blockset using the proposed modulation scheme. A resistive load RLV was placed on the LV side and a small resistance RHV was placed on the HV side between VHV and C1 to more accurately depict realistic behavior. IGBTs were used for switching devices. Salient converter parameters are given in Table II. Simulation waveforms of inductor current and voltage IL and VL, respectively, as well as the voltage and current of C1 and output voltage VLV are provided in Fig. 7.

TABLE II. SIMULATED CONVERTER PARAMETERS

Parameter Value Parameter Value VHV 900 V L 1 mH VLV 50 V Switching Freq. 10 kHz C1 – C3 100 μF RHV 0.1 Ω C 100 μF RLV 10 Ω

Conduction Period 1

Conduction Period 2

Conduction Period 3

Conduction Period 4

Conduction Period 5

Conduction Period 6

Figure 6. Proposed modulation scheme for 4-level converter, showing all 6 conduction periods within one switching period.

0

0.5

0

1

Time0 Ts

d'

h1

h2

h3

h5

Period

h4

vsw

Ramp 2 Ramp 3 Ramp 1

Ramp 4

1 2 3 4 5 6 1

VC1

VC2

VC3

Figure 7. Simulation waveforms showing inductor voltage and current

(vL, iL), capacitor C1 voltage and current (vC1, iC1), and output voltage VLV.

SUMMARY

A multilevel dc-dc converter has been presented which is suitable for very high conversion ratios and bidirectional power throughput. It is less costly than other topologies that are typically used to achieve high conversion ratios because it does not require a transformer. The converter dynamic model has been derived based on the switching structure behavior, including a state space representation. A modulation scheme suitable for the 4-level converter was presented. Finally, the converter behavior was validated using computer simulations.

ACKNOWLEDGMENTS

The authors would like to acknowledge the support of the Wisconsin Electric Machines and Power Electronics Consortium.

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conversion for offshore windfarms," in 9th European Conference on Power Electronics and Applications, Graz, Austria, 2001, p. 11.

[2] A. Farini, F. Fuga, R. Manigrasso, and M. Ubaldini, "Light weight DC/DC converters for high-speed traction applications," in Proc. Second European Conference on Power Electronics and Applications (EPE), Paris, France, 1987, pp. 1287-92.

[3] R. W. A. A. De Doncker, D. M. Divan, and M. H. Kheraluwala, "A three-phase soft-switched high-power-density DC/DC converter for high-power applications," IEEE Transactions on Industry Applications, vol. 27, pp. 63-73, 1991.

[4] D. Aggeler, J. Biela, and J. W. Kolar, "A compact, high voltage 25 kW, 50 kHz DC-DC converter based on SiC JFETs," in 23rd Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Austin, TX, 2008, pp. 801-7.

[5] G. Zhu and A. Ioinovici, "Switched-capacitor power supplies: DC voltage ratio, efficiency, ripple, regulation," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 1996, pp. 553-556.

[6] Y. Darroman and A. Ferre, "42-V/3-V Watkins-Johnson converter for automotive use," IEEE Transactions on Power Electronics, vol. 21, pp. 592-602, 2006.

[7] K. A. Corzine and S. K. Majeethia, "Analysis of a novel four-level DC/DC boost converter," IEEE Transactions on Industry Applications, vol. 36, pp. 1342-50, 2000.

[8] G. Butti and J. Biela, "Novel high efficiency multilevel DC-DC boost converter topologies and modulation strategies," in Proceedings of the European Conference on Power Electronics and Applications (EPE), Birmingham, UK, 2011, pp. 1-10.

[9] X. Ruan, B. Li, Q. Chen, S.-C. Tan, and C. K. Tse, "Fundamental Considerations of Three-Level DC-DC Converters: Topologies, Analyses, and Control," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, pp. 3733-3743, 2008.

[10] R. C. Dorf and R. H. Bishop, Modern control systems, 9th ed. Upper Saddle River, NJ: Prentice Hall, 2001.

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