[IEEE 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PRIMEASIA) - Hyderabad, India (2012.12.5-2012.12.7)] 2012 Asia Pacific Conference on

Leakage Power Recovery in Spare Cells by using State Dependent Leakage Tables from Library models

Vasantha Kumar B.V.P Synopsys (India) Pvt. Ltd

Hyderabad, India [email protected]

N. S. Murthy Sharma BVCE College, Odalarevu,

India, 533210. [email protected]

K. Lal Kishore JNTU Ananthapur, Ananthapur, India

[email protected]

Nitika Goel M.Tech, VLSI DESIGN

NIET, Greater Noida, India [email protected]

Abstract— As the technology continues to shrinks, leakage power is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness, and doping profiles combined with an increasing number of transistors packaged in a single chip. During the physical implementation stages VLSI designs often needs be corrected due to the changes in specification or design rule constraints violations. This correction process is called Engineering Change Order (ECO). Spare cells are redundant cells introduced in the layout during early physical design stage whose inputs are traditionally tied to Power (VDD) or Ground (VSS) and will be used during ECO changes. However these spare or ECO cells in stand-by mode contributes to a significant sub-threshold leakage power in lower technology nodes. In this paper we are proposing a method which involves assigning optimal standby at every input of spare cell gate based on state dependent leakage power tables to minimize leakage power of spare cells. The proposed method was tested on standard cell based LVDS layout created using Synopsys SAED 32/28nm and other available Synopsys Design Ware 65nm, 45nm, 40nm & 28nm standard cell libraries. With the proposed method we could observe 48% to 30% reduction in spare cell leakage power and 3.8% to 0.7% reduction in design leakage power. Keywords-Spare Cells; State dependent leakage power; Engineering Change Order (ECO);Constant Insertion; Liberty Standard; Subthreshold Leackage Power; Power Recovery.

I. INTRODUCTION Minimization of power is one of the most important performance metrics in the design of portable systems and wireless communication devices. On the other hand the demand for greater integration, higher performance, and lower dynamic power dissipation drives scaling of CMOS devices. In nanoscaled CMOS devices leakage currents have increased dramatically leading to higher static power dissipation. There are many leakage sources. Among them the three major contributors are gate oxide tunneling based leakage (~54.79 percent), subthreshold leakage (~44.5 percent), and Band-To-Band-Tunneling (BTBT) based leakage (~0.68 percent) for 45 nm Bulk-CMOS [1]. Other components of leakage include Gate Induced Drain Leakage (GIDL), Drain Induced Barrier Lowering (DIBL), etc., [2]. The magnitude of each leakage component depends on the process technology used. However use of high-K dielectric gate helps reduce gate oxide leakage current. But, when high-K dielectric is used, the channel mobility degrades leading to reduced performance. SiGe layer has been used to strain Si to overcome reduced carrier mobility to improve performance. This, however, causes an

increase in subthreshold and BTBT leakage current [3]. For 65nm and below scaled CMOS devices the most important sources of leakage are: subthreshold leakage, gate leakage, and the reversed bias junction BTBT leakage. Subthreshold current rises due to lowering of threshold voltage which is scaled to maintain transistor ON current on the face of falling power supply voltage. Gate leakage current density is increasing due to scaling of oxide thickness resulting in rising tunneling current. In fact, gate leakage is expected to increase at least by 10 times for each of the future generations [4]. Reverse-biased tunneling band-to-band leakage is increasing due to reduction in junction depletion width that is necessary to contain transistor short channel effects (SCE). In previous CMOS technologies, dynamic power easily wins over leakage power but as shown in Figure. 1, ITRS road map predicted that this trend is coming to an end [5]. As technologies scales down, percentage of leakage power to total power is gradually going up with every node as shown in Figure.2. Leakage is an unwanted byproduct and substantially reduces the operational time of the devices thereby rendering such devices uncompetitive. It is, therefore, absolutely necessary to eliminate leakage, wherever it is possible. As leakage becomes increasingly significant in overall power consumption with feature size reduction, the goal of many implementations is to meet timing with the lowest possible leakage. Various system and architectural strategies are available to reduce overall power but there still remains the challenge of arriving at the optimal library cell mix for at-speed lowest power. A. Multi-threshold libraries cells Multi-threshold libraries are used to achieve the optimal library cell mix for at-speed lowest power design. These libraries are released with multiple versions typically called as high Vt (HVT), standard Vt (SVT) and low Vt(LVT) cells which are differentiated by gate length and/or gate implant thus providing a variety of trade-offs in performance versus leakage. SVT cells refers to the cell with standard threshold for the given process technology. The HVT cells refer to cells with higher threshold voltage than the standard for that process technology. Similarly, the LVT cells are faster than SVT and HVT cells but the leakage is also correspondingly high. Typically in high speed CPU design, the percentage of LVT cells from Synthesis netlist can be up to 99% as the

2012 Asia Pacific Conference on Post Graduate Research in Microelectronics & Electronics (PRIMEASIA) 19

BITS Pilani Hyderabad Campus 5th - 7h December 2012

designs are first synthesized using LVT cells to meet speed target. Even in physical design stage since performance target is most critical requirement designers put more effort on timing optimization from placement through post routing optimization. However power optimization during placement stages is done optionally or incrementally if critical timing can be met with small total negative slack (TNS). Final stage leakage power recovery is only done at ECO stages by swapping LVT cells with HVT cells on positive slack paths. B. Spare (or) ECO Cells leakage Design leakage is of particular importance not only to data path combinational logics, memory blocks and sequential elements but also to standby circuit connections of ECO or spare cells. In this paper we are focusing on standby leakage elimination in spare cells. Spare cells are redundant cells or extra cells distributed in the design as backup cells to implement any ECOs that may be required in the design, at a later stage. Spare cells do not play any active role in the IC operation. But some of these cells can be selectively connected to the normally functioning electronic components, during revising or rerouting process of IC. This process is often referred to as an ECO, and the spare cells can be alternatively referred to as ECO cells. Based on the performance of the design and switching activity involved different combinations of HVT, SVT and LVT cells will be sprinkled in the design core as spare cells. Spare cell not only occupy more chip areas causing substantial impact on the profit but are also responsible for the more leakage power [6]. The goal of the spare cell is to provide sufficient resources for ECO at every possible location so they are evenly distributed over the whole layout. Spare cells contribute to 5-20% of the total cell count in an IC [7]. As all the spare cells are not used by the additional design revisions, significant amount of power leakage exists throughout the life time of the chip due to cells which are not the part of the logic. In traditional design flows unused spare cells inputs are connected to VDD and VSS supply rails, which is called constant insertion technique and they will draw static or leakage current [8]. But this method of always tying inputs of spare cells to GND or VCC will not ensure less leakage. So, to address this issue we proposed an optimal state assignment technique to spare cell inputs to reduce their leakage power based on state dependent leakage table provided by foundry. To demonstrate the leakage recovery form ECO cells we have shown experimental results on LVDS design using Synopsys SAED 32/28nm library and other available Synopsys Design Ware 65nm, 45nm, 40nm & 28nm standard cell libraries [9, 10]. This paper is organized in to six sections. Section II talks about various ECO techniques along with prior work to reduce leakage power in spare cells. Section III talks about state dependent leakage power, Section IV talks about proposed method for reducing spare cells leakage, Section V talks about experimental results and Section VI conclusions.

Figure 1. ITRS road map showing static power surpassing dynamic power

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Switching Power, Logic Switching Power, Memory

Leakage Power, Logic Leakage Power, Memory Figure 2. SYSD11 SOC Consumer Stationary Power Consumption

Trends(from ITRS)

II. SPARE CELL BASED ECO’S AND MOTIVATION Design changes are inevitable and are increasing in complexity due to rapid growth in Very Large Scale Integrated (VLSI) design size. When these changes occur towards the end of the design cycle, where the design has converged after significant efforts, it is infeasible to go through the top down design flow again. This demands a method called Engineering Change Order (ECO) to keep these changes local to avoid any need to do re-synthesis of the whole design. Since the ECOs are done very close to tape out, these are time critical missions and any inefficiency in implementation will directly impact the cost of the product. ECOs can be functional and nonfunctional. Functional ECOs deal with making logical changes to the design. The core objective of a functional ECO is to accommodate RTL changes without major perturbation to the converged design. Nonfunctional ECOs deal with changes that affect signal integrity, Design Rule Verification (DRV) or routing.



A. Implementing ECOs There are two types of functional ECO flows during physical design flow. Unconstrained ECO (Non-Freeze Silicon ECO) flow and Freeze silicon ECO flow [11]. Unconstrained ECO flow is used if the design has not been taped out yet or before the mask preparations of the chip. In this flow there is flexibility of addition/deletion of standard cells while doing the change. These changes are first implemented logically with any type or number of standard cells and then these cells are placed and routed incrementally as part of physical implementation. This do not impact the mask cost for the SoC as all the masks are prepared after database is sent to Fab and no spare cells are required in the design. Freeze silicon ECO flow is used if cell placement is fixed or the changes are required to be done after the SoC is fabricated and issues are caught during its post silicon validation (i.e very late design change request). As, the mask generation cost for the base layers is multiple times the mask generation cost for the metal layers so addition/deletion or movement of any standard cell requires the base layer change hence any of such activity is avoided and some extra unused or redundant standard cells are added in the design for this purpose known as Spare Cells [12, 13, 14, 15, 16, 17, 18]. Spare cells are the extra functional cells kept in the design for ECO. The number of spare cells and their type depends on the design complexity and functionality, but it is advisable to use universal gates so that we can get most of the functionality or from the design functionality. The most commonly useful type of spare cells are INV, BUF, NAND and NOR, while the complex gates like XOR are rarely used [19]. B. Prior Work and motivation There are some techniques developed to reduce leakage in the circuit level, like programmable spare cells which will separate power rail from cell structure proposed by Anubhav Srivastava [6] and spare cell with two power supply rails proposed by Yung-Chin Hou [20]. This approach involves altering design cells layout (or) creating new libraries which requires significant changes to traditional flows. Also metal-configurable-gate-array spare cell ECO flows are becoming popular in recent technologies which needs gate array cells library provided by library vendor separately [21]. During the re-spin these cells can be programmed by metal mask changes for ECO implementation, thus reducing mask cost. These above mentioned methods are not flexible for re-spin designs and methodologies like gate array eco requires new libraries with entirely different flows. Engineering change order (ECO) is a highly constrained design optimization based on an existing design with tight design schedules due to time to market consideration [22]. Because of these reasons designers do not tend to change their design flows quickly to adopt these new flows which involves process changes. Also most of the re-spin designs with uses spare cell methodology for ECOs also require a smart of way of reducing spare cell leakages with minimum changes to lower metals. So there is a need for a smart approach with very minimum changes to existing design flows to address spare cell leakage.

III. STATE DEPENDENT LEAKAGE POWER The CMOS gates leakage power consumption would depend on the different states taken by the inputs of the gates [23]. This is referred as state dependent leakage power consumption of the CMOS gates. For a gate which has “n” inputs, there can be 2n states for which the leakage power consumption is found using the simulation models of the circuit and is stored in a format which can used by the EDA tools to estimate the state dependent leakage power of those gates. Every cell would contribute to the state dependent leakage power including the spare cells in the design. The silicon vendor models these state dependent leakage tables in the form of .lib (liberty) format [24]. Below is an example of state dependent leakage values specified in .lib for AND gate:

cell_leakage_power : 1.0 ; leakage_power() { when : "!A B" ; value : 1.5 ; } leakage_power() { when : "A !B" ; value : 2.0 ; }

The EDA tools will calculate the total leakage power consumption using above power models for leakage power optimization of functional paths. In the above power model example there are two "when" conditions; each "when" condition will be evaluated and multiplied with its probability. (Here the probability refers to the chances that the net "A" and "B" would be in such a state that the Boolean condition is satisfied). So the total leakage power would be the summation of all these "when" conditions multiplied with their probability. This can be formulated as shown below:

Pr(when1)*Val1 + Pr(when2)*Val2 + [1 - Pr(when1) - Pr(when2)]*Total_Val (1)

Pr (when1), Indicates the probability that the first condition will occur (i.e. "! A*B" will be true). Pr(when2), Indicates the probability that the second condition will occur (i.e"A*!B" will be true). The signal probability values Pr(A), Pr(B), and so on will be obtained from the net switching activity file provided as the input to the EDA tools. General formula for calculation of state dependent leakage power can be given as follows:

Pr(when1)*Val1+Pr(when2)*Val2+… Pr(when2

n)*Val2n+[1-Pr(when1)-Pr(when2)-

…Pr(when2n)]*Total_Val (2)

Where “n” stands for the no of inputs of the gate and

Total_Val= cell_leakage_power (3)



IV. PROPOSED METHOD For illustration let’s assume that the AND gate in above example .lib is a spare cell. This gate can have 4 different combinations (C1, C2, C3 and C4) of the A and B and hence four different state dependent leakage power values. If the state dependent leakage power table of this AND gate would be summarized as shown in Table 1. As per the traditional approach, if A and B inputs of the AND gate are tied to ground, C4 would be evaluated to be true and the leakage value would be V4 as per the table and the probability of occurrence of other conditions C1, C2 and C3 will be zero. Now from equation (2) Pr(C1), Pr(C2), Pr(C3) is zero as A and B of the AND gate is tied to ground and it’s leakage power can be given as: Psdlp of AND gate =Pr(whenC4)*V4 =1*V4= V4 (4) Pr(whenC4) = 1 as the inputs are tied to ground and hence when this condition will be evaluated to be true. But the leakage value V4 may not be the lowest value of power in the table. This is the problem with the traditional approach of connecting all spare cell inputs to ground. So we propose a state dependent leakage optimization method to idle spare cells where we assign a optimal state to inputs which will guarantee lowest possible leakage. In the proposed algorithm or flow we would be finding out the minimum leakage value Vmin for the spare gate and find the corresponding input condition Cmin from .lib models and tie the spare cell inputs based on this condition. If a spare master gate say “spareN” has n input pins, then there can be 2n when conditions or states in the power model table and 2n values of the leakage power values. So the minimum state dependent leakage power of the spare master as per the proposed flow would be:

P[minsdlp,spareN] = Pr(whenCmin) * Vmin (5)

As the inputs of the spare master “spareN” are tied to always evaluate condition Cmin, P[minsdlp,spareN] = Vmin for the spare master “spareN”. If there are “m” instances of this spare master “spareN” in the design then as per the proposed flow the total minimum leakage power consumption would be:

Total P[sdlp,spareN] = m * P[minsdlp,spareN] (6)

TABLE I. STATE DEPENDENT LEAKAGE POWER OF 2-INPUT AND GATE

When Condition Leakage Power ValueC1(A, B) V1 C2(A!, B) V2 C3(A, B!) V3 C4(A! B!) V4

A. Problem formation and algorithm Now our problem is defined as follows: Given a set of placed spare cell instances in a layout, our objective is to find

the optimal state which gives minimum leakage value form state dependent leakage power table of the corresponding .lib (liberty) files and tie them accordingly to their inputs. Our algorithm SDLPT_Based_Sparecell_Connection_Algorithm is shown in Figure 3. This proposed algorithm is written using tcl in order to be used in placement or post routing stages of physical design flow.

Figure 3. SDLPT_Based_Sparecell_Connection_Algorithm

V. EXPERIMENTAL RESULTS Our algorithm was used to tie the spare cells inputs with optimal state which promises low standby leakage on Low Voltage Differential Signalling (LVDS) design. We have used Synopsys SAED 32nm Multi-threshold library and 65nm, 45nm, 40nm & 28nm Synopsys Design Ware Multi-threshold libraries consisting of HVT, SVT & LVT cells. For this we carried out synthesis on LVDS RTL using these technology logical libraries using Synopsys’s Design Compiler® to get gate level netlist. We have implemented two sets of design suits. First 15 sets of layouts as shown in Table-II are implemented for each threshold (VT) cells across all mentioned technology libraries separately to observe the leakage variation. The second set of 5 layouts are created using all combinations of HVT, SVT & LVT cells to demonstrate real design scenario with optimal library cell mix for at-speed lowest power design. After synthesis we have done the floorplan, placement and placement optimizations using Synopsys IC Compiler®. At this point we inserted various spare cells into the layout and sprinkled them evenly across the layout. We have inserted 7 to 12% of total design cells as spare cells in these layouts. Figure 4 shows the spare cells distribution in LVDS design which are highlighted in white throughout the layout. We have selected spare cells based on conclusions made in [9] with majority of INV, BUF, NAND, OR and few NOR gates. We have also included few scanable flops per each clock group. In the second set of layouts in Table-II the combination of HVT, SVT & LVT cells are maintained as per the timing requirements and number of LVT spare cells are restricted up to 20% of total spare cells. Only for 28nm technology 14% LVT cells and 67% of SVT cells are used during synthesis for meeting timing. For the remaining technologies LVT cells percentage is restricted to below 2% and SVT cell to below 30% of total design cells count. HVT cells are used to primarily to reduce the leakage power by maintain design time and total negative slack (TNS). At this point we have made two copies



TABLE II. LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING STANDALONE VT CELLS ACROSS VARIOUS TECHNOLOGIES WITH PROPOSED METHOD

TABLE III. LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING OPTIMIAL LIBRARY CELL MIX FOR AT-SPEED LOWEST POWER WITH PROPOSED METHOD

Technology Node

(Mix of HVT, SVT & LVT %)

Total Cell

Count

Spare Cells

Count

Overall Design

Leakage

Spare Cell Leakage

with Traditional

Flow

% of Spare Cell Leakage in

Design with

Traditional Flow

Spare Cell Leakage

with Proposed

Flow

% Reduction in Spare

Cells Leakage


Design with

proposed Flow

% Reduction

in the overall Design leakage

65nm 298 30(10.0) 50.242nW 6.018nW 11.97803 3.993nW 33.64905 8.28131 -3.69672 45nm 385 30(7.7) 6.161uW 931.709nW 15.12269 669.898nW 28.10008 11.35576 -3.76693 40nm 493 50(10.1) 586.520nW 68.188nW 11.62586 47.649nW 30.12114 8.41883 -3.20703 32nm 417 30(7.1) 30.655uW 1.817uW 5.92725 1.640uW 9.74133 5.38093 -0.54632 28nm 540 50(7.3) 59.705uW 895.802nW 1.50038 481.001nW 46.30499 0.81127 -0.68911

of these layouts in each design directory for demonstrating variation in overall design leakage due to spare cells when they are connected in traditional (constant insertion method) versus proposed methods. After spreading spare or ECO cells in to the layout at placement stage we have used our tcl based algorithm to assign optimal states derived from state dependent leakage tables to the input of spare cells. Similarly other set of layout spare cell inputs are connect to ground (VSS). After this we proceeded to clock tree synthesis and finished routing and routing optimizations using IC Compiler® on all layouts. For this implementation starting form Synthesis we have used fast process, high temperature and high voltage corner which is the worst case PVT corner for leakage where the leakage values trend will as expected and without leakage inversion. Now finally at this point to analyze the leakage power of the design and spare cells contribution toward designs leakage in all layouts we have used Synopsys’s PrimeTime-PX® signoff power analysis tool. The result in Table-II shows the comparison between the spare cell leakage power numbers between traditional and proposed

flows and their contributions to overall design leakage. Nearly 48% to 30% of leakage recovery in spare cells is observed with proposed flow and it is consistent across different VT cells. This results in 1.7 to 0.7% of overall designs leakage recovery which is very significant for any handheld device chip. The results from Table-III shows real design scenario with mix of different VT cells shows an overall designs leakage recovery of 3.7% to 0.7% with proposed spare cell connections. Also with the recent enhancements in routing technology to handle special power cells comb routing of spare cells as per proposed method is not an issue. The input connections made by the tool during the routing as per the proposed optimal inputs states for the spare cells OR and XNOR in SAED 32nm layout is shown in Figure 5.

VI. CONCLUSIONS In this paper we proposed a new state dependent leakage tables based connections to ideal spare cell inputs which ensures minimum leakage power when compared to traditional constant insertion method where all inputs will be tied to

Technology (Vt Node)

Total Cell

Count

Spare Cells

Count (%)

Overall Design

Leakage

Spare Cell Leakage

with Traditional

Flow


Design with

Traditional Flow

Spare Cell Leakage

with Proposed

Flow

% Reduction in Spare

Cells Leakage


Design with

proposed Flow

% Reduction

in the overall Design leakage

svt 65nm 289 30(10.3) 305.601nW 15.953nW 5.22021 10.597nW 33.57362 3.52945 -1.72021 svt 45nm 383 30(7.8) 21.488uW 1.096uW 5.10052 774.427nW 29.3406 3.65875 -1.40052 svt 40nm 546 50(9.1) 1.191uW 49.799nW 4.18128 36.356nW 26.99452 3.08741 -1.08128 svt 32nm 378 30(7.9) 87.164uW 3.694uW 4.23799 3.332uW 9.79968 3.83862 -0.43799 svt 28nm 553 50(9.0) 35.303uW 789.896nW 2.23748 406.740nW 48.50715 1.16478 -1.03748 lvt 65nm 290 30(10.3) 1.204uW 61.769nW 5.13032 40.283nW 34.78444 3.40656 -1.73032 lvt 45nm 383 30(7.8) 47.422uW 2.145uW 4.52322 1.510uW 29.60373 3.22739 -1.32322 lvt 40nm 407 50(12) 2.970uW 224.308nW 7.55246 151.559nW 32.43264 5.23113 -2.35246 lvt 32nm 340 30(8.8) 578.984uW 31.447uW 5.43141 22.198uW 29.41139 3.8962 -1.53141 lvt 28nm 560 50(8.9) 123.511uW 2.729uW 2.20952 1.483uW 45.65775 1.21294 -1.00952 hvt 65nm 291 30(10.3) 23.454nW 1.051nW 4.48111 691.515pW 34.20409 2.99428 -1.48111 hvt 45nm 382 30(7.8) 6.508uW 325.125nW 4.99577 250.049nW 23.09143 3.88702 -1.09577 hvt 40nm 547 50(9.1) 192.856nW 8.518nW 4.41677 6.987nW 17.9737 3.6519 -0.71677 hvt 32nm 372 30(8.0) 26.196uW 878.018nW 3.35173 793.798nW 9.59206 3.04 -0.35173 hvt 28nm 608 50(7.3) 4.376uW 85.092nW 1.94452 54.222nW 36.27838 1.24788 -0.74452



power or ground. The method of using state dependent leakage tables to compute standard cells leakage has been explored much earlier. However its application to spare cells is new. The proposed method was tested on post placed layouts using 65nm and below technologies and results after routing shows that there is a huge reduction of 48 to 30 percent standby leakage power of spare cells and 1.7 to 0.7% reduction in total standby leakage of IC. The proposed method can be easily adapted to new or re-spin designs with very minimum changes to design flows.

Figure 4. Spare Cells Distribution across the layout in LVDS design

Figure 5. Spare Cells OR and XNOR connections after routing

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[IEEE 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PRIMEASIA) - Hyderabad, India (2012.12.5-2012.12.7)] 2012 Asia Pacific Conference on