Novel Multi-Level PCRAM cell with Ta2O5 Barrier Layer in between a Graded Ge2Sb2Te5 Stack

Ashvini Gyanathan,1 and Yee-Chia Yeo.1,* 1 Dept. of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore 117576.

* Phone: +65-6516-2298, Fax: +65-6779-1103, Email: yeo@ieee.org

ABSTRACT We report a novel multi-level phase change random

access memory (PCRAM) cell with a graded Ge2Sb2Te5 (GST) structure which enables multi-bit, high density storage. This work delves into the mechanism of the multi-level switching behaviour with both electrical as well as thermal analyses.

INTRODUCTION PCRAM is a promising candidate for non-volatile

memory (NVM) technology. PCRAM’s superior characteristics, such as fast read and write speeds and low power consumption [1], are factors that set it aside from other NVMs. PCRAM has the potential to compete with Flash Memory as it is capable of being scaled down to lower than the 22 nm node. PCRAM also exhibits multi-level behaviour, thereby making multi-bit high density storage realisable [2].

In this work, multi-level behaviour of PCRAM using a novel structure, consisting of a graded GST stack separated by a thin layer of Ta2O5, is demonstrated. Electrical as well thermal analyses were also done to better understand the mechanism behind multi-level switching in the PCRAM cell.

DEVICE FABRICATION Fig. 1(a) shows the schematic of the T-shape graded

GST PCRAM structure fabricated. 200 nm of titanium-tungsten (TiW) was deposited on thermally grown SiO2 on Si wafer. A 1 μm contact diameter was then formed between the TiW bottom electrode and the graded GST stack. The graded GST stack was formed by sputtering 25 nm of undoped GST, followed by a 1.5 nm layer of Ta2O5. 25 nm of nitrogen-doped GST was then deposited on top of this Ta2O5 barrier layer by sputtering GST composite target in N2/Ar ambient. The NGST contained 3.5 atomic percent of nitrogen. This graded GST stack was then capped with 10 nm of TiW to prevent oxidation. SiO2 dielectric deposition and TiW metallization were then performed. The TEM image in Fig. 1(b) confirms the 1.5 nm Ta2O5 layer.

RESULTS AND DISCUSSION A. Electrical Characterisation

The three distinct resistance states defining the multi-level PCRAM are shown in Fig. 2. Fig. 3 shows a statistical distribution of the three resistance states for a set of 8 measured devices. It is clear from this plot that the resistance window remains fairly constant from device to device. The set operation of another multi-level PCRAM device is portrayed in Fig. 4. The three resistance states are again clearly observed in this plot. Both the set and reset operations are also demonstrated here. Fig. 5 shows a DC sweep of a typical multi-level PCRAM cell. The change in gradient at the two points in the graph (as indicated by the dashed lines), confirms the resistance jump from state to state.

B. Thermal Analysis and Mechanism A two dimensional finite element thermal analysis was

done to obtain temperature profiles in each phase change material (PCM) layer in the graded GST stack to better

understand the mechanism behind the multi-level switching. The crystallization temperature (TC) of GST (145 ºC) is lower than that of NGST (~180 ºC) [3]. However, the melting temperature (TM) of GST (620 ºC) [4] is slightly higher than that of NGST (~600 ºC) [5]. A sufficient short high voltage pulse melts and quenches the PCM from a crystalline state to an amorphous one, whereas a longer but smaller voltage pulse crystallizes the PCM. This principle can be applied to the multi-level PCRAM cell as well.

When the first reset pulse of 4 V 10 ns is applied, the temperature of the NGST layer exceeds its TM and melts. The NGST layer becomes amorphous due to this melting and quenching process. The temperature in the GST layer however, does not exceed its TM and remains crystalline. This combination of both the amorphous NGST and the crystalline GST phases form the intermediate resistance level (State 2). Fig. 6 shows both the temperature profiles in GST and NGST as well as the contour plot during this 1st reset pulse.

When a second, higher voltage reset pulse of 6 V 10 ns is applied, both the GST and NGST layers amorphize as the temperatures in both of the layers exceed TM, thus achieving a very high resistance level (State 3), as shown in Fig. 7.

Once a set pulse of 1.5 V 400 ns is applied, both the layers crystallize to form a low resistance state (State 1). Fig. 8 confirms this as the temperature profiles are in between the respective TM and TC. The complete schematic portraying the transition from one state to another is shown in Fig. 9.

Another point to note is that the Ta2O5 layer acts as a thermal barrier which retains heat in the NGST layer. The thermal conductivity of ultrathin Ta2O5 (0.026 W/mK) [6] is an order lower than that of GST (0.2 W/mK). When the first reset pulse is applied, joule heating predominantly occurs within the higher resistive NGST layer. This causes the NGST layer to amorphize, while the GST layer remains thermally insulated and thus, crystalline. The difference in resistivities in the two PCM layers, coupled with the thermal barrier between them, enables the realisation of multi-level storage in this PCRAM cell.

CONCLUSION A novel multi-level PCRAM cell was fabricated using a

graded GST structure and a Ta2O5 barrier layer. The multi-bit storage capabilities of the structure are promising for very high density storage. This work shows the understanding of the mechanics behind the switching behaviour of the multi-level PCRAM cell through electrical and thermal analyses.

ACKNOWLEDGEMENT

We would like to thank Dr Zhao Rong, Dr Shi Luping and Mr Kian-Guan Lim from Data Storage Institute, A*STAR (Agency for Science, Technology and Research), for their invaluable help and support in this work.

978-1-4244-8492-8/11/$26.00 ©2011 IEEE

TiW

TiW

SiO2SiO2

SiO2

Ta2O5

NGST

GST

Si Substrate

(a) Schematic (b) TEM Image

NGST

GST

Ta2O5

20 nm 0 20 40 60 80100

101

102

103

Res

ista

nce

(kΩ

)

Time (s)

2

3

1

6V10ns

4V 10ns1.5V 800ns

Fig. 1. (a) Schematic of PCRAM cell fabricated in this work, and (b) TEM image showing various material layers in this cell.

Fig. 2. Resistance-Time display showing the three respective multi-level states.

State 1 State 2 State 3100

101

102

25%50%

Res

istan

ce (k

Ω)

75%

75%50%25%

75%50%25%

0 1 2 3 4 5 6

101

102

Res

istan

ce (k

Ω)

Voltage Applied (V)0.0 0.5 1.0 1.50

1

2

Cur

rent

(mA

)

Voltage (V)

Fig. 3. Distribution of resistance values for each state respectively.

Fig. 4. R-V curve of a multilevel PCRAM device with a 800 ns pulse width. The device was initialized to the amorphous state.

Fig. 5. DC I-V sweep showing threshold switching characteristics.

0 20 40 600

200

400

600

800

(a)

Tem

pera

ture

(°C

)

Time (ns)

GST NGSTTm,GST

Tm,NGST

Tc,NGSTTc,GST

100.0

200.0

300.0

400.0500.0

600.0620.0

700.0

-0.5 0.0 0.50

25

50

(b)Distance (μm)

Dep

th (n

m)

NGST

Ta2O5

GST 200.0

400.0

600.0620.0800.0

1000

12001500

-0.5 0.0 0.50

25

50

Ta2O

5

G ST

D istance (μm )

Dep

th (n

m)

NG ST

Fig. 6. 1st Reset Pulse (4 V 10 ns). (a) Temperature profile showing the peak temperatures in GST and NGST, and (b) Temperature Contour Plot (ºC) of 1st Reset Pulse in 1 �m contact region.

Fig. 7. Temperature Contour Plot (ºC) of 2nd Reset Pulse (6 V 10 ns) in 1 �m contact region.

0 100 200 300 4000

200

400

600

800

Tem

pera

ture

(°C

)

Time (ns)

NGST GSTTm,GST

Tm,NGST

Tc,GST

Tc,NGST

Crystalline NGST

Crystalline GST

State 1Crystalline

GST

State 2

Amorphous NGST

Amorphous GST

State 3

1st Reset pulse

2nd Reset pulse

Set Pulse

Amorphous NGST

REFERENCES

[1] S. Lai, IEDM Tech. Dig. 2003, pp.255. [2] Y. F. Lai et al, Appl. Phy. A. 84 2006, pp. 21-25. [3] H. Seo et al, Jpn. J. Appl. Phys. Vol. 39 2000, pp. 745-751. [4] A. L. Lacaita, Solid-State Elect. 50 2006, pp. 24-31. [5] S. Raoux et al, J. Appl. Phys. Vol. 103 2008, pp. 114310 [6] M. L. Grilli et al, Appl. Phy. A 71 2000, pp. 71-76.

Fig. 8. Temperature profile during a Set pulse (1.5 V 400 ns), extracted from peak temperatures in GST and NGST.

Fig. 9. Schematic showing the transition from one state to another. State 1 has the lowest resistance, while State 3 has the highest resistance.