Bias Temperature Instability (BTI) Characteristics of Graphene Field-Effect Transistors Bin Liu1, Mingchu Yang2, Chunlei Zhan1, Yue Yang1, and Yee-Chia Yeo1

1 National University of Singapore (NUS), Dept. of Electrical & Computer Engineering, Singapore 117576. and NUS Graduate School of Integrative Sciences and Engineering (NGS), Singapore 117456

2 Data Storage Institute, 5 Engineering Drive 1, 117608 Singapore.

* Phone: +65 6516-2298, Fax: +65 6779-1103, E-mail: yeo@ieee.org

ABSTRACT We report a bias temperature instability (BTI) study of graphene

Field-Effect Transistor (G-FET) for the first time. New BTI characteristics are observed for G-FETs fabricated using a graphene transfer-free process. Temperature significantly affects BTI of G-FETs by changing the direction of shift of IDS. A plausible graphene BTI mechanism is discussed.

INTRODUCTION Graphene is an alternative channel material to Silicon (Si) for

high-speed circuit applications due to its extraordinary physical properties such as extremely high carrier mobility [1]-[3]. Graphene Field-Effect Transistors (G-FETs) have attracted great attention [4],[5]. However, device reliability issues, such as bias temperature instability (BTI) which is an important issue faced by conventional Si CMOS devices [6]-[8], have not been investigated for G-FETs.

In the work, we report the first BTI study of G-FETs. G-FETs were fabricated using graphene formed on Nickel (Ni). New BTI characteristics which differ from those of Si MOSFETs are observed in G-FETs. Possible BTI mechanism of G-FETs will be discussed.

DEVICE FABRICATION Fig. 1 shows the process flow for fabricating G-FETs. Graphene

was synthesized using a process involving nickel catalyzed crystallization of Diamond-Like Carbon (DLC) [9]. Graphene was formed on 200 nm Ni on SiO2 substrates. Graphene on Ni was patterned to form ribbons. Ni was then etched using FeCl3 solution. Over-etch of Ni was performed in order to remove Ni under the graphene ribbon which will be used as G-FET channel. Graphene ribbon with underlying Ni etched lies on the SiO2 substrate as illustrated in Fig. 2. Source/Drain (S/D) contact formation (~50 nm Ni) was then performed, followed by gate stack (~15 nm Al2O3/~50 nm Ni) formation using a lift-off process. This completes the device fabrication. Fig. 3 shows a top view SEM image of a G-FET with a gate length LG of ~1.1 �m and a gate width WG of ~500 nm.

RESULTS AND DISCUSSION A. Basic Device Characteristics

Fig. 4 shows |IDS|-VDS of a G-FET with a LG of ~5.1 �m and a WG of ~500 nm. G-FETs in this work have p-type channels, which could be due to the fact that the graphene edge is terminated by hydroxyl group [10], hydrogen, and oxygen [11]. B. BTI Characteristics of G-FETs

Fig. 5 and 6 show the |IDS|-VGS characteristics of G-FETs before and after being stressed for 1000 s under gate stresses VGS,Stress of -1.5 V and 1.5 V, respectively, at room temperature (22 ºC). Negative VGS,Stress leads to right-shift of the |IDS|-VGS curve, while positive VGS,Stress results in left-shift of |IDS|-VGS curve. This observation is quite different from that for a typical Si p-channel MOSFET in which the current decreases in response to negative VGS,Stress and has almost no change under a positive gate stress. Note the |IDS|-VGS shift is almost parallel, especially for VGS > 0, so the threshold voltage VTH (could be defined at a fixed IDS) shift (�VTH) could be estimated from the VGS shift, i.e. �VGS.

The time evolution plots of �VGS at IDS = the average of maximum and minimum drain current [(IMAX + IMIN) / 2, refer to Fig. 5] under VGS,Stress = -1.5 V (top) and 1.5 V (bottom) are shown in Fig. 7. Fig. 8 shows the IDS changes (�IDS) at VGS = -1.0 V (left axis) and VGS = -1.0 V + �VGS (right axis) for VGS,Stress = -3.0 V and -1.5 V,

respectively. Positive IDS and VGS (VTH) shifts are observed under negative VGS,Stress. Fig. 9 shows the �IDS at VGS = -1.0 V (left axis) and VGS = -1.0 V + �VGS (right axis) for VGS,Stress = 3.0 V and 1.5 V.

Fig. 10 shows the |IDS|-VGS characteristics at different temperatures (22 ºC and 60 ºC). Under low field, higher IDS is obtained at a higher temperature of 60 ºC, as compared with 22 ºC, which could be attributed to increased carrier density and mobility under high temperature [12]. Fig. 11 shows �IDS under these two temperatures for VGS,Stress of -3 V and 3 V. Different IDS shifts in terms of direction are observed under the same VGS,Stress of -3 V. For VGS,Stress = -3 V, negative IDS shift is observed at 60 ºC, which completely differs from the results obtained at 22 ºC . Similarly, positive IDS shift is obtained at 60 ºC for VGS,Stress = 3 V, as compared with the negative IDS shift at 22 ºC. C. BTI Mechanism of G-FETs

We propose a plausible degradation mechanism for the new BTI phenomenon of G-FETs observed. Two factors would affect the performance of G-FETs under BTI stress. Like a conventional Si p-FET [13], positive charges (holes) will be trapped in the Al2O3 layer and interface states at graphene-Al2O3 interface will be generated (these two components will be together referred to as “interface factor”) under a negative VGS,Stress. The holes and interface states will act as a positive electrostatic gate which decreases the effective electrical field in the graphene channel for a same gate supply voltage as compared with the condition without interface factor, leading to decrease of IDS.

On the other hand, a negative charge layer (referred to as “substrate factor”), which acts as an effective negative electrostatic back gate, could be built up at the graphene-SiO2 interface in response to a negative VGS,Stress. This could be due to several factors. Electrons could be injected from graphene channel to the graphene-SiO2 interface and trapped in the oxide traps under a negative VGS,Stress [14],[15]. Adsorbates on the SiO2 substrate such as water and silanol groups could also have charge transfer with the graphene channel, trapping negative charges at the interface [16],[17]. Hole trapping in the gate dielectric and negative charge layer building up at graphene-SiO2 substrate interface in response to a negative VGS,Stress are illustrated in Fig. 12. A similar case could be considered for a positive VGS,Stress.

The results in Fig. 7 and 8 suggest that the negative charge layer at the graphene-substrate interface possibly has a dominant effect on the G-FET BTI characteristics under a negative VGS,Stress, resulting in positive shift of IDS and VTH. The results at 60 ºC (Fig. 11), however, indicate that the effects of this negative charge layer is significantly suppressed, as compared with that at 22 ºC, making the dielectric trapped holes and interface states generation (interface factor) dominant. As in Si MOSFETs [6],[7], higher temperature is likely to enhance interface state generation in G-FETs, which possibly enhances the effect of interface factor on BTI. The results obtained suggest that the enhanced interface factor overwhelms the substrate factor under elevated temperatures.

CONCLUSION Reliability performance of G-FETs is studied for the first time.

New BTI characteristics were observed on G-FETs on SiO2 substrate. Unlike Si MOSFET, G-FETs response to both negative and positive VGS,Stress by shifting the |IDS|-VGS curves to different directions. Temperature was found to have a significant effect on G-FET BTI characteristics. A plausible mechanism was discussed.

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REFERENCES [1] K. S. Novoselov et al., Science, vol. 306, pp. 666, Oct 2004. [2] S. V. Morozov et al., Phys. Rev. Lett., vol. 100, pp. 016602-1, Jan 2008. [3] K. I. Bolotin et al., Solid State Comm., vol. 146, pp. 351, Jun 2008. [4] L. Liao et al., Nano Lett., vol. 10, pp. 3952, Sep 2010. [5] Y. M. Lin et al., Science, vol. 327, pp. 662, Feb 2010. [6] M. A. Alam et al., Microelectronics Reliab., vol. 45, pp. 71, Jan 2005. [7] D. K. Schroder et al., J. Appl. Phys., vol. 94, pp. 1, 2003. [8] K. Onishi et al., IEEE Trans. Elect. Dev., vol. 50, pp. 1517, 2003.

[9] B. Liu et al., in SSDM, Tokyo, Japan, 2010, pp.123. [10] M. Lafkioti et al., Nano Lett., vol. 10, pp. 1149, Apr 2010. [11] X. R. Wang et al., Science, vol. 324, pp. 768, May 2009. [12] W. Zhu et al., Phys. Rev. B, vol. 80, pp. 235402, 2009. [13] M.-F. Li et al., IEEE T-DMR, vol. 8, pp. 62, 2008. [14] M. Radosavljevic et al., Nano Lett., vol. 2, pp. 761, 2002. [15] J. Yao et al., ACS Nano, vol. 3, pp. 4122, 2009. [16] J. S. Lee et al., J. Phys. Chem. C, vol. 111, pp. 12504, 2007. [17] E. David et al., Nanotechnology, vol. 21, pp. 085702, 2010.

Ni, DLC, and SiO2 Deposition

Graphene Synthesis (Anneal)

Patterning of Graphene-on-Ni

Removal of Ni under Graphene Ribbon

S/D Contact (Ni) Formation

Gate Stack (Al2O3/Ni) Formation

Ni NiS/D

NiS/D

300 nm SiO2

Graphene~15 nm Al2O3

~50 nm~200 nm

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Gate

S/D S/D

2 �m

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Drain Voltage VDS (V) -4 -2 0 2 4

6.0

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(IMAX + IMIN)/2

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1000 s Stress

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rain

Cur

rent

|ID

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Gate Voltage VGS (V)

0 200 400 600 800 1000

-1.0

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0.0

0.0

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1.0

22 �C

22 �C

VGS,Stress = 1.5 V

Stress Time (s)

VGS,Stress = -1.5 V

�VG

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DS =

(IM

AX +

I MIN

)/2 (V

)

0 200 400 600 800 1000

0

2

4

6

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2

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VGS,Stress = -1.5 V

�ID

S at V

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-1 V

(%)

Stress Time (s)

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-1 V

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-6

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Gate (Ni)

Gate Dielectric (Al2O3)

SiO2

Ground Ground

Gate (Ni)

Gate Dielectric (Al2O3)

SiO2

NegativeVGS,Stress

GroundGround

Graphene

After Stress

(a)

(b)

Negative Charge

Trapped Hole

Fig. 7. Time evolution of VGS or VTH shifts (�VGS or �VTH) for G-FETs under different VGS,Stress of -1.5 V (top) and 1.5 V (bottom).

Fig. 12. Hole trapping in the gate dielectric andnegative charge layer building up at graphene-substrate interface in response to a negativeVGS,Stress: (a) Before stress; (b) After stress.

Fig. 9. Time evolution of �IDS at VGS = -1.0 V (left axis) and VGS = -1.0 V + �VGS (right axis) for G-FETs under different VGS,Stress of 3.0 V and 1.5 V.

Fig. 6. |IDS|-VGS characteristics at VDS = -0.1 V of a G-FET before and after being stressed for 1000 s at 22 ºC. Gate stress voltage VGS,Stress is 1.5 V.

Fig. 1. Process flow for graphene synthesis and G-FET fabrication. The process is graphene-transfer free.

Fig. 11. �IDS at 22 and 60 ºC, and at different VGS,Stress values. At the same negative VGS,Stress, negative IDS shift is observed at 60 ºC, as compared with positive IDS shift at 22 ºC.

Fig. 5. |IDS|-VGS characteristics at VDS = -0.1 V of a G-FET before and after being stressed for 1000 s at 22 ºC. Gate stress voltage VGS,Stress is -1.5 V.

Fig. 3. Top view SEM image of a G-FET with a gate length of ~1.1 �m and a gate width of ~500 nm.

Fig. 2. Schematic of a typical G-FET. The graphene channel lies on a SiO2 substrate. The Al2O3 gate dielectric thickness is ~15 nm.

Fig. 4. |IDS|-VDS characteristics of a G-FET with gate length LG of ~5.1 �m and gate width WG of ~500 nm.

Fig. 10. |IDS|-VGS characteristics at 22 and 60 ºC for VDS = -0.1 V. The enhanced low field IDS could be attributed to increased carrier density and mobility under high temperature.

Fig. 8. Time evolution of �IDS at VGS = -1.0 V (left axis) and VGS = -1.0 V + �VGS (right axis) for G-FETs under different VGS,Stress of -3.0 V and -1.5 V.