50-90%

40-70%

30-50%

20-30%

10-20%

5-10%

System Level

Behavioural Level

Register-Transfer Level

Gate Level

Transistor/Circuit Level

Physical Level

Analysis of Leakage Power Reduction Techniques in Digital Circuits

Anup Jalan and Mamta Khosla

Department of ECE Dr. B. R. Ambedkar National Institute of Technology

Jalandhar (Punjab), India jalananup@gmail.com, khoslam@nitj.ac.in

Abstract—With the advent of battery operated devices and scaling trends in deep submicron (DSM) regime, leakage power is becoming large component of total power dissipation. In this paper leakage reduction techniques viz. Stack forcing and Multi-Threshold CMOS (MTCMOS) have been implemented on CMOS, Complementary Pass Transistor Logic (CPL), and Transmission Gate (TG) logic style based digital circuits. The effects of these techniques are analysed and compared using NAND, MUX, XOR, and Full Adder circuits. MTCMOS approach showed significant leakage power reduction by the order of three in case of CMOS and modified TG logic style based circuits. MTCMOS approach was not effective in CPL style circuits as it was in CMOS and TG logic style circuits, in standby mode. In Stack forced approach, decent leakage power reduction is achieved with large delay overhead, for all CMOS, CPL and TG logic style based circuits. Designs and simulations were done on Cadence® Virtuoso® and Spectre® tools, using UMC 0.18 µm technology.

Index Terms—MTCMOS (power gating); Stack forcing; CMOS; CPL; transmission gate; leakage power

I. INTRODUCTION While designing digital circuits and systems, minimizing

power consumption has gained considerable significance in DSM regime. And with the advent of modern battery operated devices, power optimization on all levels during design flow, from system level down to technology level has become important, to maximize battery life. On each level through the refinement process, the designer can manually or automatically apply optimizing transformations to minimize the power consumption of the design.

From the Fig. 1 it can be seen that the power saving reduces as the level of abstraction moves from system level to physical level, but increase in power saving at one level cause the increase in total power saving. So, saving power at each level is important. It should be noted that all parameters affecting power consumption could be addressed on circuit level, i.e. leakage power, switching power, short circuit power, etc. [11]. In this work emphasis is given on circuit level power saving.

At the circuit level, the digital circuits could be static or dynamic. The choice of using static or dynamic style is dependent on many criteria than just its low-power

performance, e.g., testability and ease of design. Dynamic logic has advantages in number of areas including reduced switching activity due to hazards, elimination of short circuit dissipation, and reduced parasitic node capacitance. Static logic also has advantage since there is no precharge operation and no charge sharing. It is this precharge and charge sharing operation in dynamic logic that causes lot of switching activity [1,9]. Large switching activity means large power dissipation. Hence, in this work static digital circuits have been analysed.

The researchers have analysed various leakage power reduction techniques at circuit level that were limited to CMOS implementation style. The leakage reduction techniques such as Stack Forcing and Power Gating or MTCMOS have been found to be effective methods to reduce leakage power in this implementation style. The application of leakage power reduction techniques on CPL and TG logic style based circuits have not been reported in literature, though these implementation styles have advantage over CMOS in many cases, in terms of power and delay [5,9].

In this work, the leakage reduction techniques viz. Stack forcing and MTCMOS have been implemented on CMOS, CPL and TG logic style based digital circuits. The effects of these leakage reduction techniques have been analysed and compared. For carrying out this analysis, four basic digital circuits NAND, MUX, XOR and Full Adder are designed using CMOS, CPL and TG logic styles. On each of these circuits, Stack forcing and MTCMOS approaches are implemented.

The remainder of the paper is organized as follows: Section II discusses the logic implementation styles. In Section III, the sources of power dissipation and dependence of leakage current on various parameters is discussed.

Figure 1. Potential power savings at different levels of abstraction.

Section IV, elaborates leakage reduction techniques and discusses Stack forced and Power gating approach in the sub-sections A and B respectively. Experimental setup to implement the logic is explained in Section V. Results have been discussed in Section VI and this work is finally concluded in Section VII.

II. LOGIC STYLES The impact of technology scaling is not the same for

different logic styles, therefore choosing the appropriate logic style for certain application is a complex task. It is a function of the system architecture, technology and design objectives. Usually, logic families are characterised by their speed, power dissipation, area, robustness and ease of use.

The static digital circuits can be implemented in many ways. Conventional CMOS, CPL, TG are a few popular design styles. Each logic style has its merits and demerits. For example, implementing MUX and XOR gate using CPL as well as TG requires few transistors compared to CMOS and is faster and consumes less power [2]. The analysis in this work focuses on CMOS, CPL and TG implementation styles.

III. SOURCES OF POWER DISSIPATION AND LEAKAGE CURRENT

In digital circuits, the total power dissipation consists of two components: a) Dynamic, and b) Static. Dynamic power dissipation consists of power consumed during charging and discharging of parasitic load capacitances, short circuit power due to conducting path between NMOS and PMOS transistors, and power consumed due to hazards and glitches. Static power dissipation is power consumed when the inputs are at steady state. The leakage power is the main component of static power. As the technology scales down the static power becomes comparable to dynamic power. Hence, leakage power dissipation has to be taken care. In DSM regime, the main sources of leakage currents are subthreshold conduction current (Isub), gate direct tunneling current(IG), gate induced drain leakage (IGIDL), reverse-biased junction leakage current, and punch-through current [3]. Amongst all the above listed leakage current components, subthreshold leakage is the dominant component of leakage current.

Subthreshold leakage current is the drain-to-source leakage current when the transistor is OFF. This happens in weak inversion mode, when the applied voltage Vgs is less than the threshold Vt of the transistor. Subthreshold current (Isub) flows due to the diffusion current of the minority carriers in the channel of Metal Oxide Field Effect Transistor (MOSFET) [3]. Equations (1) and (2) relate Isub with other device parameters.

Isub = I0 exp [(Vgs-Vth0-ηVds-γVsb)/nVθ ] [1-exp(-Vds/Vθ)] (1)

I0 = µ0 Cox (W/L) (Vθ) 2 e1.8 (2)

where, W and L are the width and length of the transistor, Vth0 is the threshold voltage; Vθ = KT/q is the thermal voltage; Cox is the gate oxide capacitance; µ0 is the carrier mobility; η is the Drain Induced barrier lowering (DIBL) coefficient; and n is the subthreshold swing coefficient. From (1) and (2), it can be

deduced that the transistor level leakage power reduction can be achieved if optimal transistor sizing is done. The transistor threshold voltage which scales down as technology scales down is another important parameter in (1) that cause the leakage current to increase exponentially. Portable devices such as cell phones operated by batteries are affected by leakage power dissipation, which remain idle for most of the time. Since it is not turned OFF, valuable battery power is drained out, which reduces the battery life [6]. Hence, existing design has to be modified in order to get low leakage power dissipation in the battery-operated devices, when it is active as well as when not operational, i.e. in active as well as in standby mode.

IV. LEAKAGE POWER REDUCTION TECHNIQUES The leakage power reduction techniques i.e. Stack forcing

and MTCMOS approaches are explained in the following sections.

A. Stack Forcing Leakage currents in NMOS or PMOS transistors depend

exponentially on the voltage at the four terminals of transistor as in (1). Increasing the source voltage, VS of NMOS transistor reduces subthreshold leakage current exponentially because of the following three effects:

• Gate-to-source voltage becomes negative, thus the subthreshold current reduces exponentially.

• Due to negative body to source potential, body effect increases which results in increased threshold voltage and thus reducing the subthreshold leakage.

• As drain-to-source potential decreases, drain induced barrier lowering (DIBL) effect lowers and thus subthreshold leakage decreases [3].

This phenomenon is also called self-reverse biasing of transistor. The self-reverse bias effect occurs when stack of transistors are turned OFF. Turning OFF more than one transistor in a stack increases the internal voltage (source voltage) of the stack, which acts as reverse biasing the source. By using input vector control approach as in [8], the leakage power can be reduced in naturally stacked transistor circuit such as CMOS NAND or NOR by providing input vector with least leakage power.

In this work, the forced stack approach has been employed on various digital circuits. It has been observed in [4] that Stack forcing has been applied in the circuits by replacing each of the transistors by two equal sized transistors; the two-stack condition for a given Vt with the least delay is for Wu = Wl = ½ W [6], to reduce the active mode leakage power. Leakage power reduces but at the cost of large delay overhead [4]. Hence, in this work, the forced stack has been employed selectively keeping in mind that the circuit performance does not degrade too much [10].

B. Power Gating or MTCMOS In MTCMOS technique, a high-threshold voltage transistor

is inserted in series with the power supply and the existing design and ground. In fact, only one type (either PMOS or NMOS) of high Vt transistor is sufficient for leakage reduction

as shown in Fig. 2. When in active mode, sleep transistors are turned ON, while in standby mode sleep transistors are turned OFF by applying appropriate voltage levels in the power gated mode, and large inserted MOSFET increase area and delay. These high threshold sleep transistors act as a current gate to the low threshold designed circuit, so this technique is also referred as Power Gating. Inserting additional sleep transistor(s) has an adverse effect on the circuit delay. Therefore, sizing sleep transistors is an important design consideration. According to the authors in [7], the drain current, (IDS)sleep flowing through the NMOS sleep transistor, considering 10% delay degradation can be expressed as in (3).

(IDS)sleep = 0.1µCox (W/L)sleep (Vdd - VtH) ( Vdd - VtL) (3)

where, µ is the mobility of the transistor, Cox is the gate –oxide capacitance, Vdd is the supply voltage, VtH is the threshold voltage of the sleep transistor, VtL is the threshold voltage low Vt transistor, W and L are the width and length of the sleep transistor respectively. From (3), the size of the sleep transistor can be found as in (4).

(W/L)sleep = (IDS)sleep / [0.1µCox(Vdd - VtH) ( Vdd - VtL)] (4)

Here, (IDS)sleep and (W/L)sleep are chosen to exhibit low power dissipation. Careful calculations and educated judgement are required to set the size of the sleep transistor.

V. EXPERIMENTAL SETUP The setup to implement the two leakage reduction

techniques i.e. Stack forcing and MTCMOS approach are explained here.

The Stack forcing is applied on the circuits where single transistor is present between the power supply and the output node of that stage. It is used to reduce the leakage by replacing a single transistor by two transistors having exactly half the width of the original transistor, and giving the same input to both the transistors.

In case of TG logic style, modification is done. The propagation delay has square dependence on number of switches and increases rapidly with the increase in number of switches in the TG chain. Hence, long delay is avoided by breaking the chain and by inserting buffers between the TG switches [5].

Figure 2. PMOS inserted MTCMOS circuit and NMOS inserted MTCMOS circuit [3].

By adding buffer stage before applying input to the TG logic, provides the solution to this delay problem with the benefit of leakage reduction in the standby mode at the same time in MTCMOS circuit as shown in full adder circuit of Fig. 3.

The leakage power in standby mode for basic and Stack forced circuits are taken as, minimum leakage power that is achieved after applying all possible combinations of input vector; for the purpose of comparison with MTCMOS approach.

The minimum frequency of the input signal was 500 MHz. In case of Full Adder circuits, to calculate the total power and delay, following input combinations were used: A (0 1.8 0 50p 50p 1n 2n), B (0 1.8 0 50p 50p 1.5n 3n), C (0 1.8 0 50p 50p 3n 6n).These input combinations cover all possible input vectors. The first and second terms in the braces indicate voltage levels of the pulse, the third term indicates the delay, fourth and fifth terms indicate the rise and fall time of the pulse respectively. The sixth term indicates the pulse width and finally the seventh term indicates the pulse period.

VI. RESULTS Based on the experimental setup, the circuits of NAND,

MUX, XOR and 1-bit Full Adder were designed in CMOS, CPL and TG logic style using UMC 0.18 µm technology. On each of these circuits the two leakage reduction techniques, Stack forcing and MTCMOS have been applied. The leakage power, total power and delay are computed on Cadence® Virtuoso® Schematic Editor and Spectre® tools. The results are listed in the Table I, II and III for CMOS, CPL and TG implementation styles respectively.

In case of Stack forcing approach, decent reduction in leakage power is achieved with increase in delay (>100% in many cases) for all logic styles viz. CMOS, CPL and TG. The total power also reduced by 15-25% compared to basic circuit without applying any leakage reduction technique.

In case of MTCMOS approach, very significant standby leakage reduction is achieved with little area overhead caused due to addition of high Vt sleep transistors in circuits designed using CMOS and TG logic style. The maximum standby leakage power achieved in power gated (or MTCMOS) CMOS Full Adder implementation was 46 pW, against 227 nW which is standby leakage power of its basic CMOS circuit.

Figure 3. Full Adder circuit implemented using power gated modified TG logic style.

TABLE I. PERFORMANCE ANALYSIS TABLE FOR CMOS CIRCUITS

CMOS Circuits Techniques

Total Power (µW)

Leakage Power Delay (ps) Active

(nW) Standby

(nW)

NAND Basic Circuit 18.87 45.42 11.33 37.82 Stack Forcing 15.72 30.33 11.33 61.82

MTCMOS 18.77 45.40 0.0103 41.63

MUX Basic Circuit 64.31 153.48 128.48 110.9 Stack Forcing 53.63 80 46.7 148.6

MTCMOS 64.09 154.75 0.04393 123.1

XOR Basic Circuit 119.9 215.43 197.75 126.8 Stack Forcing 104.3 106.79 102.8 190.35

MTCMOS 120.6 215.43 0.04401 152.5 1-bit Full

Adder

Basic Circuit 162.4 268.38 227.79 143.8 Stack Forcing 134 198.53 143.55 189.05

MTCMOS 159 268.38 0.04605 175.8

TABLE II. PERFORMANCE ANALYSIS TABLE FOR CPL CIRCUITS

CPL Circuits Techniques

Total Power (µW)

Leakage Power Delay (ps) Active

(nW) Standby

(nW)

NAND Basic Circuit 50.31 152.41 99.32 59.04 Stack Forcing 41.84 73.8 20.8 101.3

MTCMOS 49.5 152.48 65.01 63.28

MUX Basic Circuit 40.06 152.41 99.32 51.33 Stack Forcing 31.22 73.8 20.8 93.19

MTCMOS 39.35 152.36 100.7 56.03

XOR Basic Circuit 81.98 205.5 205.5 58.33 Stack Forcing 62.9 126.8 126.8 99.85

MTCMOS 79.48 205.7 106.7 63.23 1-bit Full

Adder

Basic Circuit 130.7 551.15 501.5 84.42 Stack Forcing 97.35 393.52 343.2 131.2

MTCMOS 128.6 512 339.35 90.5

TABLE III. PERFORMANCE ANALYSIS TABLE FOR TG CIRCUITS

TG Circuits Techniques

Total Power (µW)

Leakage Power Delay (ps) Active

(nW) Standby

(nW)

NAND Basic Circuit 69.11 214.75 180.1 76.08 Stack Forcing 60.57 70.15 35.61 182.45

MTCMOS 66.18 214.6 0.02482 83.42

MUX Basic Circuit 59.03 214.68 164.1 83.73 Stack Forcing 46.97 70.1 31.59 200.8

MTCMOS 57.05 214.52 0.02228 90.68

XOR Basic Circuit 82.18 249.2 249.2 76.09 Stack Forcing 74.8 104.6 104.6 179.65

MTCMOS 78.3 249.2 0.02482 84.17 1-bit Full

Adder

Basic Circuit 132 488.2 446 111.8 Stack Forcing 121.5 201.42 198.5 262.15

MTCMOS 122.5 487.37 0.02483 122.7

In case of TG logic style with MTCMOS approach, standby leakage power also showed a significant reduction by the order of three as found in CMOS implementation. Power gated TG Full Adder has maximum of 24.83 pW standby. From this analysis, it is observed that MTCMOS approach

was not effective in CPL style circuits as it is in CMOS and TG logic style circuits. Large leakage reduction in standby mode could not be achieved because of the presence of restoring PMOS transistor which is not completely OFF, and form sneak leakage path. The total power of the circuit reduced to some extent and the active leakage power was found to be almost equal to that of the basic circuit.

VII. CONCLUSIONS From this analysis, it can be concluded that leakage power,

total power and delay are inter-related. Optimization for one metric leads to compromise in the other metrics.

It can be concluded that when the delay caused due to Stack forced approach is tolerable, the circuit could be designed using Stack forced CMOS, CPL or TG logic styles to achieve decent leakage reduction both in active as well as standby mode.

MTCMOS approach is best suited when circuit performance cannot be neglected in active mode and good standby leakage reduction is desired. For designing battery operated devices that remain idle for long time one can choose between power gated CMOS and power gated TG logic styles of implementation.

REFERENCES [1] Chandrakasan, S.Sheng and R. Brodersen, “Low power CMOS Digital

Design”, IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473-484, April 1992.

[2] Reto Zimmermann and Wolfgang Fichtner, “Low-Power Logic Styles: CMOS Versus Pass Transistor Logic”, IEEE J. Solid-State Circuits, vol. 32, no. 7, April 1997.

[3] K.Roy, S. Mukhopadhyay, H Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no.2, pp. 305-327, February 2003.

[4] Jun Cheol Park and Vincent J. Mooney, “ Sleepy Stack Leakage Reduction,” IEEE Transaction on VLSI System, vol.14, No. 11, Nov. 2006.

[5] J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits-A Design Perspective, Second Edition, Pearson Education, 2009.

[6] Siva Narendra, Vivek De, Shekhar Borkar,Dimitri A. Antoniadis, and Anantha P. Chandrakasan, “Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-µm CMOS,” IEEE Journal Of Solid-State Circuits, vol. 39, No. 2, pp. 501-510, February 2004.

[7] M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique”, Proceedings ACM/IEEE Design Automation Conference, pp.480 - 485, 2002.

[8] Afshin Abdollahi, Farzan Fallah, and Massoud Pedram, “Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 12, No. 2, pp. 140-154 February 2004.

[9] Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits- Analysis and Design, Third Edition, Tata McGraw-Hill, New Delhi, 2003.

[10] Savithra Erante, Pradeep Nair, and Eugene John, “Leakage control in Full adders with selectively stacked Inverters,” Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium, August 1-4, 2010.

[11] N. When and M. Muench, Minimizing power consumption in digital circuits and systems-An Overview, Kleinheubacher Berichte, vol. 43, pp. 308-319, 2000.