A 500 W Push-pull Dc-dc Power Converter with a

30 MHz Switching Frequency

John S. Glaser, Juan M. Rivas

ELECTRONIC POWER CONVERSION LAB

GENERAL ELECTRIC GLOBAL RESEARCH

glaser@ieee.org

Abstract—

DESIGNERS of power conversion circuits are under relentlesspressure to increase power density while maintaining high

efficiency. Increased switching frequency is a primary path tohigher power density. Prior work has shown that the use ofswitching frequencies in the VHF band (30 MHz-300 MHz) area viable path to the achievement of gains in power density.A promising topology for VHF operation is the voltage-fedClass EF2 (Class Φ2) inverter based topology, where the use ofcontrolled impedance at the switching frequency and its 2

nd and3rd harmonics provides both full soft switching and substantially

reduced voltage stress compared to topologies such as Class E.However, such converters contain multiple resonant elements,and the tuning of the converter can be complicated due in partto the interaction of said elements. It is proposed that a push-pull version of the Class EF2 inverter can alleviate some of thesedifficulties. In particular, it is shown that odd and even frequencycomponents can be independently tuned without interaction,and furthermore that center-tapped inductors may be used toreduce the total volume occupied by said inductors. The benefitsinclude simplified design and increased power density. Evidenceis presented in the form of a push-pull Class EF2 (Class Φ2)unregulated 500 W prototype dc-dc converter with a 30 MHzswitching frequency, an input voltage 150 VDC, and an outputvoltage of 65 VDC. This converter has an efficiency of > 81%

under nominal conditions, including gate drive power.

I. INTRODUCTION

Designers of dc-dc power converters are under relentless

pressure to increase power density, efficiency, reliability, im-

prove transient response, and reduce cost, preferably achieving

all these goals simultaneously. In reality, certain goals are more

important than others. For example, aerospace applications

often have restrictions on overall system mass, and some loads

require fast dynamic response. The use of switching frequen-

cies in the VHF (very high frequency, 30 MHz-300 MHz)

band is a promising approach to provide substantial gains in

power density and bandwidth.

The chief operational principle of efficient power conver-

sion is the periodic controlled storage and release of energy,

whereby one regulates the average flow of power from one port

to another. In principle, power processing thus accomplished

is lossless, and in practice, low losses can be achieved [1]. One

of the key contributors to the volume of a power processing

circuit is the required energy storage, normally implemented

with capacitors and inductors. For a given technology, the

size of the energy storage elements is a monotonic, increasing

function of the energy to be stored. Thus, increases in power

density require a reduction in energy stored, or an increase

in energy storage density. The latter is influenced in part

by the physical structure of the energy storage elements, but

it is fundamentally dependent upon the materials available.

Limitations include the finite electrical and thermal conduc-

tivity of relevant materials; dielectric breakdown voltage and

permittivity for capacitors, and saturation flux density and per-

meability for inductors. Improvement in the material properties

of conductive, magnetic and dielectric components is generally

a slow, incremental process, and major breakthroughs happen

infrequently. The only alternative to increased energy density

is reduction of the required amount of stored energy per

operating cycle. For a circuit processing a specified amount

of power, this is accomplished by increasing the switching

frequency. Reduction in energy storage will also improve the

transient response of the converters.

Up to a point, increasing switching frequency results in

increased power density. As switching frequency further in-

creases, issues arise which detract from expected gains. These

issues include increased switching losses; proximity and core

losses in magnetic components; dielectric losses; and problems

with parasitic components. These can be mitigated to some

extent, but at a large enough switching frequency they domi-

nate the converter performance. Further increases in switching

frequency increase cost and power loss with no attendant

increase, or even a decrease, in power density [1]–[3].

Thus, how does one attain the potential power density

benefit resulting from high switching frequencies? Magnetic

components and semiconductors dominate the design in this

frequency range, with semiconductors dominating the effi-

ciency and magnetic components dominating the converter

power density. It is shown in [4] that if the frequency is high

enough that air core magnetics can be used, the scaling of

magnetics is favorable. In particular, it has been shown that

for constant heat flux and fixed impedance, inductor volume is

inversely proportional to 1/√FSW . However, the semiconduc-

tor switches still present a number of problems. Semiconductor

switches have two dominant loss mechanisms: conduction

losses and switching losses. A full discussion of semiconductor

losses is beyond the scope of this paper, and is well known;

see [5] for detailed discussion. The key point is that in con-

ventional hard switching topologies, as semiconductor die size

978-1-4244-4783-1/10/$25.00 ©2010 IEEE 654

increases, conduction losses are reduced, but switching losses

are increased, primarily due to increased device capacitance.

Soft-switching topologies have reduced switching losses at

the expense of higher semiconductor stresses and conduction

losses.

There exist several circuit topologies with low switching

loss capable of VHF frequencies. The most promising topolo-

gies to date are topologies based on the Class E inverter [6].

Furthermore, with the deliberate control of circuit impedances

at the harmonics of FSW , i.e. Class F operation [7]–[9], it

is possible to garner additional benefits including reduction

of peak stresses and higher FSW for a given semiconductor

switch technology. By combining Class E and F operation,

the benefits of both may be obtained, and this has been

demonstrated analytically and experimentally [10]–[14]. A

particularly promising topology for power conversion appli-

cations is the voltage-fed Class EF2 converter (also referred

to as Class Φ2), due to its combination of low transistor

voltage stress and greater capability to absorb transistor output

capacitance relative to Class E. However, this circuit suffers

from some drawbacks, including the use of four inductances

which must be tuned for proper operation, and whose tuning

interacts. In an effort to alleviate the latter issue and to gain

additional advantages, the authors propose a push-pull version

of the Class EF2 dc-dc converter. The benefits of push-

pull operation in RF amplifiers are well known [7], [14],

[15]. A key advantage relevant to this paper is the ability

to independently tune the MOSFET’s impedance at the even

and odd harmonics, which simplifies the design. Additional

advantages include the possibility of dc flux cancellation in

magnetic cores, reduction of the total number and size of

magnetic components, and a doubling of the ripple frequency.

Some of these advantages have been demonstrated in the

context of Class EF−1

x RF amplifiers [14], [16].

Section II presents an overview of converter topologies

suitable for VHF operation and highlights the advantages

a push-pull configuration has in power density and tran-

sient response. Section III, briefly reviews the single-ended

Class EF2 converter design and operation, and extends the

concept to a push-pull design. This section also shows how

the impedance at the odd and even harmonics can be in-

dependently tuned to achieve soft-switching and low device

voltage stress. Additionally, this section discusses other non-

obvious benefits such as the reduction of inductor number

and improvements in converter size. Details on the design

of a Push-pull Class EF2 dc-dc converter with a 30 MHz

switching frequency, an input voltage 150 VDC, and an output

voltage of 65 VDC are presented in Section IV. Experimental

evidence on the performance of this approach is presented in

Section V in the form of an unregulated 500 W converter with

an efficiency of > 81.5% under nominal conditions, including

gate drive power. Conclusions and future work are presented

in Section VI.

II. MOTIVATION FOR A PUSH-PULL CLASS EF2

CONVERTER

Let us first review the basic concepts of VHF dc-dc convert-

ers. Dc-dc converters can in general be modeled as an inverter

which generates an ac power signal, followed by a rectifier and

filter to convert the ac power signal back to a dc signal. In the

VHF range, inverters and rectifiers employ soft switching for

both turn-on and turn-off semiconductor transitions, keeping

switching losses at acceptable levels.

This paper is focused on the inverter and most of the

following discussion addresses the challenges in the design of

the push-pull implementation of a VHF inverter. There is some

discussion of the rectifier, but this topic is open research and a

thorough discussion of the rectifier will need to be addressed

by another paper.

The most common inverter topologies used in the HF or

VHF band are based on Class D, E, or F topologies [2], [6],

[13], [17]–[20]. Class D refers to switch mode amplifiers using

two transistors, and these may be arranged as either a half-

bridge or a push-pull arrangement, such that square waves are

generated. According to the conventional definition, Class Ddoes not imply soft-switching; thus, it will not be considered

further. Class E generally refers to a single-ended converter

with a resonant network that gives soft-switching on both

switch transitions. Class F generally refers to a single-ended

converter with control of impedance seen by the transistor at

one or more harmonics of the switching frequency, shaping

the waveforms to reduce stress and/or enhance efficiency. Both

Class D and F can be combined with Class E to obtain both

soft-switching and wave-shaping.

Class DE operation has desirable characteristics. When im-

plemented with a half-bridge switch, voltage stress is limited

to the bus voltage. However, driving the high-side switch with

the relatively precise timing required becomes difficult as the

frequency increases beyond 10 MHz-20 MHz, due in large

part to common-mode currents in the high-side gate drive that

flow through the parasitic impedance (usually capacitance) that

connects the high side gate drive to the gate control circuit.

This circuit can also be implemented as a push-pull design

with a center-tapped inductor. In this case, voltage stress is

twice the bus voltage, but two ground-referenced switches

simplify gate drive design. A major difficulty with this is that

true Class D or DE operation requires the coupling of the

two halves of the center-tapped inductor to approach unity.

As frequency increases, this becomes difficult to achieve, in

part due the reduced permeability of practical magnetic cores

at VHF frequencies.

The single-ended Class EF2 (Φ2) inverter has voltage stress

of approximately twice the bus voltage, similar to the push-

pull Class DE, but achieves this with inductance between the

dc bus and the transistor drain. This suggests that a push-

pull version of the Class EF2 could achieve the relatively

low voltage stress of the Class DE inverter, but with the

ability to handle a center-tapped inductor with low to mod-

erate coupling, i.e. considerable flux leakage. This allows the

655

L1

VDC,SE

iIN(t)iQ1(t)

vD(t)

vQ1(t)

i2(t)

C2

L2

C1

iC1(t) L3C3

iLD(t)

ZLD,SE vLD,SE(t)

ZQ1

(a) Single Ended Class EF2

20 40 60 80 100 120-120

-60

0

60

120

Ph

as

e [

de

gs

]

Frequency [MHz]

ZQ1, Simulated

-50

-25

0

25

50

20 40 60 80 100 120

Ma

gn

itu

de

[d

BΩ

]

(b) Drain-Source impedance

Fig. 1: Single ended Class EF2 and typical drain source impedance.

advantageous properties of the of the Class EF2 (Φ2) inverter

with push-pull operation to achieve the benefits of Class DEoperation at VHF switching frequencies.

There are several additional benefits. One anticipated benefit

is the doubling of ripple frequencies on both the inputs and

outputs, thereby reducing the input and output filter sizes.

III. PUSH-PULL CLASS EF2 CONVERTER DEVELOPMENT

This section describes the development of the push-pull

Class EF2 converter from the single-ended version. The

discussion begins with inverters in order to better illustrate

the key points, and the rectifier is discussed later.

A. Single-ended VHF EF2 inverter

Figure 1(a) shows a single-ended Class EF2 inverter. De-

tails of operation and a design procedure are given in [12].

The key components are switch Q1 which turns on and off

at frequency FSW ; the resonant network formed by L1, L2,

L3, C1, and C2; and the load ZLD,SE (a resistor in this

case). Capacitor C1 includes any switch output capacitance

that may exist. The main point is that the periodic waveforms

on switch Q1 are completely determined by the impedance

ZQ1 seen by Q1 at FSW and its harmonics. One of the difficult

aspects of the single-ended EF2 inverter is the proper tuning

of all the reactive components. For the Class EF2 inverter,

the impedances ZQ1 (FSW ), ZQ1 (2FSW ) and ZQ1 (3FSW )are deliberately controlled to provide wave-shaping and ZVS

at the semiconductor drain-source terminals. The impedance at

higher harmonic components is dominated by the impedance

of C1.

To achieve ZVS the resonant network is tuned to present

an inductive impedance at the switching frequency. The series

network formed by L2-C2 is tuned to be series resonant at

2FSW which provides a low impedance value of ZQ1 at the

drain. Besides providing dc blocking, C3 along with L3 set the

desired power to the load while at the same time interact with

the other resonant elements to shape the switch voltage and

lower the voltage stress. As shown in [12] a desirable operating

condition occurs when the resonant components are tuned such

ZQ1 (FSW ) > ZQ1 (3FSW ) ≫ ZQ1 (2FSW ). A typical drain

to source impedance of a tuned Class EF2 inverter tuned to

operate at 30 MHz is shown in Fig. 1(b). The tuning procedure

given in [12] is useful because it allows for the nonlinear

output capacitance of a real transistor, e.g. a MOSFET, but

requires trial-and-error tuning to get to the final design. This

can be difficult because adjustment of any reactive component

affects the impedance at all frequencies of interest, i.e. all the

resonant components interact with each other.

B. Push-Pull Class EF2 Inverter

This section develops the push-pull Class EF2 inverter

from the single-ended version. Section III-A points out that a

difficult aspect of the single-ended EF2 inverter design is the

tuning of all the reactive components. This requires some trial-

and-error tuning to get to the final design, and relies heavily

upon the designer’s experience because adjustment of any

reactive component affects the impedance at all frequencies

of interest. Nevertheless, with a transistor model of sufficient

accuracy it is possible to tune a design in simulation with

a high probability that said design can be translated into

functional hardware.

The construction of working hardware has practical diffi-

culties. A key reason for this is that it is extremely diffi-

cult to know and model all important circuit board parasitic

components prior to the design, and yet these parasitics have

a strong influence on the inverter operation. While a major

advantage of the Class EF2 inverter is that these parasitics

can be absorbed into the design, the lack of prior knowledge

means that once a hardware prototype is constructed, the

main resonant components need adjustment to account for the

parasitic components. At this point, the fact that each reactive

component affects the impedance at all frequencies of interest

makes tuning of the circuit a long and iterative process.

The first step in developing the push-pull version of the

inverter is to combine two inverters as shown in Fig. 2. The

two inverters, denoted by A and B for the top and bottom

inverter, respectively, are identical to each other and to Fig.

1(a). The total power processed by this system is now twice

that of the single-ended system. The position of C1 has been

changed to better illustrate the separation between switch Q1

and the rest of the circuit, but the connectivity is unchanged.

The key differences are that the input dc voltage VDC is

shared, and more importantly, gate drive signals are related

by

vDB(t) = vDA

(

t− TSW

2

)

(1)

656

where TSW = 1/FSW .

We begin to modify the circuit of Fig. 2 towards a single

push-pull converter with a single input voltage source and a

single load. The main point to keep in mind is that to achieve

Class EF2 operation, the transistor voltage waveforms must

be ideally identical to those for the single-ended inverter. This

requires that the drain impedances for the push-pull case be

identical to the drain impedance for the single-ended case at

multiples of the switching frequency, i.e., ZQ1A (nωSW ) =ZQ1B (nωSW ) = ZQ1,SE (nωSW ) , n ∈ 0, 1, 2, . . ..

This appears straightforward until it is understood that when

the circuit of Figure 2 is modified to make some components

common to both halves, the effective impedance in one half

of the push-pull circuit becomes influenced by the voltages

and currents in the other half, the latter being driven by

a time-shifted gate signal. One way to handle this is by

considering the odd and even multiples of the switching

frequency separately.

Equation (1) is used because it is not precise enough

to say that vDA and vDB are 180 out of phase in the

case where waveforms have harmonic content. Since periodic

waveforms with period TSW are assumed, all waveforms in

inverters A and B have frequency components at nFSW where

n ∈ 0, 1, 2, . . .. Furthermore that all waveforms in B will

be identical to those in A except for a delay of TSW /2. These

facts imply that the even components of waveforms of A and

B will be in phase, and the odd components will be 180 out

of phase, i.e.

VB (nωSW ) =

VA (nωSW ) if n is even

−VA (nωSW ) if n is odd(2)

IB (nωSW ) =

IA (nωSW ) if n is even

−IA (nωSW ) if n is odd(3)

L1A

VDC

iQ1(t)

vDA(t)

vQ1A(t) i2A(t)

C2A

L2A

C1A

iC1A(t) L3AC3A

ZLDA

ZQ1A

iQ1B(t)

vDB(t)vQ1B(t)

C2B

L2B

C1BL1B

L3BC3B

i2B(t)

iC1B(t)iL1B(t)

iL1A(t)

ZQ1B

vDD(t)vLD(t)

ZLDB

Q1A

Q1B

Fig. 2: Two Class EF2 inverters operating in push-pull fashion.

We can now define odd- and even-mode quantities in the fre-

quency domain (equivalent to common and differential mode)

and relate them to the values for a single-ended converter. For

voltages V (ω) and currents I (ω), the A and B subscripts

designate the corresponding nodes in the push-pull circuit, and

the SE subscript, the corresponding node on the single-ended

circuit.

Vodd (ω) =VA (ω)− VB (ω) = 2VSE (ω) (4)

Iodd (ω) =1

2[IA (ω)− IB (ω)] = ISE (ω) (5)

Veven (ω) =1

2[VA (ω) + VB (ω)] = VSE (ω) (6)

Ieven (ω) =IA (ω) + IB (ω) = 2ISE (ω) (7)

At this point the ω will be implied unless it is necessary to

specify a particular frequency. Since the component values are

assumed identical in the A and B sections, we can define the

even and odd mode impedances in terms of the single-ended

impedances [14]:

Zodd =Vodd

Iodd= ZA + ZB = 2ZSE (8)

Zeven =Veven

Ieven=

1

2(ZA + ZB) =

1

2ZSE (9)

The next step is to merge the two loads ZLDA = ZLDB =ZLD,SE into a single load ZLD = 2ZLD,SE , as Fig. 3 shows.

Clearly ILDA = −ILDB in all cases, so that ILD,even ≡ 0, i.e.

the well-known cancellation of even harmonics. This means

that the load now only affects the transistor drain impedance

at odd harmonics. For a typical Class EF2 inverter, this has

little effect on the drain impedance due to the combined effect

of the series network L3-C3, the second harmonic short L2-

C2, and the dominant effect of C1 at the third and higher

harmonics.

L1A

VDC

iQ1(t)

vDA(t)

vQ1A(t) i2A(t)

C2A

L2A

C1A

iC1A(t) L3AC3A

ZLDA

ZQ1A

iQ1B(t)

vDB(t)vQ1B(t)

C2B

L2B

C1BL1B

L3BC3B

i2B(t)

iC1B(t)iL1B(t)

iL1A(t)

ZQ1B

vDD(t) vLD(t)

Q1A

Q1B

Fig. 3: Two Class EF2 inverters operating in push-pull fashion witha single load.

The next step is to merge the two dc feed inductors

L1A and L1B into a single center-tapped inductor. This is

commonly done in push-pull RF amplifiers. In the ideal case,

the two halves of the inductor would have perfect coupling,

i.e. no leakage inductance. If this could be achieved, the even-

mode impedance due to this component would vanish, thereby

causing it to act as a short circuit to all even harmonics. This

would do away with the need for a separate second harmonic

short, and would allow the circuit to operate as a push-pull

Class DE inverter. Unfortunately, good coupling is difficult

to achieve for high power components at VHF frequencies;

the second harmonic short will be addressed below. Another

benefit is a result of the fact that the inductance is a super-

linear function function of the number of turns. Recall that

the odd-mode inductance of L1 is simply the inductance with

657

the center-tap open. All else being equal, the push-pull (odd-

mode) value of this inductance should be twice the single-

ended value. However, this will not require twice the turns,

hence the push-pull inductor will not double in size compared

to the single-ended inductor, even though the push-pull power

is double the single-ended power. This gives the push-pull

inverter a power density advantage over the single-ended

inverter. Finally, for cases that employ magnetic cores, dc flux

cancellation occurs. This allows a larger flux swing and thus a

smaller core. The latter assumes that such a design would not

be core loss dominated; there are promising developments in

magnetic materials that may allow this benefit to be realized

[21].

VDC

iQ1(t)

vDA(t)

vQ1A(t) i2A(t)

C2A

L2A

C1A

iC1A(t) L3AC3A

ZLDA

ZQ1A

iQ1B(t)

vDB(t)vQ1B(t)

C2B

L2B

C1B

L3BC3B

i2B(t)

iC1B(t)iL1B(t)

iL1A(t)

ZQ1B

vDD(t) vLD(t)

Q1A

Q1B

L1A

L1B

Fig. 4: Push-pull Class EF2 inverter with a center-tapped dc feedinductor L1.

Finally, we can address the second harmonic short. In the

single-ended Class EF2 inverter, the series resonant network

formed by C2 and L2 forms a short circuit at the second

harmonic, but it still has a substantial effect on the impedance

at other components of the switching frequency, especially at

the fundamental frequency. It is documented in [14] that a

network can be specifically designed to have different odd-

and even-mode impedances. There are two simple ways that

this can be accomplished for the push-pull Class EF2 inverter.

Figure 5 shows the first way. The second harmonic short

network is accomplished with C2, L2A, and L2B . Since L2A

and L2B are identical, IC2,odd≡ 0, and so the odd mode

components of the drain voltage see only ZL2A+ ZL2B

.

The even mode components of the drain voltage see ZC2+

1

2(ZL2A

+ ZL2B). Thus, we can adjust the value of L2A and

L2B to get the desired impedance at the transistor drains for

FSW and 3FSW without regard to the second harmonic. Once

this is done, C2 is selected to form a series resonant short for

the second harmonic 2FSW , and this can be done without

affecting any odd frequency components. Higher harmonics,

both even and odd, are dominated by the drain capacitances,

as with the single-ended inverter. It is possible to implement

L2A and L2B as a single center-tapped inductor. This will

beneficially present a higher odd-mode impedance, and the

smaller even-mode impedance would allow a larger C2 with

a lower voltage rating.

Figure 6 shows the second way, which is dual to the

first. The second harmonic short network is accomplished

with L2, C2A, and C2B . Since C2A and C2B are identical,

IL2,odd≡ 0, and so the odd components of the drain voltage

see ZC2A+ ZC2B

. The even components of the drain voltage

L1A

VDC

iQ1(t)

vDA(t)

vQ1A(t)

i2A(t)

C2

L2AC1A

iC1A(t) L3AC3AZQ1A

iQ1B(t)

vDB(t)vQ1B(t) L2B

C1B

L3BC3B

i2B(t)iC1B(t)iL1B(t)

iL1A(t)

ZQ1B

vDD(t) vLD(t)ZLDL1B

Q1A

Q1B

Fig. 5: Push-pull Class EF2 inverter with center-tapped dc feedinductor and single capacitor (C2) for second harmonic shunt.

see ZL2+ 1

2(ZC2A

+ ZC2B). Thus, we can adjust the value

of C2A and C2B to get the desired transistor drain impedance

at FSW and 3FSW without regard to 2FSW . Once done, L2

is selected to form a series resonant short for the second

harmonic 2FSW , and this can be done without affecting

odd frequency components. Again, all higher harmonics are

dominated by C1A and C1B .

In theory, both methods should work. In practice, the selec-

tion depends on the specific design. Presently it is unknown

how to select the best method a priori. At this point, the key

concepts to the push-pull inverter have been discussed. This

is far from a systematic design procedure, but is sufficient to

implement a design.

L1A

VDC

iQ1(t)

vDA(t)

vQ1A(t)

i2A(t)

L2

C2AC1A

iC1A(t) L3AC3AZQ1A

iQ1B(t)

vDB(t)

vQ1B(t) C2BC1B

L3BC3B

i2B(t)iC1B(t)iL1B(t)

iL1A(t)

ZQ1B

vDD(t) vLD(t)ZLDL1B

Q1A

Q1B

Fig. 6: Push-pull Class EF2 inverter with center-tapped dc feedinductor and single inductor (L2) for second harmonic shunt.

C. Push-Pull Rectifier

The development of the push-pull resonant rectifier from the

single-ended version follows the same path as for the inverter

[13]. The single-ended resonant rectifier is shown in Fig. 7(a),

and the push-pull version in Fig. 7(b). Figure 7(b) shows two

separate inductors L4A and L4B . It is possible to combine

these into a single center-tapped inductor as with the inverter

inductors L1A and L1B , and realize similar benefits.

IV. CONVERTER DESIGN

This section describes the design of push-pull converter with

the nominal specifications in Table I. These specifications were

chosen based on the desire to demonstrate the converter at

power levels consistent with conventional printed-circuit board

techniques. A systematic procedure for the optimal design of

Class EF2 converters does not yet exist. However, a general

set of guidelines combined with some iteration can yield useful

results. This section illustrates this design process.

658

L4D1CLD

RLD,SE vOUT,SE(t)vLD,SE(t)

ZLD,SE

(a) Single-ended resonant rectifier.

L4D1A

CLD

RLD

VOUTvLD,SE(t)ZLD

L4D1B

(b) Push-pull resonant rectifier.

Fig. 7: Single-ended and push-pull resonant rectifier implementations

The overall process consists of designing a simulation model

of a converter, getting the simulation running and then building

the converter based on the simulation model. It is likely that

there will be numerous parasitic components not accounted

for in the simulation. These parasitics can and should be

minimized via the use of RF design techniques, but it is

difficult to anticipate all the parasitics and pre-assess their

values, and some cannot be eliminated due to the physical

size of parts required to handle the design power. Fortunately,

the Class EF2 converter is highly tolerant of parasitics, and

they can be accounted for by using the simulator to plot the

expected drain impedance under a selected bias condition, and

then measuring the same impedance on the real circuit board.

Components are then adjusted in value until one obtains a

close match between simulation and measurement of even-

and odd-mode impedance values at FSW , 2FSW , and 3FSW .TABLE I: Nominal specifications for prototype push-pull Class EF2

dc-dc converter

Parameter Name Value Units

DC input voltage VIN 150 [V]DC output voltage VOUT 65 [V]

Output power POUT 500 [W]Switching frequency FSW 30 [MHz]

First we choose power semiconductor devices, namely

transistors Q1A and Q1B and rectifiers D1A and D1B . The

transistor is a Microsemi ARF475FL [22], which is actually

a pair of 500V RF MOSFETs in an RF package designed

for push-pull operation. A single ARF475FL will be used for

both Q1A and Q1B . The rectifier is a silicon carbide Schottky

diode, a Cree CSD10060A rated for 10A, 600V, which is

a proven performer at the frequency of interest. A Schottky

diode is required to eliminate reverse recovery and associated

losses. Each diode D1A and D1B comprises two CSD10060As

in parallel, so that the complete rectifier uses four physical

diodes. The use of parallel diodes reduces the rectifier losses

considerably [13].

Good models of the semiconductor devices are necessary.

These devices have inherently nonlinear I-V and C-V char-

acteristics. Behavioral models are sufficient, possessing the

benefit of relatively simple parameter extraction and fast

simulation speed. For the ARF475FL, a close comparison with

the Microsemi ARF521 [23] shows that each transistor in the

ARF475FL package likely uses the same die as the ARF521.

This allows the use of the ARF521 SpiceTM model developed

and used successfully in [13]. The diode model was developed

using I-V and C-V measurements as input to the modeling

procedure in [24]. A small stray series inductance (7nH) was

incorporated into the diode model.

The next step is to design the rectifier. A simulation of

the rectifier of Fig. 7(b) is built using the diode model and

driven by a sinusoidal current source of frequency FSW .

The current amplitude and inductance value of L4A and

L4B are adjusted until the correct power is obtained and the

fundamental component of VLD is in phase with the driving

current. At this time, an effective equivalent load resistance

can be determined.

The next choice is which second harmonic network to use.

For this converter, the network in Fig. 6 yielded smaller

inductor values, and had the practical benefit that a single

L2 was easier to tune in the prototype than a capacitor.

Now the push-pull inverter is designed based on the load

resistance from the rectifier, following the same procedure

as given in [12]. Fig. 8 gives the simulation schematic. The

key difference in tuning from the single-ended version is the

simulated measurement of the even and odd drain impedance.

Two 1 amp current AC sources are used to inject a test current

at each drain, and the voltages measured. Due to the A-Bsymmetry, if the currents are injected in phase, a measurement

of the drain voltages will yield the even-mode drain impedance

ZD,even =1

2 (1A)(VQ1A + VQ1B) (10)

The odd-mode impedance is determined by changing the phase

of the test current sources so that they are out of phase, which

will give the odd-mode impedance

ZD,odd =1

(1A)(VQ1A − VQ1B) (11)

The final impedance magnitude plots thus obtained are shown

in Fig. 11, where they are plotted along with the experimental

results. The values are of meaning only at the corresponding

components of the switching frequency (pointed out in the

figure). Similar plots are used to aid the design iteration

process. The final plots are used to as a reference to guide

the tuning of the hardware prototype.

Figure 9 gives the key simulated waveforms of the of the

full converter.

V. EXPERIMENTAL RESULTS

Figure 10 shows a photograph of the 500 W push-pull

Class EF2 dc-dc converter prototype with a 30 MHz switching

frequency, an input voltage of 150 VDC and an output voltage

of 65 VDC.

Figure 11 shows the measured even- and odd-mode

impedances. These were measured by applying 100VDC to

659

Fig. 8: Simulation schematic of push-pull Class EF2 dc-dc converter including push-pull resonant rectifier.

##.2-345)6&+#.2-7++#7+$-0+##+#.#

Fig. 9: Simulation results for converter of Fig. 8. Top pane shows thetwo drain-source voltages and the drain-drain voltage. Middle paneshows comparable waveforms for rectifier input. Bottom plane showsthe output voltage. The time scale is 7 ns/div.

Fig. 10: Photograph of 500 W, 150 VDC to 65 VDC with 30 MHzswitching frequency.

the drain and 50VDC to the output in order to bias the

semiconductor junctions to an approximate operating point.

These bias conditions are the same used for the simulation.

These were measured using a network analyzer in conjunction

with a balun and dc blocking capacitors to allow the odd-

mode measurement to be made. Note the close match at FSW ,

2FSW , and 3FSW . At the other less critical frequencies the

impedance plots, though similar, are not identical. This is due

to parasitic component value estimation errors the range of

about 30MHz to 100MHz. The additional resonances below

30MHz have been traced to changes in the gate drive circuit

from the model. Nevertheless, the critical frequencies match,

and the converter operates as expected.

Figure 12 shows the waveforms for the converter of Fig. 10.

Note the out of phase waveforms for the two drain voltages,

as expected. Note also that they are not completely identical,

which indicates that the circuit is not completely balanced;

nevertheless, it appears to tolerate the slight imbalance.

−20

0

20

40

60

80

Zeven,

[dB

Ω]

Even−mode impedance magnitude

60MHz →60MHz →

20 30 40 50 60 70 80 90 100 200−20

0

20

40

60

80

Zodd,

[dB

Ω]

F [MHz]

Odd−mode impedance magnitude

← 30MHz

90MHz →

← 30MHz

90MHz →

Meas

Sim

Fig. 11: Experimental and simulated push-pull Class EF2 drainimpedance plots. DC bias voltages set to 100VDC for the drain and50VDC for the rectifier.

The electrical performance of the prototype converter of

Fig. 10 was measured and results are given in Table II. Gate

power given is the difference of forward and reflected power.

Total efficiency ηTotal includes the effect of gate drive power;

drain efficiency ηDrain does not. Gate power was supplied

via an RF amplifier, and was calculated from the difference

of forward and reverse power.

660

TABLE II: Electrical performance of converter of Fig. 10 at two operating points.

VIN IIN VOUT IOUT PGATE PIN,DC PIN,Total POUT ηDrain ηTotal

[V] [A] [V] [I] [W] [W] [W] [W] [%] [%]

140.0 4.04 65.430 7.212 1.88 565.6 567.5 471.9 83.4 83.2150.1 4.48 65.575 8.391 1.7 672.4 674.1 550.2 81.8 81.6

Fig. 12: Waveforms of converter of Fig. 10. Chan. 1 trace (20V/div)shows Vgs drive waveform for one transistor. Chan. 2 and 3 traces(100V/div) show Vds for each for each transistor. Chan. 4 shows theoutput voltage (50 V/div). Chan. M1 (150 V/div) shows the drain-to-drain voltage Vdd. The time scale is 10 ns/div.

VI. CONCLUSION

A push-pull Class EF2 (Class Φ2) dc-dc power converter

topology suitable for operation in the VHF frequency range

has been proposed along with some considerations and ad-

vantages of the converter. The concept is verified via an

experimental 500 W, 150 VDC to 65 VDC converter with a

30 MHz switching frequency. This converter has an efficiency

> 81.5% at full power and > 83% at slightly reduced power.

The topic of efficient power processing with switching

frequencies in the VHF band is an area of open research. The

main goal of this paper is to extend the art of VHF power

stage topologies, and to experimentally demonstrate feasibility

at power levels of 0.1 to 1 kW. An additional goal is to

stimulate research into areas that need to be addressed. First,

the converter of this paper is a power stage only, without a

practical gate drive. Second, the design of such converters is

not very systematic and depends heavily upon the experience

of the designer. Third, it is an unregulated power stage, and

this needs to be addressed for widespread adoption. Finally,

the main goal of this work is not only to increase the power

density entitlement of power conversion, but to achieve this

benefit in practice. Although progress is being made on all

fronts, much work remains.

REFERENCES

[1] R. Erickson and D. Maksimovic, Fundamentals of Power Electronics.Springer, second ed., January 2001.

[2] C. Xaio, An Investigation of Fundamental Frequency Limitations for

HF/VHF Power Conversion. PhD thesis, Virginia Polytechnic Institute,July 2006.

[3] J. Kassakian and M. Schlecht, “High-frequency high-density convertersfor distributed power supply systems,” Proceedings of the IEEE, vol. 76,pp. 362–376, April 1988.

[4] D. Perreault, J. Hu, J. Rivas, Y. Han, O. Leitermann, R. Pilawa-Podgurski, A. Sagneri, and C. Sullivan, “Opportunities and challengesin very high frequency power conversion,” in Applied Power Electronics

Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual

IEEE, pp. 1–14, Feb. 2009.[5] B. J. Baliga, Power Semiconductor Devices. PWS Publishing Company,

1996.[6] N. Sokal and A. Sokal, “Class E-A new class of high-efficiency tuned

single-ended switching power amplifiers,” IEEE Journal of Solid-State

Circuits, vol. 10, pp. 168–176, June 1975.[7] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech

House Publishers, second ed., 2006.[8] F. Raab, “Class-f power amplifiers with maximally flat waveforms,”

Microwave Theory and Techniques, IEEE Transactions on, vol. 45,no. 11, pp. 2007–2012, 1997.

[9] F. Raab, “Maximum efficiency and output of class-f power amplifiers,”Microwave Theory and Techniques, IEEE Transactions on, vol. 49, no. 6,pp. 1162–1166, 2001.

[10] J. Glaser, J. Nasadoski, and R. Heinrich, “A 900w, 300v to 50v dc-dcpower converter with a 30mhz switching frequency,” in Applied Power

Electronics Conference and Exposition, 2009. APEC 2009. Twenty-

Fourth Annual IEEE, pp. 1121–1128, Feb. 2009.[11] Z. Kaczmarczyk, “High-efficiency class E,EF2, and E/F3 inverters,”

IEEE Transactions on Industrial Electronics, vol. 53, pp. 1584–1593,Oct. 2006.

[12] J. M. Rivas, Y. Han, O. Leitermann, A. Sagneri, and D. J. Perreault, “Ahigh-frequency resonant inverter topology with low voltage stress,” 2007

IEEE Power Electronics Specialists Conference (PESC 2007), pp. 2705–2717, June 2007.

[13] J. Rivas, Radio Frequency dc-dc Power Conversion. PhD thesis,Massachusetts Institute of Technology, September 2006.

[14] S. Kee, I. Aoki, A. Hajimiri, and D. Rutledge, “The class-e/f familyof zvs switching amplifiers,” Microwave Theory and Techniques, IEEE

Transactions on, vol. 51, no. 6, pp. 1677–1690, 2003.[15] H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio

Engineering. Wiley, first ed., 1980.[16] Z. Kaczmarczyk and W. Jurczak, “A pushpull class-e inverter with

improved efficiency,” Industrial Electronics, IEEE Transactions on,vol. 55, pp. 1871–1874, April 2008.

[17] R. Redl, B. Molnar, and N. Sokal, “Class E resonant regulated dc/dcpower converters: Analysis of operations, and experimental results at1.5MHz,” IEEE Transactions on Power Electronics, vol. 1, pp. 111–120, April 1986.

[18] J. Rivas, R. Wahby, J. Shafran, and D. Perreault, “New architectures forradio-frequency DC/DC power conversion,” in IEEE 35th Annual Power

Electronics Specialists Conference PESC 04, vol. 5, pp. 4074–4084, June2004.

[19] S.-A. El-Hamamsy, “Design of high-efficiency RF class-D power am-plifier,” IEEE Transactions on Power Electronics, vol. 9, pp. 297–308,May 1994.

[20] M. Kazimierczuk and J. Jozwik, “Resonant dc/dc converter with class-Einverter and class-E rectifier,” IEEE Transactions on Industrial Electron-

ics,, vol. 36, no. 4, pp. 468–478, 1989.[21] S. Lu, Y. Sun, M. Goldbeck, D. Zimmanck, and C. Sullivan, “30-

MHz power inductor using nano-granular magnetic material,” in Power

Electronics Specialists Conference, 2007. PESC 2007. IEEE, pp. 1773–1776, 2007.

[22] Microsemi Corporation, “ARF475FL Datasheet,” June 2007.[23] Microsemi Corporation, “ARF521 Datasheet,” February 2007.[24] R. Kielkowski, SPICE: Practical Device Modeling. McGraw-Hill

Professional Publishing, August 1995.

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