1626 IEEE TRANSACTIONS ON POWER ELECTRONICS, · PDF file1626 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 An Insight into the Switching Process of Power MOSFETs:

1626 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010

An Insight into the Switching Process of PowerMOSFETs: An Improved Analytical Losses Model

Miguel Rodrıguez, Student Member, IEEE, Alberto Rodrıguez, Student Member, IEEE,Pablo Fernandez Miaja, Student Member, IEEE, Diego Gonzalez Lamar, Member, IEEE,

and Javier Sebastian Zuniga, Member, IEEE

Abstract—The piecewise linear model has traditionally beenused to calculate switching losses in switching mode power suppliesdue to its simplicity and good performance. However, the use of thelatest low voltage power MOSFET generations and the continu-ously increasing range of switching frequencies have made it nec-essary to review this model to account for the parasitic inductancesthat it does not include. This paper presents a complete analyticalswitching loss model for power MOSFETs in low voltage switchingconverters that includes the most relevant parasitic elements. Itclarifies the switching process, providing information about howthese parasitics, especially the inductances, determine switchinglosses and hence the final converter efficiency. The analysis pre-sented in this paper yields two different types of possible switchingsituations: capacitance-limited switching and inductance-limitedswitching. This paper shows that, while the piecewise linear modelmay be applied in the former, the proposed model is more accuratefor the latter. Carefully-obtained experimental results, describedin detail, support the analytical results presented.

Index Terms—Losses, modeling, MOSFETs, switched modepower supplies.

I. INTRODUCTION

THE continuously increasing range of operating frequenciesin actual power converters has caused switching losses to

greatly determine the final performance of a design. On theone hand, switching losses can be accurately calculated us-ing physical simulation software or circuit simulations that usecomplete MOSFET models [1]; unfortunately, both methodsare quite time consuming, and the information required to ob-tain precise results is not always available for many designers.Besides, as each simulation only provides valid results for thecase under study, neither general conclusions nor a clear phys-ical insight into the switching process are easily obtained fromthese tools. On the other hand, analytical switching loss models(usually based upon certain simplifications) provide less accu-rate results, but enable the designer to make fast calculations,thus allowing almost immediate comparison between differentoperating conditions or between different semiconductor perfor-mances. Furthermore, analytical models also provide physical

Manuscript received June 23, 2009; revised November 3, 2009. Currentversion published June 4, 2010. This work has been supported by theSpanish Ministry of Science and Innovation under Grants AP2006-04777,AP2008-03380, and project TEC-2007-66917. Recommended for publicationby Associate Editor E. Santi.

The authors are with the Power Supply Systems Group, Department of Elec-trical and Electronic Engineering, University of Oviedo, Gijon 33204, Spain(e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2040852

insight into the switching process, allowing designers to acquirein-depth knowledge of the switching loss mechanisms.

The classical analytical model, or piecewise-linear model [2],is based on the assumption that MOSFET’s capacitances com-pletely determine its switching behavior. However, it does notaccount for parasitic inductances. The latest generation of low-voltage power MOSFETs exhibit an extremely good switchingperformance, mainly due to their low capacitances and increasedtransconductances; this key fact means that parasitic inductanceslimit the switching process in practice. The classical model thusneeds a review to account for the effect of these parasitics (ac-tual values for the parasitic inductances vary from around 15 nHin a classic TO-220 package to less than 1 n in the DirecFETpackage used by International Rectifier).

Several detailed models that include such parasitics have al-ready been proposed, including either a fully analytical treat-ment [3], [4] or a more empirical approach [5]. This issue hasalso been addressed in [6]– [8], but applied to a current sourceresonant driver. This paper presents an analytical loss modelfor power MOSFETs in actual low-medium voltage (< 40 V)switching converters that includes all the parasitics. It is ob-tained by solving the equivalent circuits during the switchingtransitions; all the approximations used are clearly stated, andthe solutions are presented in a relatively simple form. Themodel is easy to understand and provides a deep insight into theswitching process. The paper is organized as follows: first, themotivation and basis of the model are given. Then, the modeland the procedure employed to obtain all the waveforms arefully explained. Finally, the proposed model is compared to theclassical model and tested by means of several experiments.

II. MOTIVATION AND BASIS OF THE MODEL

Fig. 1(a) shows a synchronous buck converter. During switch-ing transitions, the output inductance L may be considered to bea current source, and the output capacitor C may be considereda constant voltage source. Such assumptions yield the circuit inFig. 1(b), from which the output voltage has been removed as itis in series with a current source. As the dead time control usedin synchronous buck converters causes the freewheeling diodeDf either to be conducting before the high-side MOSFET, HS,turns on or to start conducting after HS turns off, the low-sideMOSFET, LS, does not play any role during the switching tran-sitions, and it can be removed from the circuit. Furthermore, thesaid dead time forces LS to switch in zero voltage conditions,thus adding no extra losses. Thus, only HS has to be consideredin the switching loss analysis. After taking into account suchconsiderations and adding the parasitic capacitances of HS, the

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RODRIGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL 1627

Fig. 1. (a) Synchronous buck converter; (b) equivalent circuit for the switchingtransition; (c) intermediate circuit after the LS MOSFET has been removed andthe parasitic capacitances of HS have been added; (d) final equivalent circuitobtained from a rearrangement of elements in (c).

circuit in Fig. 1(c) is obtained. Finally, a rearrangement of theelements in Fig. 1(c) yields the circuit in Fig. 1(d). The sametransformations can easily be applied to boost or buck–boostconverters, yielding exactly the same final equivalent circuit; theonly difference is that the values of voltages and currents change(e.g., in the boost converter the voltage source value is Vout andthe current source value is Iin ). A synchronous buck converterwill be used in the following sections to present the model. Themajor advantage of this approach arises from a practical issue: ina conventional buck converter, conduction losses would maskswitching losses due to the high-conduction losses caused bythe freewheeling diode Df , thus hindering any laboratory mea-surement aimed at testing the proposed model. However, it isworth to comment that the analysis is still directly applicable toa conventional buck converter: the only special concern shouldbe that the model would become more difficult to verify due tothe aforementioned issues.

A. Range of Application of the Classical Model

The classical model has been widely used by power supplydesigners. It provides quite accurate results, especially bearingin mind its simplicity. It also provides a simple, comprehensiveapproach to the switching process. However, careful analysisof the model shows that it is based on the assumption that theswitching transitions are strongly determined by the parasiticcapacitances. Fig. 2(a) shows the typical turn-ON waveformsin the piecewise-linear model. First, the drain current increaseslinearly until reaching its final value Iout ; then, the drain-sourcevoltage drops to 0 V. The procedure is easy to understand: asthe freewheeling diode of Fig. 1(d) is initially forward biased,it forces the drain-source voltage to remain constant until theMOSFET carries all the output current. The turn-OFF process isvery similar, but the voltage increase takes place before the cur-rent drop. This switching behavior can be referred to as capaci-tance limited. Fig. 2(b) shows the equivalent circuit of Fig. 1(d)with an extra inductance in the drain terminal of the MOSFET.This inductance limits the drain current change rate, and thusnothing stops the drain-source voltage from changing before the

Fig. 2. (a) Typical turn-ON waveforms in the classical model; (b) equivalentcircuit with an extra parasitic drain inductance.

Fig. 3. (a) Simplified physical view of a power MOSFET; (b) simplified 3-Dview of the silicon die with the package.

current. In this situation, the assumptions of the classical modelare no longer valid.

B. Basis of the Proposed Model

The proposed model includes the most relevant parasiticspresent in actual power MOSFETs. Fig. 3(a) shows a simplifiedphysical view of a MOSFET. Three intrinsic parasitic capaci-tances are considered in this model: the gate-source capacitance,the gate-drain capacitance, and the drain-source capacitance. Asboth the drain-source capacitance and the gate-drain capacitanceare associated with a reverse-biased p-n junction, they changewith the applied voltage. This change is modeled by the follow-ing equation:

C (v) =C0(

1 +v

K

)γ (1)



Fig. 4. Equivalent MOSFET circuit including internal and major externalparasitics.

Fig. 5. Final equivalent circuit used to obtain the proposed model, along withthe electrical variables.

where K and γ are two adjustment parameters extracted fromthe capacitance versus voltage curve that can be found in thedatasheet of the MOSFET, and C0 is the 0 V capacitance value.The gate-source capacitance remains approximately constantregardless of the applied voltage.

The model also includes several parasitic inductances thatcan appear for different reasons. Fig. 3(b) shows the silicon dietogether with the MOSFET package. The pad parasitic induc-tances and the internal bondings between the silicon die and thepackage pads contribute to the total parasitic inductance. Currentpackaging technology tries to minimize such inductances by di-rectly connecting the die with almost noninductive pads, achiev-ing inductances as low as 0.1 nH [9]. The layout of the printedcircuit board also contributes slightly to the inductance.

Fig. 4 shows the equivalent circuit resulting from the previ-ous considerations. The final circuit model used to analyze theswitching process is shown in Fig. 5. All the parasitic induc-tances in series in each terminal of the MOSFET are added andthus represented as one single element. The gate circuit resis-tance Rg is made up of the gate driver equivalent resistance andan internal resistance due to the gate contact. The internal nodesare Gint , Dint , and Sint , while the final external nodes, whichinclude the effect of all the parasitic inductances are G, D, and S.

The procedure to obtain the model equations is as follows:first, the theoretical analysis is divided into two different stages,the turn-ON and turn-OFF transitions. Within each transition,different substages arise; these are treated separately. At the

beginning of each substage, the equivalent circuit with its cor-responding initial conditions is stated. Capacitance values arechosen using (1) in accordance with the initial voltage over thecapacitance at the beginning of the substage; though this pro-cedure might yield discontinuities at the substage boundaries, itwill provide more accurate results when calculating switchinglosses and the obtained waveforms will also be more meaningfulfrom a physical point of view. The time-domain equations of theequivalent circuit are then obtained and solved using Laplacetransforms. Once the drain current and the internal drain-sourcevoltage are known, switching losses are calculated in terms ofenergy by integrating the product of those waveforms, and thenthe energy is multiplied by the switching frequency fsw . In cer-tain substages, it is possible to obtain equations that allow theenergy losses to be directly found (without an integration pro-cedure). Tables I and II summarize all the relevant equations.

As the final conditions of one substage are used as the initialconditions for the following, and to simplify the use of Laplacetransforms, the state variables are chosen such that their initialcondition is zero in each substage. Mathematically, x′ beinga state variable, then x′ (t = 0) = 0. The initial conditions areincluded in the circuits and in the corresponding equations asindependent voltage sources (for the capacitances) or currentsources (for the inductances), but are not drawn in most of theequivalent circuits for the sake of clarity. The actual voltagesand currents in the circuits (electrical variables) are noted withan apostrophe, while the state variables are noted without theapostrophe. It is straightforward to find one from the other

x′ (t) = x (t) + x′ (0) . (2)

Furthermore, the initial time is chosen as zero at the beginningof each substage.

The ultimate goal of this paper is to obtain relatively sim-ple and handy analytical expressions of voltage and currentwaveforms that enable the designer to easily calculate switch-ing losses using a conventional spreadsheet. A simple modelfor MOSFET behavior must be used to achieve such objective.Thus, the MOSFET is considered to be a resistance, an opencircuit or a dependent current source in all the analytical cal-culations presented in this paper. The behavior as a dependentcurrent source (controlled by the voltage between Sint and Gint)is described by (3).

ichannel = gm

(v′

gs − VTH)

(3)

gm and VTH being the MOSFET transconductance and thethreshold voltage, respectively. Obviously, modeling MOSFETbehavior using (3) provides results with limited accuracy. How-ever, its use provides a physical insight into the switching pro-cess that would be very difficult to obtain if more complicatedexpressions were used.

III. TURN-ON TRANSITION

The equivalent circuit at the beginning of the turn-ON tran-sition is shown in Fig. 6. As the freewheeling diode is forwardbiased, the voltage Vin is applied over the MOSFET equiva-lent circuit and its parasitics. A detailed analysis of this circuitleads to the four different substages described in the followingsections.



TABLE ISUMMARY OF LOSS CALCULATIONS DURING TURN-ON

A. Substage I

During substage I, the gate-source equivalent capacitance ischarged until it reaches VTH . As the MOSFET is open circuited,approximately no drain current flows in the circuit and the drain-source voltage remains constant. Thus, only the gate circuit mustbe considered. The equivalent circuit is shown in Fig. 7. Theinitial conditions for the electrical variables are:

i′g (0) = 0 (10)

v′gs (0) = 0 . (11)

From the circuit in Fig. 7, the following equations areobtained:

Vg =(

Lg +LsLd

Ls + Ld

)digdt

+ igRg + vgs (12)

ig = (Cgs + Cgd)dvgs

dt. (13)

Applying Laplace transforms to (12) and (13) and solving forvgs yields

vgs (s) =1s

Vg

LeqCeqs2 + RgCeqs + 1(14)

Leq and Ceq now being

Leq =(

Lg +LsLd

Ls + Ld

)Ceq = (Cgs + Cgd) .

The inverse Laplace transform of (14) is shown in Table I as(4). The current ig can be obtained from (12) and (13), followingthe same procedure. This current, as shown in Table I as (5), isused to calculate the initial current for the following substage.As the MOSFET is not activated, there is no power loss duringthis period, except for the losses in the gate drive circuit that areincluded as a separate term in the final loss calculations.



TABLE IISUMMARY OF LOSS CALCULATIONS DURING TURN-OFF



Fig. 6. Equivalent circuit at the beginning of the turn-ON transition.

Fig. 7. Equivalent circuit during substage I.

Fig. 8. Equivalent circuit during substage II.

B. Substage II

When vgs reaches VTH , the MOSFET channel starts conduct-ing. Equation (3) then applies, and the channel current is directlyproportional to Vgs − VTH . Fig. 8 shows the equivalent circuitfor this substage.

The initial conditions are:

v′gs (0) = VTH (24)

v′gd (0) = Vin − VTH (25)

v′ds (0) = Vin (26)

i′d (0) = 0 (27)

i′g (0) = i′s (0) = Ig 1 (28)

with Ig 1 being the initial current in the gate circuit.

A total of seven differential equations can be obtained fromthe circuit in Fig. 8, one for each state variable in the circuit(yielding six equations) and (3) being the seventh. This set ofdifferential equations can be reduced to four by eliminating threestate variables: the current through the source inductance is , thechannel current ichannel , and the voltage across the gate-draincapacitance vdg . The remaining set of equations is

Vg − Vth = (ig + Ig 1) Rg

+ Lgdigdt

+ vgs + Ls

(diddt

+digdt

)(29)

0 = vds + Lddiddt

+ Ls

(diddt

+digdt

)(30)

Cgsdvgs

dt= ig + Ig 1 + Cgd

(dvds

dt− dvgs

dt

)(31)

id = Cgd

(dvds

dt− dvgs

dt

)+ Cds

dvds

dt+ gm vgs . (32)

As this set of equations is, in general, coupled, a simple an-alytical solution cannot be easily found. However, consideringthe typical values of the capacitances and transconductances inmodern low-voltage power MOSFETs, it can be concluded thatthe channel current will increase very fast, rapidly discharg-ing the drain-source capacitance. The parasitic inductances stopthe drain current from increasing, thus allowing Cds to be dis-charged by the channel current. The drain current id and itsderivatives can be neglected.

Equation (34) is no longer needed, and the other three equa-tions are uncoupled. Thus, the remaining set of equations canbe solved to find voltages and currents in a simple form. UsingLaplace transforms, vgs (s) is obtained as

vgs (s) =1s

· Vg − Vth + Ig 1Leqs

s2 (LeqCeq) + s (RgCeq + (M − 1) (Leq/Rg )) + M(37)



Fig. 9. Equivalent circuit during substage III.

with M , Leq and Ceq now being

M = 1 + RggmCgd

Cgd + Cds

Leq = Lg + Ls Ceq = Cgs +CgdCds

Cgd + Cds.

The inverse Laplace transform of (37) is shown in Table I as(6). The drain-source voltage state variable can also be obtainedby applying Laplace transforms to vds

vds (s) =gm

s2 (Cgd + Cds)

· (Vg − Vth + Ig 1Leqs) (s(Cgd/gm ) − 1)s2(LeqCeq) + s (RgCeq +(M −1) (Leq/Rg ))+M

. (38)

The inverse Laplace transform of (38) is shown in Table I as(7). The power loss during this substage has to be found by in-tegrating the product ichannelvds . The end of this substage takesplace when the drain-source voltage reaches approximately 0 V.

If the input voltage were higher than a few tens of volts, Vdswould not reach 0 V, but would tend to reach an intermediatevoltage. As the present analysis is limited to input voltagesbelow approximately 40 V, this situation is not considered andVds will drop to 0 V in most practical situations.

C. Substage III

After the drain-source voltage reaches approximately 0 V,the MOSFET starts behaving as a resistor. Fig. 9 shows theequivalent circuit. The initial condition is

i′d (0) ≈ 0 . (39)

Thus, the drain current is approximately determined by theinput voltage source and the parasitic inductances

i′d ≈ Vin

Ld + Lst . (40)

Once again, the state variable id and the actual drain current i′dare the same. As this substage lasts for a short period of time andRds,ON is usually very low, switching losses can be neglected.This substage finishes when the drain current reaches the outputcurrent.

D. Substage IV

This substage, which is usually called the reverse recoveryperiod, has been extensively analyzed in [3]. When the draincurrent reaches the output current, the reverse recovery period

Fig. 10. Equivalent circuits during substage IV. The initial current through theinductances has been drawn as an independent current source: (a) equivalentcircuit at the beginning of substage IV; (b) equivalent circuit after an appropriaterearrangement of elements in (a); (c) equivalent circuit when the freewheelingdiode becomes capable of blocking voltage, i.e., when the drain current hasreached its maximum value Ip eak ; (d) equivalent circuit after an appropriaterearrangement of elements in (c).

begins. Fig. 10(a) shows the equivalent circuit at the beginningof this period. The freewheeling diode is unable to block reversevoltage until a certain amount of charge has been removed fromits junction. Thus, the drain current increases until it reaches acertain peak current Ipeak ; at this moment, the charge has beenremoved from the diode junction and it becomes capable ofblocking reverse voltage. Fig. 10(c) shows the equivalent circuitat this moment, CD being the equivalent freewheeling diodecapacitance. A resonant period then begins, at the end of whichthe capacitance is charged to Vin and the current through theinductance is Iout once again.

Fig. 11 shows the definition of the reverse recovery charge Qrrand the reverse recovery time trr , under common test conditions.The reverse recovery charge is the total charge that has to beprovided to the diode junction until the voltage across it reachesits steady-state value and the current through the diode drops to0 A. The charge provided to the equivalent diode capacitanceduring the resonant period is hence included in the term Qrr .This is the major difference between the present analysis andpreviously presented results.

The energy stored in the circuit at the beginning of substageIV is

EL =12

(Ls + Ld) I2out (41)

ECD= 0 . (42)



Fig. 11. (a) Test circuit for reverse recovery charge and reverse recovery time.At time t0 , when the forward current through the diode is IF , switch S1 opensand switch S2 closes; (b) current through the diode.

When the current reaches Ipeak , the energy stored in theinductance is

EL,peak =12

(Ls + Ld) I2peak . (43)

The energy provided by the voltage source during said periodis

EV i n = VinQrr,1 (44)

with Qrr,1 being the part of Qrr that is removed from the diodebefore the current reaches Ipeak . Thus, the energy loss is

Eloss,1 = VinQrr,1 −12

(Ls + Ld)(I2peak − I2

out)

. (45)

During the resonant period, the energy stored in the induc-tance changes from 1

2 (Ls + Ld)I2peak to 1

2 (Ls + Ld)I2out , so the

net energy provided to the inductance during the whole substageis zero. The energy loss during the resonant period is

Eloss,2 = VinQrr,2 −12CD V 2

in

+12

(Ls + Ld)(I2peak − I2

0)

(46)

with Qrr,2 being the part of Qrr that is needed to charge theequivalent parasitic diode capacitance once it is able to blockreverse voltage. The second term in (46) stands for the finalenergy stored in the diode parasitic capacitance. The total energyloss is thus given by (47)

Eloss = Eloss,1 + Eloss,2 = Vin (Qrr,1 + Qrr,2) (47)

− 12CD V 2

in = VinQrr −12CD V 2

in .

As CD depends on the applied voltage, (47) can be rewritten as

Eloss = VinQrr −12QD Vin (48)

with QD being the total charge supplied to the diode junction;this charge can be calculated integrating the capacitance versusvoltage graph.

Noteworthily, significant reverse recovery parameters arevery difficult to calculate; for instance, Qrr strongly dependson Iout and on the rate of change of the current, see, e.g., [10].If the freewheeling diode is a Schottky diode, which suffersalmost no reverse recovery effects, then (47) becomes

Eloss = Vin

Q r r︷︸︸︷(VinCSchottky)

− 12CSchottkyV 2

in =12CSchottkyV 2

in (49)

with CSchottky being the Schottky diode equivalent capacitance.

E. Example Waveforms

Fig. 12 shows a set of example waveforms provided by themodel, using typical MOSFET parameters. Fig. 12(a) showsthe drain to source voltage and the channel current, as wellas the instantaneous power in the channel, during the first threesubstages (the reverse recovery substage has not been included).It can be seen that, as long as the reverse recovery process isnot taken into account, significant power loss only takes placeduring substage II, which lasts for a relatively short period. Thus,the model suggests that, when an inductance-limited switchingtakes place, there are small turn-ON losses. Furthermore, asstated in [11], there is no need to include the rather arbitraryoutput capacitance loss term, 1

2 CdsV2in . Fig. 12(b) shows the

gate to source voltage; it can be seen that the Miller effect takesplace during substage II, and that it is predicted by the analyticalmodel. The gate to source voltage is essentially equal to that ofthe classical model and to the waveforms found in conventionalMOSFET datasheet.

IV. TURN-OFF TRANSITION

The equivalent circuit at the beginning of the turn-OFF tran-sition is shown in Fig. 13. As the freewheeling diode is reversebiased, the current Iout circulates through the MOSFET and theparasitic inductances. A detailed analysis of this circuit leads tothe five different substages described in the following sections.

A. Substage I

The gate circuit discharges the gate-source equivalent capac-itance. Fig. 14 shows the equivalent circuit during this period.The initial conditions are

v′gs (0) = Vg (50)

i′g (0) = 0 . (51)



Fig. 12. (a) Turn-ON example waveform (the reverse recovery period is notincluded). The sudden change in the channel current is a consequence of theapproximations that were made during the analysis; (b) gate to source voltageexample waveform. The Miller effect takes place during substage II and causesthe actual channel current waveform.

Fig. 13. Equivalent circuit at the beginning of the turn-OFF transition.

From the circuit in Fig. 14, the following equations can beeasily obtained:

−Vg = (Lg + Ls)digdt

+ igRg + vgs (52)

ig = (Cgs + Cgd)dvgs

dt. (53)

Using Laplace transforms, vgs is found

vgs (s) = −1s

Vg

LeqCeqs2 + RgCeqs + 1(54)

Leq and Ceq now being

Leq = Lg + Ls Ceq = Cgs + Cgd .

Fig. 14. Equivalent circuit during substage I.

Fig. 15. Equivalent circuit during substage II.

The inverse Laplace transform of (54) is shown in Table IIas (15). The current ig can be obtained from (52) and (53), fol-lowing the same procedure. This current, as shown in Table IIas (16), is used to calculate the initial current for the follow-ing substage. Even though the MOSFET is carrying the outputcurrent, this period lasts for a short time and the losses can beneglected.

Substage I finishes at a time t1 , when the MOSFET enters intothe linear region, where (3) applies. Thus, t1 can be calculatedas

vgs (t1) = −Vg + VTH +Iout

gm. (55)

B. Substage II

Fig. 15 shows the equivalent circuit during this period. Thechannel current suddenly decreases, thus causing the excesscurrent Iout − ichannel charging the MOSFET capacitances. Theinitial conditions are

v′gs (0) = VTH +

Iout

gm(56)

v′dg (0) = −

(VTH +

Iout

gm

)(57)

v′ds (0) ≈ 0 (58)

i′g (0) = −Ig 2 (59)

i′d (0) = Iout (60)

i′s (0) = Iout − Ig 2 (61)

with Ig 2 being the initial current in the gate circuit.



The circuit equations are the following:

0 = (ig + Ig 2) Rg + Lgdigdt

− vgs −(

VTH +Iout

gm

)+ Ls

diLs

dt(62)

vds = vgs + vgd (63)

ig + Ig 2 + Cgsdvgs

dt= Cgd

dvgd

dt(64)

Iout − Cdsdvds

dt= ichannel + Cgd

dvgd

dt(65)

ig + is = 0 . (66)

These equations can be solved directly using Laplace transformsto find vgs

vgs (s) = −1s

· sLeqIg 2 + (Vth + (Iout/gm ))LeqCeqs2 + (RgCeq + (M − 1) (Leq/Rg )) s + M

(67)

with M , Leq , and Ceq being the same as in Section III-B

Leq = Ls + Lg Ceq = Cgs +CdsCgd

Cds + Cgd

M = 1 + RggmCgd

Cgd + Cds.

Applying the inverse Laplace transform to (67) yields (17)in Table II. The results are very similar to those obtained inSection III-B. The drain-source voltage can be obtained from(62)–(66) using the same procedure. The result is shown inTable II as (18). This period ends when the drain-source voltagereaches Vin . The channel current could reach 0 A before thatmoment; such a situation will be addressed in Section IV-F.

C. Substage III

At the beginning of this substage, v′ds has reached Vin and the

freewheeling diode becomes forward biased. Fig. 16(a) showsthe equivalent circuit during this period. The initial conditionsare

i′d (0) = Iout (68)

i′s (0) ≈ Iout (69)

ichannel (0) = Ich,∞ (70)

v′ds (0) = Vin . (71)

As the drain inductance impedes a sudden change in the draincurrent, the drain-source voltage continues increasing. It is as-sumed that the gate voltage remains constant during this period,and as does the channel current. The latter can be approximated

Fig. 16. (a) Equivalent circuit during substage III; (b) intermediate circuitobtained by changing the position of the current sources; (c) final equivalentcircuit during substage III.

using (67) and the final value theorem

Ich,∞ = limt→∞

ichannel = limt→∞

gm Vgs (t)

= lims→0

svgs + VTH +Iout

gm

=Iout (M − 1) − VTHgm

M. (72)

In this substage, the initial conditions have been representedby independent voltage and current sources in the circuit inFig. 16(a); instead of solving the circuit equations, a rearrange-ment of these sources easily yields the circuit in Fig. 16(c).

Fig. 16(c) shows that the final equivalent circuit is a simpleparallel resonant circuit. As the current and voltage waveformsin this circuit are oscillating, it seems clear that the proposedapproximation is valid as long as the substage lasts for a timeshorter than half a resonant period. vds is easily found fromFig. 16(c)

v′ds (t) = Vin + (Iout − Ich,∞) Ldω0 sin (ω0t) (73)

with ω0 being

ω0 =1√

(Ls + Ld) Cds. (74)

This substage ends when the drain current reaches the chan-nel current Ich,∞. At this moment, the drain-source voltage hasreached its peak voltage Vds,peak . This value can easily be cal-culated once t3 is known.

Vds, peak = v′ds (t3) . (75)

D. Substage IV

During this period, the drain current continues decreasingtoward zero, forced by the voltage difference that exists between



Fig. 17. (a) Equivalent circuit during substage IV; (b) equivalent circuit forthe resonant turn-OFF stage (substage V).

Vds, peak and Vin . As the current that charged Cds to Vds, peakwas the difference between the drain and the channel current,there will not be a high amount of current to change Vds duringthis period. Thus, Vds is considered to remain approximatelyequal to Vds, peak during this substage. In order to simplify theanalysis, the channel current is assumed to decrease as if itwere controlled by the voltage source Vin , instead of by thegate-source voltage. The power loss can thus be obtained as

Ploss =∫

Vdsichanneldt ≈ Vds, peak

∫ichanneldt . (76)

Fig. 17(a) shows the equivalent circuit. Thus, the channelcurrent can be approximated as

ichannel (t) = Ich,∞ − Vds, peak − Vin

Ls + Ldt . (77)

E. Substage V

A resonant stage begins when the channel current reaches0 A; the MOSFET stops conducting current and becomes anopen circuit. The gate circuit continues discharging Cgs andCgd more or less independently from the rest of the circuit.At the same time, the resonant circuit formed by Ls + Ld andCds starts oscillating until it reaches its steady-state value. Theequivalent circuit is shown in Fig. 17(b). R stands for the equiv-alent resistance that dumps the oscillations, which is mainlymade up of the circuit tracks high-frequency resistance and theparasitic inductance and capacitance high-frequency equivalentresistances.

The loss calculations during this substage are identical tothose in Section III-D. Once again, losses can be calculated byconsidering the energy stored at the beginning and the end ofthe substage. The energy stored at the beginning is

EL = 0 (78)

EC,i =12Cds (Vds, peak)

2 . (79)

The energy stored at the end of the period is

EL = 0 (80)

EC,f =12CdsV

2in . (81)

Fig. 18. Turn-OFF example waveform.

The energy provided by the voltage source is

EV in = VinCds (Vin − Vds, peak) (82)

an equation that shows that some energy has been returned tothe input source. Finally, the energy loss is

Eloss = EV in − (EC,f − EC,i)

=12Cds

(V 2

peak + V 2in

)− CdsVpeakVin . (83)

The latter expression is the same as the one obtained in [3].

F. Substage III: Drain Current Drops to Zero Before vdsreaches Vin

As previously stated in Section IV-B, the channel currentcould drop to 0 A during substage II, thus causing a sudden endof said substage. This is likely to happen if Iout is relativelysmall. In that case, the MOSFET becomes open circuited andthe analysis is straightforward; switching losses during the restof the turn-OFF transition can be approximated by consideringthat all the energy stored in the parasitic inductances is lostduring the resonant period

Eloss ≈12

(Ls + Ld) I2out . (84)

Equation (84) neglects the voltage difference between Vds andVin at the moment when this substage begins.

However, as the switching losses given by (84) are noticeablysmaller than in the normal switching transition, this case is ofminor relevance.

G. Example Waveforms

Fig. 18 shows a set of example waveforms provided by themodel, using typical MOSFET parameters. As the gate to sourcevoltage provided by the model is again essentially equal to whatcan be found in a conventional MOSFET datasheet, it has notbeen included in this section. It can be seen in Fig. 18 thata noticeable power loss occurs during the turn-OFF transition,especially in comparison with the turn-ON. Thus, the modelsuggests that turn-OFF switching losses are much higher thanturn-ON switching losses.

This fact can be easily explained taking into considerationthe effect of the parasitic inductances: these limit the current



Fig. 19. Comparison between the losses provided by the proposed model andthe classical piecewise–linear model [2].

change rate during turn-ON, thus inducing an almost zero-current-switching transition. Conversely, during the turn-OFF

transition, the inductances lengthen the duration of the process,thereby causing an increase in the losses.

V. COMPARISON WITH THE CLASSICAL PIECEWISE-LINEAR

MODEL

Fig. 19 shows a comparison between the results provided bythe classical model (extracted from [2]) and the proposed model.It is apparent that the classical model yields higher losses duringturn-ON than the proposed model, whereas during turn-OFF theopposite happens and the classical model yields smaller lossesthan the proposed model.

However, there is a “compensation effect” between these twoerrors that leads to the final losses not being very different fromone model to another. This coincidence means that the classicalmodel is still very useful, but only when the switching process isnot inductance limited: in that case it yields inaccurate results,as is shown in Section VI. The proposed model clearly indicatesthat turn-OFF losses are much higher than turn-ON losses in theinductance-limited case.

From a designer’s point of view, it is interesting to establish anapproximate boundary between the region where the classicalmodel can be reliably applied (capacitance-limited switching)and the region when the proposed model should be used be-cause the effect of parasitic inductances cannot be neglected(inductance-limited switching). The classical model states thatthe turn-ON time is

tturn−on =QswitchingRg

Vth + (Iout/gm )(85)

with Qswitching being the total switching charge that has tobe transferred into the gate-drain capacitance during the Millereffect period, the value of which is usually given in the datasheet.Thus, the current increase through Ld during the estimated turn-ON time can be compared with the output current Iout ; if thelatter is much smaller than the former, Ld will not be able to limitthe current rate of change and the switching will be capacitancelimited. On the contrary, if Iout is much bigger than the currentincrease through Ld , then Ld will limit the current rate of change

Fig. 20. LM3152 demo board.

and its effect should be taken into account. Both conditions arestated in (86) and (87):

Iout <<tturn−onVin

2Ld⇒ capacitance limited (86)

Iout >>tturn−onVin

2Ld⇒ inductance limited. (87)

A comprehensive differentiation of these two cases can alsobe found in [12].

VI. EXPERIMENTAL RESULTS

To experimentally test the proposed model, several labora-tory measurements were conducted. First, the efficiency of asynchronous buck converter was measured and compared withthe data provided by the proposed model. A National Semicon-ductor LM3152 demo board switching at 500 kHz (see Fig. 20)was used. As not enough reverse recovery data are given inthe datasheet of the MOSFETs (RJK0305), a Schottky diodewas connected in parallel with the low-side MOSFET. Thus,(49) can be used to estimate the losses during substage IV of theturn-ON transition. Conduction losses of both MOSFETs and thediode were fully taken into account and calculated using con-ventional equations (e.g., in the case of one of the MOSFETs,the expression i2rmsRds,ON was used, irms being the root meansquare current through the MOSFET); power losses in input andoutput capacitances and in the control circuitry were also con-sidered, as well as the increase of the MOSFETs on-resistancewith operating temperature.

The results are shown in Fig. 21(a) and (b). It can be seen thatthe model provides accurate results and that the trend followedby experimental data is clearly reproduced by the model. Switch-ing losses account for approximately 25% of the total amountof losses in this experiment. There is a certain amount of un-certainty in the efficiency results provided by the model mainlycaused by the uncertainty in the current ripple of the demo boardoutput inductance and by the reverse recovery losses that maystill be existing in the circuit.

A second experiment was carried out to minimize these un-certainties. A synchronous buck converter switching at 1.3 MHzwas built using RJK0305 MOSFETs and an LM2727 controller.Several changes were made with respect to the previously de-scribed experiment. First, the switching frequency was increasedto give more weight to switching losses against other loss terms.Second, a very small inductor (≈300 nH) was used to obtain a



Fig. 21. (a) Experimental and model results (Vin = 6 V); (b) experimentaland model results (Vin = 12 V).

very high current ripple. The effect of reverse recovery losseswas thus diminished, because the inductor current at the turn-ON instant was much smaller than the current at the turn-OFF.Moreover, the high current ripple allowed us to have less aver-age output current while maintaining a high turn-OFF current,thus achieving lower conduction losses and giving more weightto switching losses. As core losses were also another source ofuncertainty, a coreless inductor was used. The output voltageripple was kept small by incrementing the output capacitance(≈ 150 µF) and by using several low-equivalent series resis-tance capacitors. Third, the current through the inductor wasmeasured using a current transformer built with a small toroid.Fig. 22 shows the prototype. Switching losses were more than30% of total losses with this setup.

Two different sets of measurements were made: first, the ef-ficiency was measured and compared to the results provided bythe classical model and the proposed model; second, a smalldrain inductance was added to the circuit and the efficiency wasmeasured again. Fig. 22 shows how the inductance was achievedin practice: the decoupling capacitors were separated about1 cm from their previous position. The current loop that causesthe inductance was thus made longer and the inductance wasincreased. The layout was measured by a precision impedanceanalyzer before and after the change. The measurements yieldedan extra inductance of approximately 10–15 nH.

Fig. 22. Prototype with the small coreless inductance and different positionsof decoupling capacitors in the layout used to achieve the extra drain inductance.

Fig. 23. (a) Comparison between the experimental data and the results pro-vided by the models with decoupling capacitors in position 1 (see Fig. 22);(b) comparison between the experimental data and the results provided by themodels with decoupling capacitors in position 2.

Fig. 23 shows a comparison between the experimental resultsobtained and the results provided by the classical and the pro-posed model. Fig. 23(a) demonstrates that both the classical andthe proposed model can approximately reproduce the measuredefficiency when decoupling capacitances are in position 1; i.e.,when the parasitic inductance is minimized. An error of nearlyone point can be appreciated in the results: as the exact values ofmost of the parameters are not precisely known, it is very diffi-cult to achieve more accuracy using datasheet values, regardlessof the model being used.

Fig. 23(b) shows the results when the decoupling capacitorsare in position 2. It is apparent that, as the classical model does



Fig. 24. Breakdown of total losses provided by the model.

Fig. 25. Detailed breakdown of total losses (Iout ,average = 7 A).

not take into account any inductance, its results were notice-ably different from the measured data. In contrast, the proposedmodel was able to reproduce the experimental efficiency.

Fig. 24 shows the breakdown of losses provided by the pro-posed and the classical model. These values were used to obtainthe results, as shown in Fig. 23. The influence of each con-tribution can be clearly appreciated: as stated, the contributionof switching losses to the total losses was above 30%. Fig. 25shows the detailed contribution of each loss term when the av-erage output current was 7 A. Yet again, the contribution ofswitching losses to the total losses can be clearly noticed, alongwith the higher contribution of the turn-OFF term in all operatingconditions. Furthermore, the extra drain inductance (the capac-itance in position 2) only increased the turn-OFF losses, whilethe rest of the terms remained constant.

VII. CONCLUSION

This paper has presented a new detailed switching model forpower MOSFETs, which allows switching losses to be calcu-lated. It has been shown that although the classical model is

very useful and provides relatively accurate results, it may notprecise enough in actual synchronous buck converter designsif their switching process is inductance limited. The proposedmodel takes into account the major circuit parasitics, especiallyinductances, providing analytical solutions for the waveformsand enabling the designer to create a simple spreadsheet toestimate switching losses. All the equations required for losscalculations are summarized in Tables I and II.

Furthermore, the model provides a clear physical overviewof the switching process and shows the effect that the differentparasitics of the transistor and the circuit have on this process.For instance, it shows that the turn-ON and the turn-OFF tran-sitions are quite different in nature. This paper has shown, viacarefully planned experimental measurements, that the modelprovides quite accurate results. It has also demonstrated that theclassical model, though very useful and accurate, has certain ap-plication limits; the proposed model is intended to provide betterresults than the classical model in such situations. The condi-tions in which each model should be used have also been stated,clearly differentiating between capacitance-limited switchingand inductance-limited switching.

The experimental results have also shown that it is very diffi-cult to accurately predict the efficiency, regardless of the modelbeing used, mainly due to the uncertainty that exists when de-termining the value of most of the parameters. For instance,both the proposed and the classical model are very sensitive tothe MOSFET threshold voltage and the transconductance. Asthe operating conditions in which these parameters are given inthe datasheet may not match actual working conditions, and alsogiven that each parameter has its own variation range withineach MOSFET, a certain deviation in the model predictionsis almost unavoidable. Furthermore, the values of the para-sitic capacitances change with the voltage applied across them,while the parasitic inductances change with the frequency ofoperation.

It is however worth pointing out that, even though the use ofanalytical models cannot provide results as accurate as, e.g., aphysical simulation software, a relatively precise prediction canbe made and tested by carefully planned setups, as this paperhas shown.



REFERENCES

[1] T. Lopez and R. Elferich, “Quantification of power MOSFET losses in asynchronous buck converter,” in Proc. IEEE Appl. Power Electron. Conf.,2008, pp. 1594–1600.

[2] J. Klein, “Synchronous buck MOSFET loss calculations with Excelmodel,” Appl. note AN–6005, Fairchild Semicond. version 1.0.1,, Apr.2006.

[3] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of powerMOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310–319,Mar. 2006.

[4] S. Clemente, B. R. Pelly, and A. Isidorf, “Understanding HEXFET switch-ing performance,” The HEXFET Designers Manual, Application note 947,pp. 85–98, published by International Rectifier, EL Segundo, CA, 1993.

[5] W. Eberle, Z. Zhang, Y. Liu, and P. C. Sen, “A practical switching lossmodel for Buck voltage regulators,” IEEE Trans. Power Electron., vol. 24,no. 3, pp. 700–713, Mar. 2009.

[6] Z. Zhang, W. Eberle, Z. Yang, Y. Liu, and P. C. Sen, “Optimal design ofresonant gate driver for Buck converter based on a new analytical lossmodel,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 653–666, Mar.2008.

[7] Z. Yang, S. Yen, and Y. Liu, “A new dual-channel resonant gate drivecircuit for low gate drive loss and low switching loss,” IEEE Trans.Power Electron., vol. 23, no. 3, pp. 1574–1583, May 2008.

[8] Z. Zhang, W. Eberle, P. Lin, Y. Liu, and P. C. Sen, “A 1-MHz high-efficiency 12-V Buck voltage regulator with a new current-source Gatedriver,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2817–2827, Nov.2008.

[9] M. Pavier, A. Sawle, A. Woodworth, R. Monteiro, J. Chiu, and C. Blake,“High frequency DC-DC power conversion: The influence of packageparasitics,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), 2003,vol. 2, pp. 699–704.

[10] B. Tien and C. Hu, “Determination of carrier lifetime from rectifier ramprecovery waveform,” IEEE Electron Device Lett., vol. 9, no. 10, pp. 553–555, Oct. 1988.

[11] Y. Xiong, S. Sun, H. Jia, P. Shea, and Z. J. Shen, “New physical insights onpower MOSFET switching losses,” IEEE Trans. Power Electron., vol. 24,no. 2, pp. 525–531, Feb. 2009.

[12] L. Gorgens, “Maximizing the effect of modern low voltage power MOS-FETs,” in Proc. Appl. Power Electron. Conf., 2009, Professional EducationSeminars, vol. II, Seminar 8, pp. 65–95.

[13] M. Eaglin, “LM3152–3.3 demonstration board datasheet,” National Semi-conductor, Sep. 2008.

[14] R. Eriksson and D. Maksimovic, Fundamentals of Power Electronics.Boston, MA: Kluwer, 2001, ISBN 0–7923–7270–0.

[15] N. Mohan, Power Electronics: Converters, Applications and Design.New York: Wiley, 2003, ISBN 0–4712–2693–9.

Miguel Rodrıguez (S’06) was born in Gijon, Spain,in 1982. He received the M.S. degree in telecommuni-cation engineering from the Universidad de Oviedo,Spain in 2006, where he is currently working towardthe Ph.D. degree in the Department of Electrical andElectronic Engineering (granted by the Spanish Min-istry of Science and Education under the Formacionde Profesorado Universitario Program).

His research interests include dc/dc conversion,high-frequency power conversion, and power-supplysystems for RF amplifiers.

Alberto Rodrıguez (S’07) was born in Oviedo,Spain, in 1981. He received the M.S. degree intelecommunication engineering in 2006 from theUniversity of Oviedo, Gijon, Spain, where he is cur-rently working toward the Ph.D. degree.

In 2006, he was a Telecommunications Engineerwith the Government of the Principality of Asturiasand an Assistant Professor with the Department ofElectrical Engineering, University of Oviedo. Since2007, he has been working in University of Oviedo atfull time. His current research interests include bidi-

rectional dc–dc power converters.

Pablo Fernandez Miaja (S’07) was born in Oviedo,Spain, in 1984. He received the M.S. degree intelecommunication engineering in 2007 from theUniversity of Oviedo, Gijon, Spain, where e is cur-rently working toward the Ph.D. degree.

His work is funded by the Spanish Ministry ofScience and Technology to study dc–dc convertersto feed RF power amplifiers. His current researchinterests include dc–dc converters, digital control ofswitching power supplies and techniques to increasethe efficiency of RF power amplifiers like envelope

tracking.

Diego Gonzalez Lamar (M’05) was born inZaragoza, Spain, in 1974. He received the M.Sc. andPh.D. degrees in electrical engineering from the Uni-versidad de Oviedo, Gijon, Spain, in 2003 and 2008,respectively.

In 2003, he was a Research Engineer at the Univer-sity of Oviedo, where he has been an Assistant Pro-fessor since September 2005. His current researchinterests include switching-mode power supplies,converter modeling, and power-factor-correctionconverters.

Javier Sebastian Zuniga (M’87) was born inMadrid, Spain, in 1958. He received the M.Sc. degreefrom the Polytechnic University of Madrid, Madrid,Spain, and the Ph.D. degree from the University ofOviedo, Gijon, Spain, in 1981 and 1985, respectively.

He was an Assistant Professor and an Asso-ciate Professor at both the Polytechnic University ofMadrid and at the University of Oviedo. Since 1992,he has been with the University of Oviedo, where heis currently a Professor. His research interests includeswitching-mode power supplies, modeling of dc-to-

dc converters, low-output voltage dc-to-dc converters, and high-power-factorrectifiers.


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