201O International Conference on Mechanical and Electrical Technology (ICMET 2010)

Implementation of Micro Controller and Reconfigurable Logic Co-Design for Low

Latency Control

Priyashraba Misra

School OfInterdisciplinary Science And Technology International Institute OfInformation Technology

Pune, India pmisra1986@gmail.com

Prof. Amit Patwardhan

School OfInterdisciplinary Science And Technology International Institute Of Information Technology

Pune, India amitp@isquareit.ac.in

Mr. Bhushan Patil

School OfInterdisciplinary Science And Technology International Institute Of Information Technology

Pune, India bhushanp@isquareit.ac.in

Abstract - Complex Programmable Logic Device (CPLD), the simplest hardware for implementing reconfigurable logic, and Micro controller have their specific advantages when implemented in their own domains. Most of the modern

electronics circuits are implemented either only on CPLD or on Micro controller. If studied carefully, there are ways to implement both CPLD and controller on a single control circuit and use the advantages of both to the maximum. The field of Co-Design is about 10 years old!l]. The paper elaborates the implementation of such a design.

KeyWords - CPLU41, Micro controllel51, Shift Register.

I. INTRODUCTION

Controllers are implemented for 2 basic purposes : Control System and General Purpose 10. On the other hand, CPLD is widely used to implement Digital logic design, both sequential and Combinational. Some of the most commonly used digital logics, like Gates and Shift Registers have been designed as Integrated Chips but they have their limitations. Frequency or Speed of execution of CPLD is much more than digital logic implementation on I.C. The main aim should be to maintain low latency. For testing, it has been implemented on a 3-D LED matrix.

II. THEORY OF LED DISPLAY: POV

LED displays are one of the most common display systems for public displays because they are very cheap and lifetime of a LED is very long. So they can keep on working continuously for a very long time. The principle behind working of these displays is based on the concept of "Persistence Of Vision".

"Persistence of Vision" is the phenomenon of human eye by which an image is retained in the retina for approximately one twentieth of a second (1I20th sec or 50 milliseconds). Although controversies surround the exact

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time for which the image is retained in our eyes, it has been a very widely accepted phenomena. Most of the film systems, Monitors and cartoon animation is based on this phenomena.

This concept is implemented here by switching all the LEDs that are needed to display a particular letter or number within 50 milliseconds and it is not necessary that all the LEDs should be switched on simultaneously. If we switch all the LEDs one by one and the total time taken to switch them on and off is less than 20 ms ( much less than 50 ms, to be on the safer side), then all the LEDs appear to be ON at any given instance. But only one of them or a single layer is on at a given instance. Modem theatrical films run at 24 frames per second. So that can be considered as a very safe rate.

From the above discussion it can be concluded that if there are at least 24 different sub patterns that can be switched continuously in a circular manner to display a required pattern then flickering dose not occur.

III. DRIVER REQUIREMENTS AND SPECIFICTIONS

The driver circuit for LED displays are hardware specific and the design depends on the type of display what we want to drive. The following specifications were considered while designing: The LED matrix to be driven is a 3-D (8 x 8 x 8) alphanumeric display.

• Each layer has 64 LEDs (8 x 8) with a common anode connection, driven by a transistor for each layer.

• All the LEDs in a vertical column (8 Nos) have a common Cathode.

2010 International Conference on Mechanical and Electrical Technology (ICMET 2010)

•

•

•

•

LEOs

To Controller

Figure 1. Connection of LED Matrix

Current requirements for one layer is (64 x 10 rnA) = 640 rnA, as each red LED takes approximately lOrnA of current. Number of controller pins need for switching layers is 8 and for controlling individual LED of each layer is 64. i.e. total 72 pins Transistors can be used at the cathode for sourcing current as the controller is not capable of providing such a large current. The Layers are switched from the controller directly and the 64 cathodes go to the CPLD.

IV. THE CONVENTIONAL CONTROLLER BASED DESIGN

. The simplest design can be implemented using only a

smgle controller (Atmel Mega8) along with some Shift registers. The most commonly used shift register is 74HC595 , a Serial-In-Parallel-Out, 8 Bit shift register. It can also be cascaded in series with a number of 74HC595 as it also gives a serial output. One 74HC595 uses 3 pins of the controller, i.e. Data pin, Serial Clock and Buffer Enable. But when cascaded only the leading 74HC595 needs 3 pins where as others need only 2 pins on the controller. As each of the shift registers have a serial out data line that can be connected to the successive IC. This has a demerit of consuming a huge space on the board as we use 1 AtMega8 and 8 74HC595. Apart from this we take 8 pins from the controller directly to the transistors controlling the layers. Alternatively, we can use I shift register fot the layers also.

This is the reason we move to a CPLD - Micro Controller Co-Design. We are saving pins on the micro controller and later they can be used for doing additional stuff. We save space on the PBC. Moreover, most of the ICs are standardized and hence work according to a set of rules defined originally by the manufacturer where as by implementing that part on reconfigurable platform we can customize it exactly as per our requirements and hence provide flexibility to the design. The controller based implementation is shown in Fig 2.

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Figure 2. Controller based design

V. CPLD - MICRO CONTROLLER CO-DESIGN

A. The Controller Advantage

Programming and Controlling of a Micro controller is done by 'Embedded C' programming which very closely resembles the conventional ANSI C. The Speed of the Controller used , AtMega8 can go up to 16 MHz when driven using an external crystal oscillator. This provides enough speed to shift data to the LEDs through the shift registers.

B. The CP LD Advantage

Sequential circuits can be designed on a CPLD very effectively and tested even before burning the CPLD. So the CPLD design is more precise and assured. A CPLD works with the help of functional blocks that are present in it. Each functional block and each array of AND and OR gates can be connected for designing a desired system .. For driving our �lardware we need a 64 Bit shift register that can be easily Implemented on a CPLD. A large amount of space is saved on the board. The working of the shift register can be verified on the test bench.

c. CP LD - Controller Co-Design Circuit

Both the CPLD and Controller work in tandem. Both are driven by their own clock pulses but the controller signal synchronizes the working of both the systems. The Co­Design schematic for driving the matrix has been shown in Fig 3. The Co-design architecture consists of a Controller and a CPLD. The controller directly controls the switching of layers by switching the transistors. Where as the patterns that were shifted through the shift registers to the cathodes in the controller based design will now be shifted with the help

2010 International Conference on Mechanical and Electrical Technology (ICMET 2010)

of the 64-Bit Shift Register that has been implemented on the CPLD.

AtMega8

To Transistors For driving layers

Data XC9572 CPLD

Clock 64-Bit Shift Register

Figure 3. Co-Design Implementation

The CPLD works on it own frequency of 3.2 MHz but the shift register dose not follow the CPLD clock. It has been synchronised to work with a clock that is manually generated by the controller and given to the CPLD as an input. By this we can control the rate of data flow in the shift register by varying the time period of the clock.

Data

Clock

Data

Figure 4. Data and Clock Signal Generated By Controller

Figure 5. Output of CPLD Shift Register

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The hardware implementation has been shown below.

Figure 6 . Hardware Implementation

VI. CONCLUSION

The Co-design architecture can be very useful for large control systems where there is limitation in space for designing the control circuit. The implementation can be extended to a FPGA in place of CPLD and the reconfigurable power of FPGA can be explored to a great extend. This logic can also be implemented at places where more than one control logics are needed but only one or two work at a given instance.

REFERENCE

[I] G. Bosman, "A Survey of Co-Design Ideas and Methologies" [2] Slim Ben Saoud, Andreas Gerstlauer and Daniel D. Gajski, "Codesign

Methodology of Real-time Embedded controller for Electromechanical Systems "

[3] Marek Wegrzyn, "The application of reconfigurable logic to controller design ", Department of Physics & Astronomy, University College London

[4] Data Sheet: XC9572XL High Performance CPLD [5] Data Sheet: Atmega8 [6] Pong P. Chu, "FPGA Prototyping by VHDL Examples"