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N-Phase Sensor-less Current Sharing Digital Controller

Jaber A. Abu Qahouq* and Lilly Huang**

*The University of Alabama Department of Electrical and Computer Engineering

Tuscaloosa, Alabama 35487, USA

**Intel Corporation Corporate Technology Group

Hillsboro, Oregon 97124, USA

Abstract- An N-Phase sensor-less current sharing digital controller algorithm and architecture for multiphase power converter is presented in this paper. It demonstrates the visibility of sensor-less current sharing implemented for buck converter with more than two-phases. The presented N-phase sensor-less current sharing controller eliminates the need for current sensing for the current sharing loops and the need for Analog-to-Digital converters for phase current sampling when digital controllers are used. The presented currentsharing controller operation is discussed and verified with experimental results obtained from a four-phase proof of concept prototype.

I. INTRODUCTION

Current sharing loop is important in multiphase andparalleled converters in order to maintain appropriate current sharing among converter phases for efficient, reliable and stable operation [1-8, 18].

In [18], a Sensor-Less Current Sharing (SLCS) method was introduced and it results in achieving the optimum current sharing between converter phases without the need to sense phase currents information. The method was discussed and implemented with two-phase digital controller algorithm. This sensor-less current sharing method eliminates the need to current sensing [9-13], and therefore, removes associated drawbacks such as the impact of sensing inaccuracies, the effect of components aging, the additional sensing components, and the need for off-line calibration. It also eliminates the need for Analog-to-Digital Conversion (ADC) of sensed phase currents when digital controller [14-18] is used.

The method is based on the observation that the optimum current distribution in a multiphase converter can be achieved by minimizing the difference between the duty cycles of converter phases. In a converter with a single voltage mode closed loop, this can be achieved by minimizing the closed loop compensator error signal (duty-cycle command) ripple or the difference between phases’ duty-cycles [18].

In this paper, the sensor-less current sharing proposed in [18] is extended with a new N-phase current sharingalgorithm. The proposed N-Phase SLCS allows for optimum current distribution among converter phases. It is implemented in multiphase buck converter with a complete closed loop digital controller where there is no need for current sensing and sampling.

Next section briefly reviews the SLCS method and its two-phase controller algorithm and implementation. Section III introduces the N-phase SLCS controller and algorithm and discusses its operation and structure. The N-phase SLCS proof of concept prototype and experimental work and results are presented in Section IV and the conclusion is given in Section V.

II. REVIEW OF THE SLCS METHOD

It was discussed and shown in [18] that SLCS can beachieved by forcing the differences between phases’ duty cycles to be at the minimum value. This will force the current sharing ratio or distribution between converter phases to be optimum for improved conversion efficiency.

Two-phase implementation and controller flowchart were discussed in [18] as shown in Fig. 1 and Fig. 2. Fig. 3 from [18] demonstrates how the Current Sharing Ratio (CSR) between phases affects both the power conversion efficiency and the phases’ duty cycles for different non-ideal mismatch degrees between phases in different power stage components. It can be observed from Fig. 3 that the maximum efficiency occurs when the difference between phases’ duty cycles is at the minimum value, and therefore the optimum %CSR of the load current can be obtained.

The two Current Sharing Coefficients (CSC), 1σ and

2σ are adjusted by the two-phase SLCS controller in a

direction (increase or decrease) which will result in minimized difference between the duty cycles of converter phases under voltage-mode closed-loop control.

978-1-4244-1668-4/08/$25.00 ©2008 IEEE

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2σ

1σ

Fig. 1: Two-phase sensor-less current sharing controller of [18]

1( ) ( )Sign Dt Sign σ= Δ

( 1) ( )Dt n Dt n− =

1 1( 1) ( )n nσ σ− =

1σ

1 1 1( ) ( 1)n nσ σ σΔ = − −

2 11σ σ= −

1 2Dt D D= −

( 1) ( )Dt Dt n Dt nΔ = − −

eDt DΔ <

1σ2 11σ σ= −

Fig. 2: Basic two-phase sensor-less current sharingcontroller algorithm flowchart of [18]

Fig. 3: Efficiency and phases’ duty-cycles vs. Current Sharing Ratio for different mismatched cases at 30oI A= .

III. N-PHASE SLCS CONTROLLER AND ALGORITHM

Fig. 4 shows an N-phase DC-DC buck converter topology with the proposed SLCS controller block diagram. Thephases’ duty-cycles or the compensated error signal (duty cycle command) is used as an input to the SLCS controller which outputs and adjusts the N-phase Current Sharing Coefficients (CSC), 1σ through Nσ .

Fig. 5 shows the proposed N-phase SLCS controller basic algorithm. This algorithm partially works in similar fashion as the algorithm shown in Fig. 2, where it minimizes the difference between phases’ duty cycles or minimizes the compensated error signal ripple. However, in Fig. 5 algorithm, the variables x and y are defined to control

which two-phases duty-cycles ( 1D , 2D , …, ND ) and current

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sharing coefficients ( 1σ , 2σ , …, Nσ ) are being adjusted for

the N-phases.

Su1

Sl1

Lo1

CoVin

Drivers Latches

D1

Su2

Sl2

Lo2

Drivers Latches

D2

Io

+

-

Vo

Vref

Compensation

N-Phase Sensor-Less

Current Sharing Controller

Vo_senseVe

Ve2

Ve1

Vo_sense

Controller

Modulator 1

Modulator 2 2σ

1σ

Su�

Sl�

LoN

Drivers Latches

DN

Phase 1

Phase 2

Phase �

Ve�Modulator N Nσ

D1'’ D2'’ DN'’

D1'

D2'

DN'

Fig. 4: N-Phase buck converter with the proposed Sensor-Less digital Current-Sharing controller block diagram

Initially, 1x = and 2y = so that 1σ and 2σ are adjusted

until minimum 1 2D D− is achieved for phase 1 and phase 2.

The defined _up counter and the _down counter variables

are used to count how many times the current sharing coefficients are incremented/decremented. Once bothcounters are larger than a constant e , this indicates that the algorithm is oscillating around the optimum values of the two current sharing coefficients being adjusted. At this condition, the x and y variables are incremented to 2x =

and 3y = so that 2σ and 3σ are adjusted until minimum

2 3D D− is achieved for phase 2 and phase 3, and so on in

similar fashion for N phases in a multiphase converter.

Calculate

( ) ( )xSign Dt Sign σ= Δ

Start

( 1) ( )Dt n Dt n− =( 1) ( )x xn nσ σ− =

Increment xσ

NoYes

Calculate

( ) ( 1)x x yn nσ σ σΔ = − −

1y xσ σ= −

Decrement

Wait Certain Number of switching

Cycles

Dt Dx Dy= −

( 1) ( )Dt Dt n Dt nΔ = − −

xσ1y xσ σ= −

Initialize1, 2x y= =

Increment Increment _up count _down count

Does

and

?

_up count e>

_down count e>

No

1,

0 ,

x if x Nx

if x N

+ <⎧= ⎨

≥⎩1,

0 ,

y if y Ny

if y N

+ <⎧= ⎨

≥⎩

Yes

_ 0up count =_ 0down count =

Fig. 5: Proposed N-Phase Sensor-Less Current-Sharing

digital controller basic algorithm

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By the defining the following as shown in Fig. 5:

1,

0 ,

x if x Nx

if x N

+ <⎧= ⎨

≥⎩

1,

0 ,

y if y Ny

if y N

+ <⎧= ⎨

≥⎩

The algorithm sweeps between all phases’ CSC, optimizing two adjacent phases at a time, in a fashion that keeps one of the last two coefficients that were optimized and replacing the other one by another phase coefficient. For example, if 4N = , and if in the current algorithm cycle we have 3x = and 4y = in order to adjust phase 3 and

phase 4 current sharing coefficients, in the next cycle, after both counters being larger than e , we would have 4x = and

1y = , to adjust phase 4 and phase 1 current sharing

coefficients (note that phase 4 current sharing coefficient is adjusted in two consecutive algorithm cycles, and same for the other phases). This method allows the effect of every phase on the other phases to be accounted for in the optimization process.

IV. PROOF OF CONCEPT EXPERIMENTAL WORK

A proof of concept prototype is designed and built in the laboratory for initial verification. It consists of a four-phase DC-DC buck converter power stage with a voltage mode digital closed loop controller implemented in FPGA.

The hardware description is as follows:

Power Stage: - Four-phase DC-DC buck converter, 12inV V= ,

0.85oV V= .

- Output Inductor: 1 2 315o oL L nH= = per phase.

- Output Capacitors: 560 10Fμ × aluminum

polymers and 22 18Fμ × ceramic.

- Upper FET: NTD40N03R, two in parallel. - Lower FET: NTD85N02R, two in parallel. - FETs Driver: ADI3418K, 12V. - Switching frequency: 150swf kHz= per phase.

Digital Controller: - FPGA part: Xilinx Virtex 4. - Output Voltage ADC: ADI9215, 10-bit, 30M

sample/sec. - Voltage Closed Loop: Type III Compensation. - 13-bits DPWM. - Proposed N-phase SLCS controller

From the preliminary test of the prototype, the proposed controller operation has been successfully tested.

The design of phases and layout was with intention to achieve symmetry between all phases. Fig. 6(a) shows the inductor current waveforms at no-load condition without current sharing loop and Fig. 7(a) shows the inductor current waveforms at 20A load condition without current sharing loop. It can be observed that even though that the design is intended to be symmetric, there is current mismatch between the four converter phases when no current sharing loop is used with the voltage mode closed loop controller.

Fig. 6(b) shows the inductors current waveforms at no-load condition with the N-phase SLCS current sharing loop and Fig. 7(b) shows the inductors current waveforms at 20A load condition with the N-phase SLCS current sharing loop. It can be observed that the N-phase SLCS controllerconverged and significantly improved the current distribution between converter phases.

As a result of improved the current distribution between phases, the efficiency is improved and the reliability of the converter is improved. Furthermore, eliminating the ADCs that are required to sense the phase currents and the other associated components result in saving additional power loss, size, and cost.

(a)

(b)

Fig. 6: Experimental phase inductor current waveforms at no-load: (a) without current sharing loop, and (b) with the

N-phase SLCS controller.

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(a)

(b)

Fig. 7: Experimental phase inductor current waveforms at 20A load: (a) without current sharing loop, and (b) with the

N-phase SLCS controller.

V. CONCLUSION

The paper presents an N-phase Sensor-Less Current Sharing (SLCS) controller and algorithm that can be used with any number of phases. This extends the two-phase algorithm previously proposed. It allows achieving optimum current sharing between N-phases without the need for phases’ current sensing and sampling.

The N-Phase SLCS controller block diagram and operation are discussed and experimentally tested using a proof of concept prototype. Preliminary experimental results presented in this paper verified the proposed algorithm. Further experimental work and study are under the way.

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