Abstract—This paper concentrates on the dynamic behavior of pulse-width-modulator (PWM) and the time-delay introduced in the modulation process is highlighted. In order to describe this effect, we derive a time-delay model, based on which the closed-loop stability of current-mode control is studied and a novel interpretation of the subharmonic oscillation is presented. Compared to its existing counterpart, the proposed model exhibits the following superiorities: (a) possesses a simpler mathematical expression; (b) gives more physical insight into the sample and hold effect of current loop; (c) provides a better prediction of the critical condition of the current loop stability without slope compensation in engineering practice. This novel time-delay model is validated by simulation results.

I. INTRODUCTION

he current-mode control is superior to the voltage mode control in many aspects [1]-[4]. However the subharmonic oscillation occurs when duty-ratio exceeds

0.5 [4]-[6] and slope compensation is generally required to stabilize the current loop [7]-[8]. The modeling of current-mode control is a task of great importance but also challenging. An elegant small-signal model was proposed by Ridley [9]-[10], the key of which is the equivalent sample-hold-effect block in the feedback path. Ridley’s model has been well-accepted in the past decade of further studies [10]-[13].

Aiming to propose an alternative approach, this paper first reviews the time-delay model of PWM derived in voltage-mode control [14], then performs the extension to current-mode control, based on which the current loop is analyzed. Both qualitative and quantitative relations between the closed-loop stability, subharmonic oscillation and the PWM time-delay effect are revealed, which are supported by simulation results. Finally we discuss the similarities and discrepancies between the proposed model and its counterpart of Ridley’s. The Advantages are highlighted.

Manuscript received June 29, 2008; revised July 18, 2008.This work was supported by the National High Technology Research and Development of China 863 Program (2006AA05Z211).

Zhiyu Xu (phone: 86-21-6598-4898, fax: 86-21-6598-4898, e-mail: xuzhiyu@yahoo.cn) is the corresponding author. All the authors are currently with the School of electronics and information engineering, Tongji University, Shanghai 201804 China.

Weisheng Xu (email: xuweisheng@mail.tongji.edu.cn)Youling Yu (email: yuyouling@mail.tongji.edu.cn)Qidi Wu was with the Ministry of education of People’s Republic of

China.

II. TIME-DELAY MODEL OF PWM IN VOLTAGE-MODE CONTROL

As shown in Fig.1, there is only the voltage feedback .in voltage-mode control. Duty-ratio d is determined by the comparison of the sawtooth waveform and the control voltage vc, which is the amplified error of voltage reference vr and the feedback voltage vf. PWM transfers vc to d.

Fig.2 illustrates the time-delay between vc perturbation and the system response in the form of adjusting d [14]. Thus, PWM in voltage-mode control is modeled as

s

secm e

TSsvsdsF τ−== 1

)(ˆ)(ˆ

)( (1)

where Se is the slope of the sawtooth waveform, Ts is the switching period. The value of is to be studied.

The variable t when vc perturbs is a continuous random variable. i.e.

[ ] 21002121 ,,,)()( ttTttttttPttP s <+∈∀=== (2)

A Study on the Stability of Current-Mode Control Using Time-Delay Model of Pulse-Width-Modulator Zhiyu Xu, Weisheng Xu, Youling Yu, and Qidi Wu

T

eS

τ

sDT sdT

sTd̂

sT sT

cv̂

cv

cV

Fig. 2. Time-delay introduced by PWM in voltage-mode control

rv

fv cv

d

ovgv

Fig. 1. Scheme of voltage-mode controlled boost DC/DC converter

1432

978-1-4244-1787-2/08/$25.00 c© 2008 IEEE

where t0 is the beginning of any switching cycle. Therefore has a uniform distribution

[ ]sT,0~ Uτ (3) The probability density function of is

≤≤=

else,0

0,1)( s

s

TTf

ττ (4)

The expected value of is

2211)()(

0

2

00s

T

s

T

s

T TT

dT

dfs

ss =⋅=== τττττττE (5)

The time-delay model of PWM in voltage-mode control

[ ]sT

s

sem e

TSsF

,0~

1)(Uτ

τ ⋅−

⋅= (6)

III. TIME-DELAY MODEL OF PWM IN CURRENT-MODE CONTROL

Fig.3 shows that in current-mode control there is an additional current loop inside the outer voltage loop. The duty-ratio is no longer an independent variable but is controlled by the inductor-current iL.

Assume each variable only perturbs in the small-signal limit, Fig.4 illustrates that the duty-ratio plays a decisive role in the stability of current loop, which is one of the most important issues of current-mode control.

Similar as (1), the time-delay model of PWM operating in current-mode control is

( ) [ ]sT

s

snecm e

TSSsvsdsF

,0~

1)(ˆ)(ˆ

)(Uτ

τ ⋅−

⋅+== (7)

where Sn is the rising slope of iL. Notice that the PWM model presented in [9], [15] only has the same term of the static gain.

IV. MODEL AND STABILITY OF CURRENT LOOP

Employing the equivalent model of power stage [16], the open-loop transfer function of current loop is

[ ]sT

s

sen

fniimop e

sTSSSS

RsFsFsG,0~

1)()()(Uτ

τ ⋅−

++

== (8)

where Sf is the falling slope of iL.Let Se = 0, i.e. without slope compensation. Since

DD

SS

n

f

−=

1 (9)

we have

( ) [ ]sT

s

sop e

sTDsG

,0~1

1)(Uτ

τ ⋅−

−= (10)

The characteristic function is ( )

[ ]sT

ss esTD

,0~1

Uττ ⋅−+− (11)

Then we could investigate the PWM time-delay effect on the stability of current loop.

A. Quadratic approximant using the mean value of For the sake of simplicity, we first consider the mean value

of and make the quadratic approximation of the exponential term.

( ) 22

0

2)(E

821

2!1 sTsTTk

ee ss

k

ks

ksTs

s

+−≅−==∞

=

−− τ (12)

Eq.(11) reduces to a second-order polynomial of s with Das the parameter.

0121

82

2

=+−+ sTDsTs

s (13)

Obviously, the necessary and sufficient condition to stabilize the system is D < 0.5. However, Fig.5 shows that the accuracy of the quadratic approximant degrades within one decade of the switching frequency. So it’s required to

τ

sDT sdT

sTd̂

sT sT

cv̂

cv

nS fS

eS

cV

(a) Current loop is stable when D < 0.5

τ

sDT sdT

sTd̂

sT sT

cv̂

cv

nSfS

eS

cV

(b) Current loop is unstable when D exceeds 0.5 Fig.4. Illustration of the stability of current loop.

rv

fvcv d

ovgv

Fig.3. Scheme of current-mode controlled boost DC/DC converter

2008 Asia Simulation Conference — 7th Intl. Conf. on Sys. Simulation and Scientific Computing 1433

investigate the exact function of the exponential term if we are interested in the high-frequency characteristics.

B. Exact function and the varying The complex equation (10) is divided into

( )

[ ]−=−−=∠

=−

=

sop

sop

TjG

TDjG

,0~,2

)(

11

1)(

Uτπωτπω

ωω (14)

Define the frequency ratio

sffr = (15)

and the time-delay ratio

sTk τ= (16)

Thus

( ) 121

1)( =−

=rD

jGop πω (

17a)

[ ]1,0~,22

)( UkrkjGop πππω −=−−=∠ (17b)

Obviously D only affects the magnitude and k determines the phase. Each k corresponds to a frequency where the phase-shift is and the magnitude should not be above 0 dB. Solve (17) yields

kDπ21max −= (18)

Since k ~ U [0, 1], k = 1( = Ts) should be taken into account to guarantee stability in the worst case, so

3634.021max ≅−=π

D (19)

That means the slope compensation could be needed to stabilize the current loop when duty-ratio exceeds 0.36, which is indicated in [17], but with no theoretical explanation provided. Fig. 6 indicates that the increasing k compresses the varying space of D, i.e. the larger k is, the smaller D could be so as to maintain the stability of current loop.

V. DISCUSSION

This section performs a comparison study on Ridley’s model and proposed time-delay model (shown in Fig.7). The essential similarities are revealed.

Ridley’s model [4], [9], [10] simplifies PWM as a gain block

( ) snem TSS

F⋅+

= 1 (20)

The sample and hold effect of current-mode control is represented by an equivalent block in the feedback path

1)(

−= ⋅ sTs

se e

sTsH (21)

On the other hand, the proposed time-delay model describes PWM as the combination of two terms, one is static and the other is dynamic.

cv Lid+− ( ) sne TSS +1

iF

iR1−ssTs

esT

(a) Ridley’s model

cv Lid+− ( ) [ ]sT

s

sne

eTSS

,0~

1

Uτ

τ−

+ iF

iR

(b) Proposed time-delay model Fig.7. Comparison of two models of current loop

10-4

10-3

10-2

10-1

100

-20

0

20

40

60

80

Ma

gn

itud

e(d

B)

10-4

10-3

10-2

10-1

100

-450

-360

-270

-180

-90

0

Ph

ase

(deg

)

Frequency ratio (f/fs)

duty-ratio increases

time-delay increases

D = 0

D = 0.4

D = 0.6

D = 0.8

D = 0.2

k = 0

k = 0.25

k = 0.50

k = 0.75

k = 1k = τ/Ts

Fig.6. Bode plot of open-loop transfer function

10-5

10-4

10-3

10-2

10-1

100

-5

0

5

10

15

Mag

nitu

de(d

B)

10-5

10-4

10-3

10-2

10-1

100

-200

-150

-100

-50

0

Pha

se(d

eg)

Frequency ratio (f/fs)

exact functionquadratic approximant

exact functionquadratic approximant

Fig. 5. Bode plots of exponential term and its quadratic approximant

1434 2008 Asia Simulation Conference — 7th Intl. Conf. on Sys. Simulation and Scientific Computing

Consider the mean value of , Ridley’s model and the time-delay model have the intrinsic similarity.

Let s = j ,

)sin(1)cos(11 ss

sTj

ssT

s

TjTTj

eTj

esT

ss ωωωω

ω +−=

−=

−

)2

(

2sin

2 s

s

sT

T

Tω

ω

ω

−∠= (22)

)2

(1)2

sin()2

cos(2)(E ssssT TTjTee

s ωωωτ −∠=−+−==−− (23)

Eq.(22) and (23) represent the same phase-frequency characteristic and a similar magnitude-frequency characteristic especially at low frequencies, since

1

2sin

2lim0

2

=→

s

s

T

T

sTω

ω

ω

(24)

Table I summarizes the comparison of the two models.

TABLE I COMPARISON OF RIDLEY’S MODEL AND TIME-DELAY MODEL

Ridley’s model Time-delay modelExact function

Quadratic approximant

Math expression

1−⋅ sTss

esT 2

2

2

21 s

Ts

T ss

π+− [ ]sT

se,0~Uτ

τ ⋅−

Location feedback path forward pathDerivation inverse computation analytical inferenceRemarks a) accurate and practical in

engineering b) verified by decades of researches c) widely accepted as a standard in this field

a) solid basis of physical meaning b) novel interpretation

of subharmonic oscillation

c) precise prediction of critical stability.

VI. CONCLUSION

This paper studies the modeling and stability issues of the current-mode controlled DC-DC converter. Unlike the well-known Ridley’s model, which views the PWM as a static gain block, the dynamic behavior is emphasized and the time-delay introduced in modulation process is highlighted. The sample and hold effect of current loop is included in the time-delay model of PWM. Employing this model, the stability of current loop is analyzed on both quadratic approximant and exact function of the exponential term. A novel interpretation of the subharmonics oscillation is presented and the accurate prediction of the critical duty-ratio to stabilize the current loop in engineering practice is derived. Comparison shows that the time-delay model has the essential similarity to its counterpart of Ridley’s, especially at low frequencies. However due to its rigorous analytical derivation, the time-delay model gives deeper physical insight into the origin of the sample and hold effect so that should be more reasonable.

REFERENCES

[1] M. Hartman, “Inside Current-Mode Control,” National Semiconductor technical report, Available: http://www.national.com/appinfo/power/files/PowerDesigner_106.pdf.

[2] C. Deisch, “Simple switching control method changes power converter into a current source,” in Proc IEEE Power Electron. Specialists Conf.,June 13-15, 1978, Syracuse, NY, USA, pp. 300-306.

[3] F. D. Tan and R. D. Middlebrook, “A unified model for current-programmed converters,” IEEE Trans. Power Electron., vol.10, no.4, pp. 397-408, July, 1995.

[4] R. B. Ridley, “Current Mode or Voltage Mode,” Switching Power Magazine, vol.1, pp.4-9, Oct, 2000.

[5] G. C. Verghese, C. A. Bruzos and K. N. Mahabir, “Averaged and sampled-data models for current mode control: a re-examination,” in Proc IEEE Power Electron. Specialists Conf., June 26-29, 1989, Milwaukee, WI, USA, pp. 484-491.

[6] I. Zafrany and S. Ben-Yaakov, “A chaos model of subharmonic oscillations in current mode PWM boost converters,” in Proc. IEEE Power Electron. Specialists Conf., June 18-22, 1995, Atlanta, GA, USA, pp. 1111-1117.

[7] H. D. Venable, “Current Mode Control,” Venable Instrument Inc. Tech. Paper TP-05, Available: http://www.venable.biz/tp-05.pdf.

[8] C. C. Yang, C. Y. Wang and T. H. Kuo, “Current-Mode Converters with Adjustable-Slope Compensating Ramp,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems, Dec. 4-7, 2006 pp. 654-657.

[9] R. B. Ridley, “A new, continuous-time model for current-mode control,” IEEE Trans. Power Electron., vol.6, no.2, pp. 271-280, April, 1991.

[10] B. Bryant and M. K. Kazimierczuk, “Modeling the closed-current loop of PWM boost DC-DC converters operating in CCM with peak current-mode control,” IEEE Trans. Circuits Syst. I: Regular Papers, [See also IEEE Trans. Circuits Syst. I: Fundam Theory and Appl],vol.52, no.11, pp. 2404-2412, Nov., 2005.

[11] Y. F. Liu and P. C. Sen, “A general unified large signal model for current programmed DC-to-DC converters,” IEEE Trans. Power Electron.,vol.9, no.4, pp. 414-424, July, 1994.

[12] E. A. Mayer and R. J. King, “An improved sampled-data current-mode-control model which explains the effects of control delay,” IEEE Trans. Power Electron., vol.16, no.3, pp. 369-374, May, 2001.

[13] E. A. Mayer, “Using modified z-transforms to model the dynamics of the peak current-mode controlled buck converter,” in Proc. IEEE Int. Conf. Electro/Information Technology, May 17-20, 2007, Chicago, IL, USA, pp. 447-452.

[14] Z. Y. Xu, W. S. Xu, Y. L. Yu and Q. D. Wu, “A Dynamic Small-Signal Model of the Constant-Frequency Pulse Width Modulator of Switching Converters,” in Proc 8th Int. Conf. Solid-State and Integrated-Circuit Technology, Oct. 25-26, 2006, Shanghai, China, pp. 1468-1470.

[15] M. K. Kazimierczuk, “Transfer function of current modulator in PWM converters with current-mode control,” IEEE Trans. Circuits Syst I: Fundam Theory and Appl, [see also IEEE Trans. Circuits Syst I: Regular Papers], vol.47, no.9, pp. 1407-1412, Sept., 2000.

[16] V. Vorperian, “Simplified analysis of PWM converters using model of PWM switch. Continuous conduction mode,” IEEE Trans. Aerosp. Electron. Syst., vol.26, no.3, pp. 490-496, May, 1990.

[17] R. B. Ridley, “A More Accurate Current-Mode Control Model,” Unitrode Seminar Handbook, SEM-1300, Appendix A2, Available: www.ridleyengineering.com.

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