Idesa Rf Lecture8 Kuzmicz 20080514

IDESAImplementation of widespread IC design skillsin advanced deep submicron technologiesat European Academia

Advanced RF implementation flow90nm design verification22 May 2008Wieslaw Kuzmicz - Warsaw University ofTechnology, Warsaw, Poland

Copyright StatementThe development of this material was funded by the EuropeanCommunity through the 7th Framework Program.

This material can be used in the curricula of regular master courses atEuropean academia. Use for commercial benefit is prohibited.

Wieslaw Kuzmicz - Warsaw University of Technology

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Outline

Verification goals and flowsCircuit extraction for post-layout simulation– Basic concepts– Parasitic extraction– Special casesDesign Rule Checking and Design for Manufacturability– Design Rules and Checks– Recommended rules for DfMLayout postprocessing and mask preparation

Goal of this presentation: discussion of design verificationtechniques, with special emphasis on realistic post-layoutsimulation and on layout verification issues in DSMtechnologies


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Chip verification 15 years ago…

Formal verification– DRC– Nominal circuit extraction, ERC and LVS

Functional verification– Circuit extraction with parasitics– Post-layout simulation

and now

Verification of manufacturability and DfM– New classes of design rules

• recommended rules• additional restrictions

– Layout postprocessing• Modifications for CMP, layer density rules• Resolution enhancement techniques: OPC, PSM, SRAF

complexity: 10x more rules

2D->3D, extraction for RFnew complex device models


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Analog verification and chip finishing - the old way

DRC

OK?

Extraction, ERC and LVS

Parasitic extraction and post-layout simulations: nominal, atPVT corners, Monte Carlo

Circuit and layout design

Pad ring, logo etc. and final DRC

OK?

OK?

Design

Traditionalverificationflow

Chip finishing Fab line

Y

Y

Y

N

N

N

Designer’sjob

OK


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Traditional verification flow

DSM analog verification and chip finishing

DfM layout improvementsLayer density verification

Circuit and complete layout design

OK?

Fab line

Not OK

OK

Applying RET (OPC, PSM, SRAF)

N Layout redesign

Traditional verification flow Not OK

Litho simulation

OK

Parasitic extractionand post-layout simulations (optional)

Not OKOK

Alwaysdesigner’sjob

Oftendesigner’sjob

Usuallymanufacturer’sjobOptionally

designer’sjob

Y


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Derived layers

Metal1

Poly

N implant

Active

Creating derived layers for circuit extraction

Contact cut

NMOS_channel =Active • N implant • Poly

NMOS_S/D =Active • N implant

M1_to_N_S/D capacitor =NMOS_S/D • Metal1 • !Contact cut

NMOS_S/D contact =NMOS_S/D • Metal1 • Contact cut

(note: this capacitoris shorted here)


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Derived layers

Creating derived layers for circuit extraction

Poly_contact =Poly • Metal • Contact cut

M1_to_poly_capacitor =Poly • Metal • !Contact cut

(note: this capacitoris shorted)

Metal1Poly


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Derived layers

Creating derived layers for design rule check (DRC)

Poly

Active

Poly_DRC

Acive_DRC

Poly_to_active_error =Poly_DRC • Active_DRC

Poly

DPA = Min poly-active spacing

DPA = Min poly-active spacing

0.5 DPA

No overlap - no error here


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Marker layers

Regions excluded from circuit extraction (e.g. I/O pads),Regions excluded from DRC (e.g. I/O pads),Regions excluded from other actions (e.g. dummy fill insertion),Regions selected for some action (e.g. dummy fill insertion),Regions that should be treated separately (e.g. digital part of thechip and analog part of the chip),Devices that cannot be recognized in the usual way (e.g.inductors).

Marker layers: auxiliary layers for better control of circuitextraction and DRC. Markers at marker layers are polygons thatmay indicate:


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Circuit extraction

Device recognition and connectivity analysis: MOS devices and resistors

NMOS_channel property:MOS device, L=90nm, W=120 nm

NMOS_S/D property:resistive, Rs=9Ω/

NMOS_SD_contact property:resistive, R=15Ω

Metal1 property:resistive, Rs=0.09Ω/

Poly property:resistive, Rs=10Ω/

1

1

3

2

2

3

GND

1

2

3

Nominal extraction (MOSdevices only)

Extraction with parasitic resistances

R1 = Rmet1+Rcont +RSD

R2 = Rmet1+Rcont +RSD

R3 = Rpoly

M1,120/90

GNDM1,120/90

4


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Circuit extraction

Device recognition and connectivity analysis: some exceptions

Connection exists

No connection

Connection exists

No connection


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Circuit extraction

Device recognition and connectivity analysis: capacitors

R: contact resistance

C: M1 to poly capacitance(area = overlap area - contact area)

C negligibleR negligible

C: M1 to poly capacitance(area = overlap area)


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Circuit extraction

Creating netlist

1

2

3

GND

1

2

3

R1

R2

M1,120/90

GNDM1,120/90

M1 1 2 3 GND NCH W=120E-9 L=90E-9... .MODEL NCH NMOS LEVEL=14 VTO=0.35...

R3

M1 1 2 3 GND NCH W=120E-9 L=90E-9...R1 1 5 27R2 3 7 30R3 2 6 33.MODEL NCH NMOS LEVEL=14 VTO=0.35...

5

6

7

From analysis of the database of layers (primaryand derived)

MOS device model added from the PDK

Resistances calculated bythe extractor


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Circuit extraction

Old technologies: lateraldimensions much largerthan vertical ones, lateralcapacitances negligiblecompared to interlayer(vertical) ones.

DSM technologies: lateraland vertical dimensionscomparable, lateralcapacitances no longernegligible, many moremetal layers.

Parasitic capacitances in DSM technologies

Computational complexity of true 3D multilayer capacitance extraction is very high.Extractors simplify this process extracting only “short range” capacitances.


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Circuit extraction

Parasitic capacitances in DSM technologiesExample: capacitances extracted by Calibre® xRC tool:

Metal2 Metal2

Metal1

Semiconductor

Platecapacitance

Platecapacitance

Platecapacitance

Fringecapacitance

Fringecapacitance

Fringecapacitance

Lateral single layercapacitance

Lateral interlayercapacitance


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Circuit extractionToo many components - netlist reduction

Extraction of all components (MOS devices, resistances of all conductingpaths on all layers, all interlayer and lateral capacitances and all diodes)creates huge netlists. Example: “full” extraction of a simple opamp gives anetlist with 1162 R, C and D components. Only few of them affect operationof the circuit! Netlist reduction performed by extractors is rather limited.

NMOS devices: 6PMOS devices: 3Diodes: 29Capacitors: 69Resistors: 1064

It doesn’t make sense to extract everything, a wise selection must be made!


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Circuit extraction: special cases

Extraction would add huge number of bipolar devices to the netlist, in the“off” state in most cases. Therefore bipolar devices are usually notextracted.

Every NMOS device is also a lateral bipolar npn transistor. In DSMtechnologies base width of this device is below 100 nm.Every PMOS device on a n-well is also a lateral pnp bipolar transistor, andsource and drain regions create substrate pnp transistors.

pn n np p

p

Bipolar devices in CMOS circuits

Intentionally used bipolar transistors are usually pre-characterized library components, not easily scalable.They are often represented by subcircuits in the netlist. Emitter

Collector

Base

Grey shape: marker layer “this is bipolar transistor”


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There is no simple and accurate way to find parasitic inductance of aninterconnection wire over a semi-conducting substrate in the vicinity of otherwires (skin effect, proximity of other wires, uncertain return path). However,extractors do have tools for estimation of parasitic inductances. Normallythese inductances are very small and can be neglected even in RF circuits.

Inductors are shaped as spiral metal wires, often overspecial patterns on other layers (e.g. pn junctionsblocking eddy currents). Although they are easilyrecognized by a human, it is not easy to extract suchstructures as inductors automatically, and it is evenmore difficult to calculate their inductance and Q-factor.

Inductors are not easily scalable. They are usually pre-characterized librarycomponents, often represented by subcircuits in the netlist.

Inductors and parasitic inductances

Blue shape: marker layer “this is an inductor”


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Inductance ERC– Intended to estimate magnetic noise due to mutual inductance

of intentional inductors; finds the magnetic noise parameter Kdefined as the ratio of the mutual inductance between twointentional devices normalized to the geometric mean of thetwo self inductances.

– Sufficiently accurate if distance larger than 1/10 of theinductor’s dimensions

Point-to-point inductance extraction– Extracts self-inductance of single paths– Endpoints (“driver” and “receiver”) must be specified on the

layout– Performed for paths longer than 100 µm

Example: inductances in Calibre® xL tool - some options


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Self- and mutual inductance extraction– Intended to estimate the effect of magnetic coupling between

long parallel paths– “Aggressor” and “victim” paths must be identified: for a given

victim all paths within a tube of radius R (default = 60 µm) areaggressors

Example: inductances in Calibre® xL tool - some options

victimpath

aggressorpath

aggressorpath

notaggressorpath

R


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Parasitics in MOS devices - extraction and modelingIf source/drain diodes of MOS devices are treated as internal parts of these devices,it is difficult to avoid ambiguities.

D2

G2

S2

D1

G1

S1

D2

G2S2 and D1

G1

S1

MN1 1 2 3 0 Nchan W=325E-9 L=65E-9 +PD=1040E-9 AD=6.34E-14

MN2 3 4 5 0 Nchan W=325E-9 L=65E-9+PD=1040E-9 AD=6.34E-14

OK for layout 1 (separate source2 and drain1)

Wrong for layout 2 (shared source2/drain1)Area and perimeter of the shared D1/S2diode overestimated -> overestimatedcapacitance and leakage current.

It is safer to treat source/drain diodes as separate devices. If they areextracted separately, MOS models must not include them.


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Parasitics in MOS devices - extraction and modeling

A way to avoid ambiguities is to use parametrized device cells (p-cells).

The devices designed using p-cells have models parametrized to match thedevice layout, with parasitics (e.g. S/D resistances and capacitances) included.The extractor must not extract any parasitics inside the p-cell.

p-cell: no parasitics extractioninside (included in device model)

Outside p-cell: extraction ofparasitic R and C


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Floating netsIsolated shapes on conducting layers may be extracted as capacitors with oneterminal disconnected. Such isolated shapes are common in DSM layouts.

Metal1 connection

Isolated piece of metal2Floating net

Circuit simulators usually don’t accept floating nets (their potential isundefined). Extractors offer several options:

Extract floating nets and leave them in the netlist.Extract floating nets together with their net-to-ground capacitances.Extract floating nets but delete them from the netlist.Connect floating nets to ground.

The last two options are “safe” for circuit simulation, but either underestimateor overestimate the total interconnect parasitic capacitance.


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Distributed RC networksExtractors offer option to extract long interconnects as RC networks. Couplingcapacitance between adjacent paths can be included.

or


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Circuit extraction - summary

Extraction is a set of logical and geometrical operations on 2Dgeometrical objects.Extractors know very little about real 3D structures of ICs.Extractors do not do any simulation of active devices.Resistances and capacitances are calculated from layer physicalproperties and device geometry; usually simple formulas are used forcomputational efficiency.Extraction of some classes of devices requires understanding of theintention of the designer; special markers are used to indicate thesedevices.Some devices are not easily scalable, usually pre-defined.Extraction in analog and RF domains is not “automatic” - goodunderstanding of circuit and device operation is needed to selectproper layout and extraction options in order to obtain realistic post-layout simulation results.


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DRC

Simple geometrical rules: min. width, spacing, overlap,enclosure, extensionVoltage dependent rules: min. spacing depending on the biasvoltageCurrent density rules: min. metal width necessary for a givenaverage or pulse currentLatchup rules: to prevent latchupAntenna rules: max. area of poly and/or metal connected to MOSgates to avoid thin oxide breakdown due to ion-induced chargeLayer density rules: min. and max. density of layout features forprocess uniformityDfM (recommended) rules: yield enhancing recommendations


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DRC

Simple geometrical rules

a bc d e f

a: minimum widthb: minimum spacing (same or different layers)c: minimum enclosured: minimum overlape: minimum extensionf: min. and max. dimension (usually contact cuts)

In DSM technologies:• more rules per layer• many more layers (10+

metal layers)-> huge total number of rules

In DSM technologies layer width and spacing are often not independent:larger width -> larger minimum spacing


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DRC

Simple geometrical rules - example (metal rules)Old technology: simple a ba: minimum width 1 µmb: minimum spacing 1 µm

DSM technology: no longer simple

a b

a: minimum width 0.15 µmb: minimum spacing:

5.05.0 < w

1.51.5 < w < 5.0

0.20.20 < w < 1.5

0.15w < 0.20

min. spacing (µm)for width w (µm)

c: min. width for 45° path: 0.19 µm

cd

d: min. spacing for 45° path: 0.19 µm e: min. width in spiral inductors: 1.5 µm f: min. spacing in spiral inductors: 1.5 µm


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DRC

Voltage dependent rules

A d1 B Cd2

Minimum spacing may depend on the voltage applied, e.g. d1 < d2 if A and Bare at the same potential while B and C are not.

Such rules, if exist, are difficult to verify - DRC tools don’t know anything aboutvoltages in the circuit.


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DRC

Current density rules

Minimum metal width depends on the lithography resolution and on the maximumcurrent density (determined by reliability considerations). Large widths may benecessary for power and ground nets.

DRC tools do not verify the current density. However, special tools exist in EDAtoolsets for design of power nets in large VLSI circuits.

Current is also limited in contacts and vias. If themaximum current exceeds such a limit, multiplecontacts or vias must be used. This also reducescontact or via resistance, improves yield andreliability.

Max. currents in minimum size metal paths inDSM circuits are very low!


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DRC

Current density rules - exampleThe maximum current density is a function of metal path width and thickness,current waveform (DC, pulse, sinusoidal…) and maximum operating temperature.

20 * IDC5 * IDC2.5*(W-0.02)10*(W-0.02)M720 * IDC5 * IDC2.5*(W-0.02)10*(W-0.02)M630 * IDC7.5 * IDC1*(W-0.02)4*(W-0.02)M530 * IDC7.5 * IDC1*(W-0.02)4*(W-0.02)M430 * IDC7.5 * IDC1*(W-0.02)4*(W-0.02)M330 * IDC7.5 * IDC1*(W-0.02)4*(W-0.02)M260 * IDC15 * IDC0.75*(W-0.02)3*(W-0.02)M1

125°C105°C125°C105°CIpeak (mA)IDC (mA)

Layer no.

W - width in µm All metal layers are copper layers


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DRC

Latchup rules

Latchup may occur when at least one of the source/drain pn junctions of MOSdevices becomes forward biased. In a well designed circuit this may happenwhen the substrate is non-equipotential due to transient currents flowing in it.Therefore the general rule to avoid latchup is very simple: make the substrateequipotential using as many contacts to the ground node (for p-wells or p-typesubstrate) or the VDD node (for n-wells) as possible.

Example of DSM latchup rule:max. distance from the body contactto the boundaries of source/drainregions < 25 µm.

For I/O cells guard rings connectingthe well or substrate to VDD orground are used.


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DRC

Antenna rulesPlasma processes (e.g. reactive ion etching) result in accumulation of charge onconducting paths. This charge may destroy thin gate oxide in MOS devices duringfabrication. Antenna rules specify the maximum area of conducting layers (poly andmetal) that can be safely connected to MOS device gates. If the total area (sum ofareas of all layers exposed to ions) is not too big, no danger exists.

pn n

Ions

Antenna error:too large metal1area


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DRC

Antenna rulesIon induced damage will not occur if ion charge is drained by a diode connectedbetween the conducting “antenna” and semiconductor substrate.

pn n n

In CMOS circuits all transistor gates are connected to such diodes in completedcircuit. However, during fabrication such a connection may not exist yet when abig conducting “antenna” is already attached to a MOS device gate.

pn n n

m1

m2Damage during m1etching, m2 doesnot exist yet.


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DRC

Antenna rulesAntenna effect prevention when a large conducting area must be connected to agate:

pn n n

pn n n

m1m2

Diode insertion

Bridging

m1m2

Area too smallto collectdangerouscharge


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DRC

Antenna rules - example

R =Aantenna

Agate

Maximum ratio R of the area of the conducting layer (“antenna”) connected tothe gate to the area of the gate for unprotected gates (no diode):

For poly (area): R < 200For poly (sidewall area): R < 450For metal (cumulative area): R < 1000

Poly sidewall area = poly perimeter * poly thicknessMetal cumulative area = sum of areas of all metal layers

where


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DRC

Layer density rulesFairly uniform density of mask features on some layers is a must for good processcontrol.

Faster etching here Slower etching hereResist

Density affects etching speed:

Density affects chemical-mechanical planarization (CMP, crucial in DSM processes):

Ta barrier Copper

Ta is hard->slow polishingCopper is soft->fast polishing“Dishing”

To achieve uniform density, dummy fills (extra shapes) are added where needed.


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DRC

Layer density rules

Usually min. density (20% - 30%) and max. density (60% - 80%)These numbers are layer-dependentChecks show areas where density rules are violatedDummy fills may be added:

– manually– automatically (markers used to exclude some areas)– by the foundry (markers used to exclude some areas)

Dummy fills on conductive layers affect parasitic capacitancesIn wide metal areas slots must be added

or


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DRC

Layer density rules

Av. density = 40%: wrong! Av. density = 40%: OK!

Layer density rules are checked in moving windows, areas violating the densityrule are indicated.


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DRC

Dummy fills on active

Layer density rules


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DRC

Dummy fills on poly

Layer density rules


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DRC

Dummy fills on two metal layers

Layer density rules


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DRC

Recommended rules and DfMThese rules help to maximize manufacturing yield. They are usually not verified.Examples:

• Recommended width and spacing larger than minimum

• Same orientation for all shapes on the layer

• Path spreading (equal distances)

• Multiple contacts and vias wherever possible


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DRC

Recommended rules and DfM

Analysis of critical area

Critical area for shorts: area in the layout wherea spot defect (extra piece of conducting material)of radius R creates a short

Critical area for opens: area in the layout wherea spot defect (missing piece of conducting material)of radius R creates a path break

Some DRC tools offer critical area analysis. Visualization of critical areas helpsto find “weak spots” in the layout - areas sensitive to spot defects. This allowsto optimize the layout (minimize defect sensitivity). The defect density and defect size distribution are needed. They are process-specific foundry proprietary data, usually not available in ordinary PDKs.


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Layout postprocessing and mask data preparation

Resolution Enhancement Techniques (RET)Subresolution Assist Features (SRAF) - addition of unprintablemask features that improve lithography resolution, e.g. scattering bars

Optical and Process Correction (OPC) - predistortion of mask shapes in orderto improve final (printed) shapes

Phase Shifting Masks (PSM) - use phase shifts and interference to make sub-wavelength printing possible (e.g. by means of double exposure with twodifferent masks)

Layout postprocessing is normally performed by the foundry.OPC picture courtesy of J-M. Brunet, IEEE Web Seminar, November 9, 2006, reproduced with permission


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DRC - summary

DRC in DSM technologies is not just simpleverification of geometry of layout features.To obtain a manufacturable design, modifications ofthe original layout beyond correction of simple DRCviolations may be needed.DRC-clean designs not always guarantee highmanufacturing yield.Recommended rules provide guidelines how toimprove the layout to make it more “litho-friendly”.DfM-oriented layout analysis and layoutpostprocessing are theoretically possible (tools exist)but require deep processing knowledge and process-specific data normally not available for the designer.

IC Design Skills for Advanced DSM Technologies

Documents

Idesa Rf Lecture8 Kuzmicz 20080514