Implementation of 1553B Bus Protocol on FPGA

Board Using Digital Phase Lock Loop

Jawad Yousaf1, Mohsin Irshad

2and Iftekhar Mehmood

3

1Institute of Space Technology, Islamabad, Pakistan

2University of Western Ontario, London, Canada

3Center for Advanced Studies in Engineering, Islamabad, Pakistan

jawad.yousaf@yahoo.com, mirshad3@uwo.ca, iftekhar@case.edu.pk

AbstractIn this paper, a new technique for the

implementation of MIL-STD-1553B bus protocol on FPGA board

using digital phase lock loop is presented. Digital phase lock loop

(DPLL) is used for data clock recovery from encoded manchester

data of the channel at receiver end, instead of implementing

common practice of initiating a separate clock for encoded

manchester data processing. Usage of DPLL, resolves the

synchronization issues, a major concern in high data rate

embedded systems and increases the integrity and reliability of

the system. Proof of concept is validated by implementing a

1553B bus transaction (BC to RT) on FPGA board with its

different modules like UART, Bus controller, Manchester

encoder/decoder and Digital phase lock loop.

Index TermsMIL-STD-1553B, FPGA, DPLL.

I. INTRODUCTION

Centralized systems were used in early 60s for

communication among various on-board avionic systems [1]. It

resulted in bulky systems as it required more computer

processing and analog point-to-point wire connections between

other devices for information interchange. The use of

distributed architecture systems and digital multiplexing

techniques increases the reliability and integrity of the system

[1]. Different serial digital multiplexed bus standards,

including 1553B were developed for standard interface

network between different avionics systems, reduction in cable

interfaces and to improve data transfer rates [1], [2]. Modern

day avionics systems communicate with others using the MIL-

STD-1553B bus.

The 1553B is an internal time division, command/

response, digital multiplexed, redundant serial data bus with

data rate of 1Mbps [2]. It provides integrated, centralized

system control as well as a standard interface for all the

equipment connected to the bus [2]. Fig.1 shows the general

architecture of 1553B bus in which all bus traffic is available to

be accessed with a single connection of twisted pair cable for

testing and interfacing with any system [2], [3]. The bus has

three word formats, command, data and status, each of 20bits,

for communication on bus. Bus controller controls the overall

functionality of the bus e.g. monitoring the remote terminals,

arbitration and data transfer.

Manchester encoder/decoder is used to provide the physical

layer connection between bus controller (BC) and remote term-

Fig. 1. 1553B Bus Structure

-inals (RT). At the decoder side of remote terminals, the clock

signal required for decoding and further processing of encoded

manchester data is usually provided by initiating a separate

clock at the receiver end [4][7]. In this scenario,

synchronization between generated clock and received encoded

data becomes a major issue especially for hardware

implementation.

In this work, we have proposed a new technique for the

implementation of 1553B bus protocol on FPGA board using

digital phase lock loop (DPLL). Digital phase lock loop/bit

synchronization circuit has wide range of applications in

commercial, military and space products for the reduction of

phase delay of clock signals, generation of high speed stable

clock signal and the synchronization of data transfer [8], [9].

The used DPLL resolves the synchronization issues by

extracting the clock from manchester encoded data of the

channel at the decoder side of the remote terminals for further

processing of data. A 1553B bus transaction, bus controller to

remote terminal (BC to RT), is successfully implemented on

FPGA board by using DPLL at the receiver ends.

II. IMPLEMENTATION METHODOLOGY

The implementation of bus protocol incorporates the design

and implementation of different modules of bus controller and

remote terminal on ISE Xilinx Spartan 3 FPGA kit [10]. The

modules were executed on hardware after verification of the

results on ModelSim [11]. The implemented 1553 encoder and

remote terminal are shown in Fig.2 & Fig.3 respectively. 1553

protocol manager formulates the words (command, data and

status) according to bus transaction. Manchester encoder

transmits the encoded data on channel for intended receivers.

For synchronization of clock at the receiver end [Fig.3], a

Digital Phase Lock Loop (DPLL) is used, which recovers the

978-1-4673-4450-0/12/$31.00 2012 IEEE

Fig. 2. 1553B Encoder

Fig. 3. Remote Terminal

clock signal from received encoded data [3], [9], [12][14] and

then sends the recovered clock and encoded data to Manchester

decoder. After this, protocol manager checks the sync bits for

differentiating received words, unwraps the original data and

performs the parity check. To display the decoded data on the

personal computer for demonstration, UART RS232 serial

interfacing is used. The hardware test results were obtained

using a 1693A PC-Hosted Logic Analyzer [15].

Implementation of the physical and data link layer is discussed

separately.

The internal 50 MHz clock of Spartan-3 LC development

board requires division to generate a 2MHz clock for the

generation of different words at 1Mbps data rate requirement.

The physical layer implementation needs manchester encoding/

decoding of the data. The block level description of the

Manchester encoder/decoder is shown in Fig.4. Manchester

decoder decodes the encoded data by using the extracted clock

of DPLL. The implemented waveforms of manchester encoder

are shown in Fig.5.

Fig. 4. Block level description of manchester encoder/decoder

III. DIGITAL PHASE LOCK LOOP

Clock signal required for the decoding of the encoded data

can be provided by either initiating a separate clock at receiver

end [4][7] or extracting the clock from the encoded data [3],

[8], [9], [13], [14], [16][20]. The requisite synchronization/

phase estimation of carrier and data in the implemented

hardware is a major issue for optimum demodulation performa-

Fig. 5. Manchester encoder implemented results

-nce [14], [21].The initiation of a separate clock for decoding at

the receiver end, demands a highly stable oscillator with such

synchronization circuitry that can achieve required

synchronization between received encoded data and the

generated clock. However extraction of clock from encoded

data can resolve the synchronization issues [9], [13], [14], [16]

of carrier.

A phase lock loop is a circuit synchronizing an output

signal generated by an oscillator with a reference or input

signal in frequency as well as in phase [12], [22]. Digital phase

lock loop are widely used in industry for coherent carrier

tracking, bit synchronization and symbol synchronization in

both wired and wireless digital communication applications

[16], [17], [19]. Digital phase lock loops have interesting

characteristics of wider frequency range and robustness of

system for temperature and voltage variations [22]. Literature

is rich for the basics of DPLLs and their various aspects of

implementations [8], [12], [13], [17], [19], [21], [22].

A. DPLL Implemented Technique

Digital phase lock loop consists of a phase detector, loop

Fig. 6. Implemented digital phase lock loop block diagram

filter and digital controlled oscillator (DCO). A divide by N

counter is inserted between DCO and phase detector in many

applications [8], [22]. Fig.6 shows the block diagram of

implemented technique of DPLL [8]. The technique is

implemented in Verilog and simulated in Modelsim. The two

phase detector EXOR and JK flipflop are connected to the loop

filter, formed by K counter. The output of the K counter is

provided to the ID counter which is used as a DCO. This DPLL

system contains an external N counter. The complete

implemented schematic of the DPLL is shown in Fig.7. The

detail of each block is discussed here separately.

1) Phase Detector: In implementing the technique, phase

detector can either be a XOR gate or an edge triggered JK

flipflop. The frequency of output signal of both phase detectors

changes with variations in phase of input signals U1 & U2respectively [8]. Fig.8 explains that Ud signal is triggered as

soon as the edge of the clock or manchester data is arrived.

Fig. 8. Phase detector implemented results

2) Loop Filter: The loop filter (K Counter) will use the Ud(DN/Up) signal generated by phase detector to output the

carry and borrow signals. The K counter consists of two

independent UP & DOWN counters. K is the modulus of both

counters. The frequency fc of the K Clock is calculated by the

following relations [8]

fc = M f

o

also K M/4 where M = 16

so K M/4 = 4

The resulting fc will be 16MHz. The value of K modulus

(K=4) is assigned using the DIP switches from the board and fc

is generated by using internal Xilinx core of digital clock

manger (DCM). The generated clock from the DCM is of

16.667 MHz instead of 16MHz. Fig.9 illustrate that borrow

signal value changes as the terminal count of the K modulus

value is reached.

Fig. 9. Loop filter implemented results

3) Digital Controlled Oscillator (DCO): Digital controlled

oscillator (DCO) utilizes digital approach for frequency tuning

of the circuit. The implemented DCO is increment decrement

(ID) counter [8]. Carry pulses (output of K counter) are fed to

the INC and Borrow to the DEC input of DCO. ID counter

works on the positive edges of carry and borrow signals. The

output IDout (U2) is obtained by the following logical function

[8]

IDout= The selection of the DCO frequency (fc) depends upon value of divide by N counter. The ID clock is calculated by following

relation [8]f

c = 2Nf

o = M f

o

Where N is the value of the divide by N counter. ID counter

has the same clock frequency fc = 2N fo (ID clock) as of the

loop filter [8], so both can be fed from a common oscillator.

As shown in Fig.10, according to the input signals, content of

toggle flip-flop changes and finally IDout signal (recovered

Fig. 7. Digital phase lock loop implemented schematic

clock of DPLL) is generated. It needs to be passed through a

divide by N counter to get the required frequency of the

recovered clock.

Fig. 10. DCO implemented results

4) Divide by N Counter: Divide by N counter is used to

divide the input frequency by a factor of N. The value of N

depends upon the value M of K clock signal. As described in

[8], the value of N comes out to be M = 2N

N = M/2 = 8 So the divide by 8 counter is used to divide the ID out signal to

get the required frequency of the recovered clock signal

[Fig.11].

Fig. 11. Divide by N counter implemented results

Fig. 12. Digital phase lock loop implemented result

Figure 12 shows the complete implemented results of the

digital phase lock loop. Combinational and routing delays of

the circuitry [23] and unstable clock of the development board

[8], [24] produce a delay of 165 nsec in recovered clock. If the

observed delay is greater than 0.5sec then the problem can be solved by delaying the recovered clock using a delaying

circuitry [25], [26]. The implemented solution to this problem

however, consists of taking the samples of the manchester

encoded data at negedge of the recovered clock. Since the

delay encountered is less the 0.5sec, this is apparently an optimized solution to the problem. The problem could have

been resolved through a delay circuit but that would introduce

its own attendant problems [25], [26]. Fig.13 illustrates the

Manchester decoded data waveforms.

Fig. 13. Manchester decoder implemented results

IV. 1553B BUS TRANSACTION

The generation, detection and decoding of the command,

data and status words for different transactions over 1553B bus

using the protocol is implemented at data link layer. The

implemented results of bus transaction, Bus Controller to

Remote Terminal (BC to RT) are discussed here. Bus

controller and remote terminals are implemented separately on

different Spartan-3 LC FPGA boards and connected through

single twisted pair cable for the test set up.

A. Bus Controller to Remote Terminal (BC to RT)

Transaction

During this transaction the BC wishes to transfer data to a

particular RT in the sequence as described in [2].

1) Bus Controller: Figure 14 shows the implemented results

of the bus controller. The command and data word signal of the

Fig.10 illustrates that the bus controller has put the two data

words on the bus after the command word. The generated data

words, for demonstration, are the ASCII codes of the A&B

(data word 1) and A&B (data word 2).

2) Remote Terminal: Remote terminal picks the data from

the bus. The decoding of the words is done by taking the

samples at the negedge of the recovered clock. The decoded

data words are stored in the registers for further processing.

Fig.15 illustrates the waveforms of the subsequently generated

status word by the concerned RT. The bus controller transmits

the next command word after the reception of the

acknowledgement in the form of status word. The optimization

of code is achieved simply by using only one counter each for

the BC and RT for the detection/decoding of the word formats.

3) UART Interfacing: For interfacing with personal computer, UART transmitter transmits the data only when it had been decoded by the Protocol Manager. Therefore synchr-

-onization between the decoded data and UART transmitter is an important issue for the implementation of UART transmitter. The needed synchronization is achieved by designing a UART controller. Remote terminal generates a control signal (UART enable) after the unwrapping of the data words. UART controller generates the Enable clock pulses according to the UART enable signal. The data is loaded from UART FIFO to UART transmitter at positive edge of the

Enable clock pulses while UART transmitter transmits the data at the negedge of the Enable Clock pulses, providing an optimized solution. As shown in UartFIFO out [Fig.16], UART transmitter sends the successfully decoded data words by remote terminal data word decoder.

V. CONCLUSION

In this work, the proposed FPGA implementation of 1553B

Fig. 14. UART interfacing implemented results

Fig. 14. Bus controller implemented results

Fig. 15. Remote terminal implemented results

bus using digital phase lock loop is discussed in detailed.

DPLL is used for the recovery of clock signal which is used for

synchronization at the receiver end. DPLL is very useful for

carrier data recovery and it is widely being used for

carrier/phase estimation and symbol synchronization in

industry. A 1553B data transaction BC to RT is implemented

and tested on FPGA board according to the protocol standard.

FPGA implementation provides a system on chip solution of

the 1553B bus protocol. As the technology is advancing and

requirements of integrated high speed processing for military

and space applications demand higher data rate buses, which

includes high speed 1553 bus, fiber distributed data interface

(FDDI), fiber channel and ATM technologies [27]. FPGA

implementation of 1553B is cost effective solution for

emerging higher bandwidth requirements due to its higher

processing speed for higher data rate, low latency and

affordable complexity as compared to DSP & microcontroller

implementation. The implemented methodology can be used

for the implementation of MIL-STD-1773 [28] data bus with

the replacement of STP to optical fiber and with the usage of

optical interfaces.

ACKNOWLEDGMENT

The authors would like to thank Mr. Faisal Raza, Mr. Irfan

Aslam and Mr. Kashif Siddique for their guidance and

productive discussions.

REFERENCES

[1] E. C. Gangl, Evolution from analog to digital integration in

aircraft avionics - a time of transition, IEEE Trans. Aerospace

and Electronic Systems, vol. 42, no. 8, pp. 11631170, 2006.

[2] Department of Defense Interface Standard for Digital Time

Division Command/ Response Multiplex Data Bus, MIL-STD-

1553B, Notice 4, Department of Defense Std., 1978.

[3] H. J. Yousaf, M. K. Siddique, and I. Mehmood, FPGA

implementation of 1553B bus protocol, in Proc. Int. Conf. on

Aero. Science and Eng., vol. 1, Aug. 2009, pp. 6973.

[4] Y. Bai, Z. Zhou, and J. Chen, The implementation of MIL-STD

1553B processor, in Proc. 2nd Int. Conf. on ASIC, Oct. 1996,

pp. 231234.

[5] D. L.-Feng, D. Ming, and L. J.-Ming, Application of IP core

technology to the 1553B bus data traffic, in Proc. Asia Pacific

Conf. on Microelectronics and Electronics, Sep. 2010, pp. 338

342.

[6] L. Zhijian, Research and design of 1553B protocol bus control

unit, in Proc. Int. Conf. on Educational and Network

Technology, Jun. 2010, pp. 330333.

[7] L. Lie and M. Chai, Design of 1553B avionics bus interface chip

based on FPGA, in Proc. Int. Conf. on Electronics

Communications and Control, Sep. 2011, pp. 36423645.

[8] R. E. Best, Phased Locked Loops Design, Simulation and

Applications, 4th ed. New York: McGraw Hill, 1999.

[9] K. Ohno and F. Adachi, Fast clock synchroniser using initial

phase presetting dpll reception (IPP-DPLL) for burst signal,

Electron. Lett., vol. 27, no. 21, pp. 19021904, Oct. 1991.

[10] (2009) Xilinx spartan 3sxlc. [Online]. Available:

http://www.memec.com/xilinxkits

[11] Modelsim se (version 6.5). [Online]. Available: Mentor

Graphics. 2009

[12] W. C. Lindsey and C. M. Chie, A survey of digital phase-

locked loops, Proc. of The IEEE, vol. 69, no. 4, pp. 410431,

Apr. 1981.

[13] J. L. Sonntag and J. Stonick, A digital clock and data recovery

architecture for multi-gigabit/s binary links, IEEE J. of Solid-

State Circuits, vol. 41, no. 8, pp. 18671875, Aug. 2006.

[14] H. L. Hartmann and E. Steiner, Synchronization techniques for

digital network, IEEE J. on Selected Areas in Comm., vol.

SAC-4, no. 4, pp. 506513, Jul. 1986.

[15] 1693A pc-hosted logic analyzer. [Online]. Available: Agilent

Technologies. 2003

[16] T. D. Loveless, L. W. Massengill, B. L. Bhuva, W. T. Holman,

A. F. Witulski, and Y. Boulghassoul, A hardened-by-design

technique for RF digital phase-locked loops, IEEE Trans. on

Nuclear Science, vol. 53, no. 6, pp. 34323438, Dec. 2006.

[17] B. Kim, Dual-loop DPLL gear-shifting algorithm for fast

synchronization, IEEE Trans. on Circuits and Sys.-II: Analog

and Digital Signal Processing, vol. 44, no. 4, pp. 577586, Jul.

1997.

[18] B. Kim, D. N. Helmen, and P. R. Gray, A 30-MHz hybrid

analog/digital clock recovery circuit in 2-pm CMOS, IEEE J.

of Solid-State Circuits, vol. 25, no. 6, pp. 13851390, Dec.

1990.

[19] M. Sangriotis and I. Xezonakis, Digital costas loop-like pll for

the carrier recovery of a QPSK signal, Electron. Lett., vol. 29,

no. 10, pp. 897899, May 1993.

[20] J.-P. Sandoz and S. W. Steenaart, Performance improvement of

a binary quantized all-digital phase-locked loop with a new

aided-acquisition technique, IEEE Trans. on Commun., vol.

COM-32, no. 12, pp. 1269 1276, Dec. 1984.

[21] A. Weinberg and B. Liu, Digital phase lock for optimum

demodulation, IEEE Trans. on Aerospace and Electronic Sys. ,

vol. AES-11, no. 6, pp. 12691280, Nov. 1975.

[22] Y. R. Shayan and T. L.-Ngoc, All digital phase-locked loop:

concepts, design and applications, IEEE Proc., vol. 136, no. 1,

pp. 5356, Feb 1989.

[23] M. D. Ciletti, Advance Digital Design with Verilog HDL, 2nd

ed. New Jersey: Prentice Hall, 2007.

[24] C. A. P.-Raez, Noise analysis of a digital tanlock loop, IEEE

Trans. on Aerospace and Electronic Sys. , vol. 24, no. 6, pp.

713718, Nov. 1988.

[25] H. Dewan, System for delay reduction during technology

mapping in FPGA, U.S. Patent 0 177 808A1, Aug. 11, 2005.

[26] E. Kassapaki, P. M. Mattheakis, and P. Sotiriou, Actual-delay

circuits on FPGA: Trading-off luts for speed, in Proc. Int.

Conf. on Field Programmable Logic and Applications, Aug.

2006, pp. 16.

[27] M. G. Hegarty, High performance 1553: a feasibility study, in

Proc. 23rd Digital Avionics Systems Conf., vol. 2, Oct. 2004, pp.

7.D.47.1.

[28] J. R. Murdock and J. R. Koenig, Open systems avionics

network to replace MIL-STD-1553, IEEE AES Systems

Magaz., pp. 1519, Aug. 2001.

/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages false /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 600 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile (None) /PDFXOutputCondition () /PDFXRegistryName (http://www.color.org) /PDFXTrapped /False

/Description >>> setdistillerparams> setpagedevice