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Educational Services Group (ESG)September 12, 1995

IC/ASIC Design Composition andAnalysisTraining ManualVersion 4.3.3

Educational Services Group (ESG)September 12, 1995

IC/ASIC Design Composition andAnalysisTraining ManualVersion 4.3.3

1990-95 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

No part of this publication may be reproduced in whole or in part by any means (including photocopying or storage in an informationstorage/retrieval system) or transmitted in any form or by any means without prior written permission from Cadence Design Systems, Inc.(Cadence).

Information in this document is subject to change without notice and does not represent a commitment on the part of Cadence. The informationcontained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used onlyby Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth insuch agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy orusefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any thirdparty rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.

RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph(c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

Cadence Design Systems, Inc. 555 River Oaks Parkway, San Jose, CA 95134, USA

Unpublished – rights reserved under the copyright laws of the United States.

In this manual the screen representation of “Framework” and any reference to it connotes Design Framework II software.

Other TrademarksFrameMaker is a registered trademark of Frame Technology Corporation.Motif is a registered trademark of Open Software Foundation, Inc.OPEN LOOK is a registered trademark of UNIX System Laboratories, Inc.PostScript is a registered trademark of Adobe Systems.SPICE ia a trademark of the Regents of the University of California.Sun is a registered trademark of Sun Microsystems.ULTRIX is a trademark of Digital Equipment Corporation.UNIX is a registered trademark of UNIX System Laboratories, Inc.X Window System is a trademark of the Massachusetts Institute of Technology.

Cadence TrademarksAccessAllegroAllegro-MCMAmadeusAnalog ArtistAnalog WorkbenchAnalyzerASIC WorkbenchAXLBitGradeCadence SPICECAEviewsCheckPlusCommunications ManagerComponent Information WorkbenchComposeComposerConceptConfirmConstructDantesDesign FrameworkDesign Framework ΙΙDesign ManagerDesign PlannerDF/Assembly

DFFabDF/Signal IntegrityDFTestprepDF/ThermaxDF/ViableDIVADLM Place & Route SystemDRACULAEDGEEnsembleGDSIIGEDHDL SynthesizerHierarchy ManagerINSIGHTIntegrator’s ToolkitLayDeLeapfrogLicense ManagerLogic WorkbenchMLM Place & Route SystemModuleMakerOpen HDL ToolkitOpenSim BackplaneOptimizerOpus

PIC DesignerPowerVHDLPRANCEPrance-XLPreviewProcess ManagerProfileRapidPARTRapidSIMRapidTESTSageSCALDsystemSimukitSKILLSmoke AlarmSpectreSPICE PLUSStructure CompilerSYMBADSynergySystemPGASystemPLDSystem WorkbenchTancellTansureTeam Design Manager

Test GeneratorTestGradeTest-intelligent Design SeriesTestScanTest SimulatorTest SynthesizerThermoSTATSTranscribeValidCOMPILERValidFrameValidGEDValidPACKAGERValidSIMValidTIMEVDoc 454Verifault-XLVerilogVerilog-XLVeritimeVeritoolsVHDL SynthesizerVHDL-XLVirtuosoWarp-4Warp GridXLProcessor

Table of Contents IC/ASIC Design Composition and Analysis

9/12/95 Cadence Design Systems, Inc. iii

Table of ContentsIC/ASIC Design Composition and Analysis

Module 1 Introduction

Audience .................................................................................................................................................. 1-4

Module 2 Using the Design Framework II Environment

Software Overview .................................................................................................................................. 2-4IC Design Flow in Design Framework II ................................................................................................ 2-6ASIC Design Flow................................................................................................................................... 2-8Starting the Design Framework II Environment.................................................................................... 2-10The Role of the Command Interpreter Window .................................................................................... 2-12Basic Components of the Design Framework II Environment.............................................................. 2-14

Using a Form.................................................................................................................................... 2-16Lab 2-1 Starting the Design Framework II Environment ...................................................................... 2-17Getting Help........................................................................................................................................... 2-20

OpenBook ........................................................................................................................................ 2-22Software Hierarchy ................................................................................................................................ 2-24Lab 2-2 Using OpenBook ...................................................................................................................... 2-25What Is a Project? .................................................................................................................................. 2-28Creating a Library .................................................................................................................................. 2-30The Library Structure............................................................................................................................. 2-32Accessing an Existing Library ............................................................................................................... 2-34Lab 2-3 Creating a Library .................................................................................................................... 2-35

Module 3 Design Entry

Contents of a Schematic........................................................................................................................... 3-4Schematic Entry Flow.............................................................................................................................. 3-6

Checking a Schematic........................................................................................................................ 3-8Examples of Schematic Rule Checks .............................................................................................. 3-10Schematic Check Severity ............................................................................................................... 3-12Cross-View Checker ........................................................................................................................ 3-14

Hierarchical Schematic .......................................................................................................................... 3-16Textual Design Entry ............................................................................................................................. 3-18

Examples of a Functional Cellview ................................................................................................. 3-20Automatic Cellview Generation Flow ................................................................................................... 3-22Plotting Schematics................................................................................................................................ 3-24

IC/ASIC Design Composition and Analysis Table of Contents

iv Cadence Design Systems, Inc. 9/12/95

Lab 3-1 Creating a Schematic with Fixed Menus.................................................................................. 3-25Lab 3-2 Automatically Creating a Symbol ............................................................................................ 3-25Lab 3-3 Creating and Modifying a Hierarchical Schematic .................................................................. 3-25Lab 3-4 Using Hierarchy Commands .................................................................................................... 3-25Lab 3-5 Checking a Schematic .............................................................................................................. 3-25Lab 3-6 Creating a Verilog HDL Cellview............................................................................................ 3-25Lab 3-7 Plotting a Schematic (Optional) ............................................................................................... 3-25

Module 4 Creating Schematic Symbols

Contents of a Symbol............................................................................................................................... 4-4Interpreted Labels .............................................................................................................................. 4-8Symbol Pins ..................................................................................................................................... 4-10

Automatic Symbol Generation Flow ..................................................................................................... 4-12Creating Block Diagrams....................................................................................................................... 4-14Lab 4-1 Creating a Schematic Symbol with Fixed Menus .................................................................... 4-15Lab 4-2 Creating a Symbol from an Existing Cellview......................................................................... 4-15Lab 4-3 Creating Block Diagrams ......................................................................................................... 4-15

Module 5 Buses and Multisheet Schematics

Buses and Symbol Iterations.................................................................................................................... 5-4Bus Tapping............................................................................................................................................. 5-6

Bus Tapping Example........................................................................................................................ 5-8Multisheet Schematic Index................................................................................................................... 5-10

Pins in Multisheet Schematics ......................................................................................................... 5-12Pin References in Multisheet Schematics ........................................................................................ 5-14

Lab 5-1 Creating a 4-Bit Adder Using Bus Tapping ............................................................................. 5-15Lab 5-2 Creating a Multisheet Schematic.............................................................................................. 5-15

Module 6 Using Verilog Integration

Using Verilog-XL in the Design Framework II Environment................................................................. 6-4Simulation Flow....................................................................................................................................... 6-6

Starting the Simulator ........................................................................................................................ 6-8Verilog Netlisting Options............................................................................................................... 6-10Verilog Simulation Options ............................................................................................................. 6-12Verilog Waveform Options.............................................................................................................. 6-14Test Fixture File Template............................................................................................................... 6-16The Verilog Window ....................................................................................................................... 6-18

Adding Breakpoints ............................................................................................................................... 6-20


9/12/95 Cadence Design Systems, Inc. v

Adding Patches ...................................................................................................................................... 6-22Run Directory Contents ......................................................................................................................... 6-24

The ihnl Directory............................................................................................................................ 6-26Lab 6-1 Running a Verilog-XL Simulation........................................................................................... 6-27Lab 6-2 Simulating a Schematic with Verilog-XL................................................................................ 6-27The Hierarchy Browser.......................................................................................................................... 6-30Simulation Comparison ......................................................................................................................... 6-32Simulation Comparison Variables ......................................................................................................... 6-34Importing Verilog Descriptions ............................................................................................................. 6-36

Inputs to Verilog In.......................................................................................................................... 6-38Outputs of Verilog In ....................................................................................................................... 6-40

Netlist Flow............................................................................................................................................ 6-42View List and Stop View List.......................................................................................................... 6-44

Netlisting Example................................................................................................................................. 6-46Netlisting Exercise ................................................................................................................................. 6-48Lab 6-3 Comparing Verilog-XL Simulations ........................................................................................ 6-49Lab 6-4 Using Verilog In....................................................................................................................... 6-49Lab 6-5 Simulating a Mixed-Level Design ........................................................................................... 6-49

Module 7 Using Synergy Interface

Logic Synthesis........................................................................................................................................ 7-4Cadence Synthesis Interface .................................................................................................................... 7-8Synthesis Library ................................................................................................................................... 7-10HDL Synthesizer and Optimizer............................................................................................................ 7-12Synthesizer/Optimizer User Interface.................................................................................................... 7-14Categories of Constraints....................................................................................................................... 7-16

Attributes ...................................................................................................................................... 7-18Finite State Machines....................................................................................................................... 7-20Preferred Library Parts..................................................................................................................... 7-20Cost .................................................................................................................................................. 7-22Timing.............................................................................................................................................. 7-22Report............................................................................................................................................... 7-22

Applying Constraints ............................................................................................................................. 7-24Timing-Driven Synthesis ....................................................................................................................... 7-26Layout Intelligent Optimization............................................................................................................. 7-28Types of Synthesis Runs........................................................................................................................ 7-30Lab 7-1 Using Synergy Integration....................................................................................................... 7-31Lab 7-2 Creating a Trade-Off Curve .................................................................................................... 7-31


vi Cadence Design Systems, Inc. 9/12/95

Module 8 Managing Design Data

Numbered Cellview Versions .................................................................................................................. 8-4Data Management of Cellviews............................................................................................................... 8-6Version Browser ...................................................................................................................................... 8-8Lab 8-1 Using Version Control................................................................................................................ 8-9Lab 8-2 Copying a Cell............................................................................................................................ 8-9Configuration Management ................................................................................................................... 8-12

Types of Configurations .................................................................................................................. 8-14Entry Configuration ......................................................................................................................... 8-16Entry Configuration Selection ......................................................................................................... 8-22Version Binding in Configurations.................................................................................................. 8-24Static and Dynamic Binding ............................................................................................................ 8-26Configurations and the Library Browser ......................................................................................... 8-28

Lab 8-3 Creating Entry Configurations ................................................................................................ 8-29

Module 9 Using the Veritime Interface

Introduction to Timing Analysis.............................................................................................................. 9-4Overview of Veritime .............................................................................................................................. 9-6Performing Path Analysis ........................................................................................................................ 9-8Performing Hybrid Analysis .................................................................................................................. 9-12Delay Annotation ................................................................................................................................... 9-22Lab 9-1 Using the Veritime Integration................................................................................................. 9-23

Module 10 Running Circuit Simulation

Simulation Flow..................................................................................................................................... 10-4The Component Description Format (CDF).......................................................................................... 10-8

Property Inheritance......................................................................................................................... 10-12Simulation and Test Language............................................................................................................. 10-14

Compiling an STL File .................................................................................................................. 10-16Sample STL File ............................................................................................................................ 10-18STL Timing Descriptions .............................................................................................................. 10-20

Lab 10-1 Adding Parameters for Simulation....................................................................................... 10-21Lab 10-2 Running a Circuit Simulation Using Spice .......................................................................... 10-21


9/12/95 Cadence Design Systems, Inc. vii

Module 11 Comparing Layouts and Schematics

Layout Versus Schematic Data Flow..................................................................................................... 11-4Extractor........................................................................................................................................... 11-6Layout Versus Schematic ................................................................................................................ 11-8

Lab 11-1 Comparing a Schematic with an Extracted Layout ................................................................ 11-9

Module 12 User Customization

Defining Bindkeys ................................................................................................................................. 12-4Design Framework II Initialization Sequence ....................................................................................... 12-6The .cdsinit File ..................................................................................................................................... 12-8Customizing Strategy........................................................................................................................... 12-10

Defining Basic Tasks in .cdsinit File ............................................................................................. 12-12Lab 12-1 Defining Bindkeys................................................................................................................ 12-15Lab 12-2 Adding Bindkeys to the .cdsinit ........................................................................................... 12-15Lab 12-3 Saving the Environment ....................................................................................................... 12-15

Module 13 Edge Database Translation

Translation Programs............................................................................................................................. 13-4Conversion Flow.................................................................................................................................... 13-6Additional Translation Inputs ................................................................................................................ 13-8Connectivity Differences ..................................................................................................................... 13-10Lab 13-1 Converting an Edge Schematic Database to Design Framework II ..................................... 13-11

Appendix A Setup and Customization Files

The .cdsinit File ................................................................................................................................ A-1Sun 4 .cshrc File ............................................................................................................................... A-1HP .cshrc File.................................................................................................................................... A-6DEC .cshrc File............................................................................................................................... A-10IBM RS/6000 .cshrc File ................................................................................................................ A-13The .login File................................................................................................................................. A-17The .Xdefaults File .......................................................................................................................... A-19HP .xinitrc File for the Motif Window Manager ............................................................................ A-24Sun 4 .xinitrc File for the Motif Window Manager ........................................................................ A-24IBM RS 6000 .xinitrc File for the Motif Window Manager........................................................... A-24OPEN LOOK .xinitrc File for the Motif Window Manager........................................................... A-25Sun 4.xinitrc File for the Motif Window Manager ......................................................................... A-25


viii Cadence Design Systems, Inc. 9/12/95

Appendix B Reference Materials

adder4bit Functional Description.......................................................................................................B-1dff2 Functional Description ...............................................................................................................B-2REGCTR Functional Description......................................................................................................B-3counter.v File .....................................................................................................................................B-4

Appendix C Lab Example Designs

HA Schematic ....................................................................................................................................C-1FA Schematic.....................................................................................................................................C-1FA Symbol .........................................................................................................................................C-2adder4bit Schematic...........................................................................................................................C-3adder4bit Symbol ...............................................................................................................................C-4adder8bit Index Schematic.................................................................................................................C-4adder8bit Sheet 1................................................................................................................................C-5adder8bit Sheet 2................................................................................................................................C-6adder8bit Sheet 3................................................................................................................................C-7CounterSlice Schematic ....................................................................................................................C-8eventCounter Schematic ....................................................................................................................C-9

Cadence Training Course Installation Guide

1/17/95 Cadence Design Systems, Inc. 1


For Questions or Problems About Contact

Training materials Training Coordinator, Jonathan Thalbergemail: [email protected] Design Systems555 River Oaks ParkwaySan Jose, CA 95134(408) 944–7814

Installing or testing Training materials Course developer listed in the README file includedwith the course database, only after following theinstallation testing instructions.

If the course developer is not available or if no coursedeveloper’s name appears in the README file, contactthe Training Coordinator or the Customer ResponseCenter (CRC). Telephone: 1-800-CADENC2


2 Cadence Design Systems, Inc. 1/17/95

Installing a Course

Install

softwareproduct

Install the

databasecourse

Create a

accounttraining

Test the

and copy datainstallation

Existingtraining account

?

No

Yes



Installing Product Software

Be sure that the software installation is complete before you try to install the coursedatabase. There might be specific issues about product installation for your application.Refer to your application product notes. For Design Framework II-based products, refer tothis section.

Setting Up Design Framework II Site Customization

The customary Design Framework II software hierarchy is shown below.

The directory <CDS_INSTDIR>/tools/dfII/local is the site customization directory.Replace <CDS_INSTDIR>, in the above diagram, with the path to your Cadence SoftwareInstallation Directory.

Setting Up the Site .cdsinit File

You must create a site customization file .cdsinit, located in <CDS_INSTDIR>/tools/dfII/local. If you already have a site .cdsinit file and choose to use it, you must also load theworking directory .cdsinit required for each Cadence Training course. If you choose to useyour own site .cdsinit, the performance of the course exercises might be affected.

1. Log in as the user who owns the software installation directory.

2. If you do not have a site .cdsinit, change to the Design Framework II directory andinstall the site customization file. Entercd <CDS_INSTDIR>/tools/dfIImkdir localcp samples/local/cdsinit local/.cdsinit

tools

other tools

<CDS_INSTDIR>

plotdfII

share

license

bin other optionaletc docframe samplescdsuser local

.cdsinit

bin

.cdsplotinit

directories



3. If you use your own site .cdsinit, you must have the following load statement in yoursite .cdsinit to load the working directory .cdsinit.load “./.cdsinit”

4. Log out.



Creating the Training Account

If you already have a user1 account or another training account from previous Cadenceclasses that is available for use, refer to Installing the Course Database on page 7.

If you have not created a training account, follow the instructions below.

The recommended training account is user1. If preferred, you can give the user accountanother name, however, you must inform the instructor and students to update their labinstructions, which use user1.

Creating a user1 Training Account

1. Log in as root.

2. Determine the course database installation directory, for example, /usr/mnt.

3. Add a user1 account to the passwd file.

a. Edit the /etc/passwd file, using the vi editor. (You can use other editors)vi /etc/passwd

b. Add an entry similar to the following lineuser1::UID:GID:Training account:/home_directory/user1:/bin/csh

Use a unique UID (User ID) number for the account.

Replace GID with the appropriate Group ID number.

Replace home_directory with the path of the user1 home directory.

c. Save the file and exit the editor.

4. Give a password to the user1 account.passwd user1Changing password for user1New password:Retype new password:

5. Create the login directory for the account.cd home_directory

(where home_directory is the same path as specified above)mkdir user1chown -R user1 user1

6. Log out.



Installing the Course Database

Log in

accountto training

Set up thedot files

Yes

NoCTCclassroom

?

Review theREADME file

Log inas root

Runload.class

script

Rebootmachines

Checkresults

Yes

Networkaccess?

No

Loadtape

Copyfiles

Uncompressand tar data

Copy dotfiles

databaseand course

Review theREADME file



Installing the Course Database

You can install the course database one of two ways. One procedure applies to CadenceTraining Center Classroom installations (loading an entire Cadence facility classroom).The other procedure applies to all other course database installations, such as customer siteclassrooms, and individual workstation installations.

Before Installing the Database

Before you install the database, you need to be sure that you have the followingrequirements for installation.

■ Cadence software installed or available through file system mounts on each classroomworkstation.

■ Site customization file installed for Design Framework II-based products. Refer toSetting Up Design Framework II Site Customization on page 3.

■ X Window System installed on each workstation.

■ Motif or OPEN LOOK window manager available on each workstation.

■ 40 Mbytes disk space to load the data tape.(After you load the course database, look for the disk space requirements in the coursedatabase directory README file.)



Classroom Installation at Cadence Training Centers

The System Administrator at each Cadence Training Center is responsible for installing thecourse database in your classroom.

If you are installing the database in multiple classrooms, repeat the procedure for eachclassroom.

Log In and Run the Install Script

1. Log in as root on the nnn1 machine in the classroom.

Where nnn1 is the numbered “1” system in the classroom, for example, log in on trn21in classroom 2 or trn31 in classroom 3.

2. Start the load.class script. Enter/etc/load.class

3. Follow the instructions on screen.

The script loads the database on each system in the classroom and begins the test script oneach classroom system.

Check Results of the Test Script

1. Check the results of the load.class script. Look at /usr/mnt/training.log.userN (whereuserN is either user1 or user2).

2. Check the installation results from the test scripts. You can check the results byentering:retrieveTest

You are prompted to specify user1 or user2 by entering 1 or 2.

Each system that has finished running the test script, returns Pass or FAIL to indicatewhether the test script has completed. If the system did not run or complete the testscript, the system returns No match. If you get No match, check to see if the test scriptis still running.

3. If the test script returns FAIL, review the contents of the .test/results file in the coursedatabase directory for the specific test failures.

Review any README files for course-specific setup requirements. Refer to Contentsof the Course Database README File on page 12.

Review any specific plotter setups that are required for classroom installation. Refer toSetting Up Plotting on page 16.



Reboot the Workstations

If the installation test script results returns Pass, then reboot all the classroom systems. Youcan reboot all the classroom systems and skip Classroom Installation at Customer Sites andTesting the Installation and Copying the Database.

When rebooting the classroom workstations, start with the nnn1 and nnn8 workstations.These are the file servers for product software in the classroom. The servers need to beoperating before rebooting any of the other workstations. When the servers are online,reboot the other workstations in the classroom.

Classroom Installation at Customer Sites

Installations other than those at Cadence Training Center classrooms, follow thisprocedure. This procedure applies to updating individual workstations, on-sites, videos,and other systems outside the classroom.

This procedure shows you how to load the course database onto one system and copy thedatabase to multiple systems.

Because training accounts normally have limited access across company networks, werecommend that you load the data in a temporary directory before you copy the data to thetraining account.

These instructions are primarily for the System Administrator at the customer site.

Network Access

If you have network access to the Educational Services Group file server then you can copythe course database files across the network.

Copying the Data Across the Network

Determine the course database that you need to copy. The databases are located under /net/cds688/usr1/cadence/MASTERS/currentCourses. The files are compressed tar files. Youneed to copy the dotfiles and course database directories.

A README file in the MASTERS/currentCourses directory correlates the database andFrameMaker files with each course.

For example, to load the IC/ASIC Design Composition and Analysis class, entercp /net/cds688/usr1/cadence/MASTERS/currentCourses/dotfiles .cp /net/cds688/usr1/cadence/MASTERS/currentCourse/ICcae_4.3.tar.Z .



Loading the Database from Tape

If you do not have network access, you must copy the course database from tape.

1. Change to a temporary directory (a directory location to copy the data), as in thisexample.cd /tmp

2. Insert the tape in the tape drive.

3. Read the tape as shown in the example below.tar xvpf /dev/rst0

Note: Replace the tar command with the actual command for your platform. Commandsare listed in the table below. In the command line, tapeserver is the name of themachine that has the tape drive mounted.

If you have a tape drive on your machine, use the command listed under With a TapeDrive.If you do not have a tape drive on your machine, use the command listed under Withouta Tape Drive.

Uncompressing a Compressed Tar File

When you have loaded the tape or copied the files across the network, you have a dotfilesdirectory and a compressed tar file in your current directory.

1. List the directory contents, enterls

which returnsdotfilesICcae_4.3.tar.Z

Workstation With a Tape Drive Without a Tape Drive

Sun tar xvpf /dev/rst0 rsh tapeserver dd if=/dev/rst0 | tar xvpf - .

IBM tar xvpf /dev/rmt0 rsh tapeserver dd if=/dev/rmt0 | tar xvpf - .

DECstation tar xvpf/dev/rmt0h. rsh tapeserver dd if=/dev/rmt0h | tar xvpf - .

HP 700 tar xvf /dev/rmt/0m remsh tapeserver dd if=/dev/rmt0m | tar xvf -

Solaris tar xvpf/dev/rmt/0h rsh tapeserver dd if=/dev/rmt/0h | tar xvpf -



2. To uncompress the tar file, enteruncompress ICcae_4.3.tar.Z

The contents of the directory includes the dotfiles directory and the uncompressedcourse_database tar file. For example,dotfilesICcae_4.3.tar

Loading the Database from a Tar File

1. Entertar xvpf <tarfilename>

(On HP machines, do not use the p option with tar.)

For example, if your tar file name is /usr/tmp/ICcae_4.3.tar, entertar xvpf ICcae_4.3.tar

The contents of the directory include the course database directory.dotfilesICcae_4.3.tarICcae



Reviewing the README File

The Course Database README file is not viewable until the course database tar file hasbeen loaded.

Review the README file for size information before copying to the data to the trainingaccount. This is to make sure the training account has ample size for the data and the class.

The README file is in the course database directory.

1. Change to the course database directory. Entercd ICcae

2. Review the README file contents using the vi editor. Entervi README

Contents of the Course Database README File

The README file in the Course Database directory tells you

■ Disk space used by the database upon installation

■ Disk space required for the labs

■ Software products and licensing required for the course

■ Reference manuals available to the student

■ Any operating system requirements or plotters required for the class

■ Instructions for testing the course installation

■ Course developer name and telephone number

Copying the Dotfiles and Course Database Directories

1. Log out of root and log in again as user1, user2, or whatever name you chose for thetraining account login.

2. Copy the dotfiles and the course database directories to the training account logindirectory. For example, entercp -rp /usr/tmp/dotfiles .cp -rp /usr/tmp/ICcae .



After Installing the Database

After you install the database, you need to

■ Set up the training account dot files for your platform.

■ Set up training account variables (optional).

■ Customize the dot files (optional).

■ Set up the training account for plotting (optional). Plotting requires a configuration fileinstalled in the software hierarchy for Design Framework II-based courses that useplotters. Refer to the Setting Up Plotting on page 16.

Setting Up the Dot Files for Your Platform

The dot files are supplied with the training database.

The training database contains a dotfiles directory and the course database directory. Youcan have more than one course directory if you plan to have several classes one after theother.

After loading the database the training account looks like this.

dotfiles UNIX and X dot files (for example, .cshrc, .xinitrc) fordifferent platforms and the install script class_install.

<CourseName> the course directory, such as Layout, ossclass, Skill,ICcae.

dotfiles

/usr/mnt/user1

class_install other

<CourseName>

README other course filesfiles



Running the Class Install Script

The install script class_install sets up the dot files for your platform type. The install scriptsasks you for the following.

■ The Cadence software installation path. You must know this path before you run thescript.

■ The window manager you want to use, if you are on a SUN machine. You can chooseMotif or OPEN LOOK. On all other platforms, the window manager is Motif.

■ To run the install script, enter$HOME/dotfiles/class_install

After the install script runs, the training directory looks like this.

Setting Up Files and Variables for the Course (Optional)

The customary Cadence software hierarchy is shown below.

The course install script sets the CDS_INSTDIR variable in $HOME/.cshrc to point to theinstallation path of the software on your workstation.

tools/bin Executable files required to run the license daemons.

tools/dfII Design Framework II-based software.

share/license License and alias files. .

.mwmrc

/usr/mnt/user1

.login .cdsplotinit.cshrc .xinitrc .Xdefaults<CourseName>

README other course files

dotfiles/

tools

bin

<CDS_INSTDIR>

other toolsdfII

share

license



The Design Framework II software expects the following directories

■ <CDS_INSTDIR>/tools/bin/dfII/doc/help to contain the help files in FrameMakerformat.

■ <CDS_INSTDIR>/tools/bin/dfII/frame to contain the FrameMaker software to viewhelp files.

If the two directories above are not available, you cannot view online help files for DesignFramework II products. If FrameMaker and the help files are available elsewhere on yournetwork, modify $HOME/.cshrc and set the variables HELPDIR and FMHOME to point tothe correct directories. Source the .cshrc file before starting the Design Framework IIsoftware.

For instructions about installing the software, refer to the SoftShare Installation andLicense Management User Guide.

Customizing the Course for Different Platforms (Optional)

The install script, class_install, that you ran after loading the course database set up the dotfiles for the different platforms. You do not have to do anything else if you ran the installscript.

If you want to delete the dot files and set them up again, complete the following steps.

1. Delete the .cds_started file from your login directory. Enterrm $HOME/.cds_started

2. Log out and log in again.

If your platform does not read the .login file after you log in, enter$HOME/.login

The .login file in the training account customizes the account for various platforms andwindow managers.

3. If you are on a Sun, you are prompted for the window manager.

You can choose Motif or OPEN LOOK or exit without making any changes.

The .login script copies the platform-specific files to the account startup files (.cshrc,.xinitrc and so forth) and gives you a message similar to the following message.

Your course directory has been set up for an IBM machineto run the X Window System using the Motif Window Manager.

To start the X Window System type xwin

The .login script creates the .cds_started file in the training account.

Subsequent login sessions will not customize the startup files for the platform if the.cds_started file is in your login directory.



Setting Up Plotting

The customary Cadence software hierarchy is shown below.

Check the course database README file to see whether the course requires plotter access.

A sample plotter configuration file is included with the training account. You must makesure that the printer entry is present in the UNIX print environment in /etc/printcap.

1. You must have the .cdsplotinit in your login directory or in the installation hierarchyas shown above. Refer to the Plotter Configuration User Guide from Cadence.

2. The .cdsplotinit file does not exist in the login directory until you complete the dot filesetup. Refer to Setting Up the Dot Files for Your Platform on page 13.

Check the file ~/.cdsplotinit to see if you can use one of the entries in this file at your site.If you cannot use an entry

1. Log in as the user who owns the software installation directory.

2. Copy the file <CDS_INSTDIR>/tools/plot/etc/cdsplotinit to <CDS_INSTDIR>/tools/plot/.cdsplotinit and edit the file to create plotter entries for your plotter.

Example plotter names: Class Laserwriter or San Jose HP 7580

3. Log out.

Review the README File

Review the README file for any course-specific setup requirements of the databasebefore you copy the setup to multiple systems.

tools

other tools

<CDS_INSTDIR>

plotdfII

share

licensebin

.cdsplotinit



Testing the Installation and Copying the Database

Runtest script

Pass

Fail

Run testscript on

Copy thecourse data

each node

Callcourse

developer

No

YesCheckresults

Firstfail

?

Check

of test scriptrecommendations



Testing the Installation and Copying the Database

To test if the environment is set up correctly, type one or more of the following commands.which xinitwhich openwin (Sun only)which olwm (Sun only)which mwmwhich xtermwhich aixterm (IBM only)

Testing the installation and copying the course database is required only if you haveinstalled individual systems and need to verify your installation. If you are installing aCadence Training Center classroom, the testing and copying is part of the load.class script.

Running the Installation Test Script

1. Look in the README file in the course directory for instructions on how to test thecourse database installation.

2. Change to the course database directory. For example, entercd ~/ICcae

3. Run the test script, enter.testscript

Checking the Results

The test script will return Pass or FAIL to your screen. If the test script returns FAIL, thenreview the contents of the .test/results file in the course database directory for the specifictest failures. If there are multiple tests run as part of the course installation and they all fail,then most likely an installation or license problem is affecting all the tests.

If you are installing the database for an on-site class, licenses or products that were notpurchased might create a test failure. If this is the case, you might be required to skip partsof the course.

First Failure of the Test Script?

The test script results provide you with some possible ways to correct some failures.

1. Review the test script results. While in the course database directory, enterpage .test/results



2. Check for README File Recommendations

Review any README files for any course specific set up requirements that you mayhave overlooked or installed incorrectly.

3. Rerun the Test Script

If you made modifications to the installation based upon any recommendations fromthe test script or README, then rerun the test script and review the results.

4. Check the Results

Check the installation test script results.

Continued Failure of the Test Script?

If the test script again returns FAIL without justifiable missing software licenses due to thecustomer purchase and configuration, contact the course developer. The course developer’sname and number is located in the README file.



Copying the Data and Running the Test Script on Each Node

When you resolve all failures, copy the course database installation to other systems for theclassroom.

Running the Test Script on Each Node

Run the test script on each node and confirm the results. The results should be consistentwith the original installation on the first system.

Before Class Begins

Before class begins make sure you have the following

■ One workstation for every one or two students. If you are using several X terminalsconnected to a single workstation, the software might not function correctly.

■ One Training Guide for each student.

■ Reference manuals or online help available to students.

Introduction 1-1

Introduction

Objectives

■ Identify the course flow and the audience.

10/11/95 Cadence Design Systems, Inc. 1-2

Terms and Definitions

EDGE First generation Design Framework based IC design tools.

Introduction 1-3

Audience

Audience

■ New users who are digital IC design engineers

■ Users migrating from EDGE CAE tools


Audience

This course covers design composition, analysis, and the Cadence logic synthesis interface toprovide a detailed working knowledge of the design environment for digital IC designers. Theaudience is digital designers who are new users to the Design Framework II environment orcurrently users of EDGE front-end tools.

Introduction 1-5

Course Overview■ Using the Design Framework II environment

■ Design composition

■ Verilog integration

■ Cadence logic synthesis integration

■ Veritime integration

■ Running circuit simulation

■ Edge to Design Framework II database translation


Course Overview

Day 1

The first day of the course takes you through an introduction to the Design Framework IIenvironment and how to create schematics.

Day 2

The second day of the course concentrates on Verilog integration.

Day 3

The third day of the course covers Cadence logic synthesis interface, Veritime integration,other simulator-specific issues and EDGE database translation.

Using the Design Framework II Environment 2-1

Using the Design Framework II Environment

Objectives

■ Show the design flow within the Design Framework II environment.

■ Identify the resources required to start the Design Framework IIenvironment.

■ Learn how to get help.

■ Learn what you need to prepare before starting your project.

■ Learn how to create your project library.



library A library contains your design data and technology information.

cell A component such as a nand2 or ALU.

view A representation of a design, such as a schematic or layout. Theview that you choose determines which tool you use.

cellview A particular view of a cell, such as ALU schematic.

Library Browser A graphic window to display and access libraries in your DesignFramework II session.

CommandInterpreter Window

The control window that appears when you start the DesignFramework II environment. The Command Interpreter Window isalso known as the CIW.

SKILL A high-level programming language, based on LISP, that usesC-like syntax. Use the SKILL programming language tocustomize Cadence applications and integrate non-Cadence toolsinto the Cadence environment.


Software Overview

COMPUTER PLATFORM

(Sun, HP/Apollo, DEC, IBM)

OPERATING SYSTEM

(UNIX, Domain/IX)

X Window System

Motif or OPEN LOOK Window Manager

• • •

User Interaction

Design Framework II

Cadence ToolsCustomer

Tools


Software OverviewMultiple Layers

The Design Framework II environment resides on top of several layers of support software.One advantage of layered support software is the ease of achieving true platformindependence. Another advantage is enhanced capability for customizing tools with theSKILL programming language.

UNIX System

The lowest layer of support software is the operating system. The Design Framework IIenvironment is compatible with the UNIX operating system and the ULTRIX operatingsystem.

Window System

A windowing system enables you to run multiple tasks concurrently, each in a window. Youcan edit layout in one window, run SPICE simulations on it in another, and document resultsin yet another. The X Window System is highly portable because it is application-oriented.In such a window-based environment, other programs can easily share the screen withCadence tools.

The X Window System relies on a window manager to supervise the moving, resizing, andshuffling of windows on your screen. The Design Framework II environment employs theMotif software, the widely accepted window manager from Open Software Foundation. TheMotif window manager imparts a highly visual and tactile “look and feel” to the user interface.You can also use the OPEN LOOK window manager on Sun platforms.


IC Design Flow in Design Framework II

Verify LayoutiDRC, iLPE, iLVS, Dracula

Circuit SimulationSpice

IC Layout

BackannotationiSLC, DIVA, Dracula

OutputStream, PG/EB

IC Fabrication

Logic SimulationVerilog, Veritime

Logic DesignDE, Verilog

Circuit DesignDE

Full Custom Layout, LAS

Place and Route BE, CE, Cell3

Layout Synthesis

Translators

Plot

Plot


IC Design Flow in Design Framework II

Tool Descriptions

Design Entry Creates a logic or circuit design graphically

Verilog Logic simulation

SPICE Circuit simulation

Layout Editor/LAS Create full custom IC layout and cell and blocks

DIVA/DRACULA Verify IC layouts. Extract physical parameters for resimulation

Block Ensemble/Cell Ensemble/Cell 3 Ensemble/Gate Ensemble

Place and Route IC designs

Translators Translate data into and out from Design Framework IIdatabases

Plot Hardcopy output


ASIC Design Flow

SPFCDC

START

Design EntryMixed Level

High - LevelFloorplan

Preview

SPF

Composer

TimingAnalysis

Veritime

Preview - Place & Route

Detailed - LevelFloorplan

Preview

Reduced

TimingAnalysis

Veritime

SDF Delays

TimingAnalysis

Veritime

Prelayout

PostlayoutSimulation

Verilog

SimulationVerilog

CDC

Delay CalculatorCDC

CompareSimulation

Verilog

SynthesizeHDL Blocks

Synergy

SDF Constraints

SDFConstraints

SDF Delays

SDF Delays


ASIC Design Flow

The ASIC design flow may include design entry, logic simulation, floorplanning, synthesis,and timing analysis. This course focuses on using the Design Framework II based tools for ofdesign entry, logic simulation, synthesis and timing analysis.

Your ASIC vendor supplies a design kit, including libraries and vendor tools for creating yourASIC designs.


Starting the Design Framework II Environment

Login:Passwd:

host>Console

1

3

UNIX

X/Motif/OPEN LOOK

DesignFramework II

CIW

host> cds3 &Work

2Open Design Manager

mouse L: R:M:>

Quit . . .Library . . .Design . . .

Show File. . .Text Editor. . .

.cshrc

.login

.xinitrc

.Xdefaults

.mwmrc

.openwin-menu.cdsinit

clientsaliases.localkeymapprerequisites<license>


Starting the Design Framework II EnvironmentLogging into UNIX and Starting X

Log in at the UNIX level. Start the X Window System by entering the appropriate command,typically xinit. The X startup program looks for and executes an initialization script if found.The initialization file is .xinitrc in your home directory. All the applications in .xinitrc look forresources in .Xdefaults when they start. You can start X at boot time or at each login session.

Starting Design Framework II

When Design Framework II starts, the Command Interpreter Window (CIW) appears. The.cdsinit file customizes the Design Framework II environment. The environment reads onlythe first .cdsinit that it finds. The search order for the .cdsinit file is

(1) <install_dir>/tools/dfII/local(2) current working directory (directory where you started the software)(3) your login directory


The Role of the Command Interpreter Window

1Open Design Manager Technology File Utilities

Log: ~user1/CDS.log

Window Banner Log File

Input Pane: SKILL functions or expressionsmouse L: R:M:> Enter first point:

Output Pane:Running history of commandsSKILL function outputEvaluated SKILL expressionsStatus or error messages

Tool Prompt Line Mouse Button Cues

Translators Help

Output decided by Utilities ➝ Log Filter settings


The Role of the Command Interpreter Window■ First window to open when you start the software.

■ Console window for Design Framework II session.

■ All outputs, status messages, errors, and warnings appear in the CIW.

■ Enter SKILL commands in the CIW.

■ Reminds you of the next step in your design editor.

— The prompt line at the bottom of the CIW reminds you of the next step in carryingout a command.

Note: The CIW is designated as window 1. (Windows are numbered in the upper right corner.) Each subsequenttool window is consecutively numbered in the order in which you open it.

Log File

All input output information is recorded in a log file for later replay. The log file’s path isdisplayed on the CIW title bar. The output pane displays the log file with the current filtersetting. Set the filter by selecting Utilities ➝ Log Filter.


Basic Components of the Design Framework IIEnvironment

Library Browser A Form

A Design Entry Window

Title barStatus bannerMenu banner

Design area

Icon menu

Mouse definitions

Prompt line

Activates the form

Sets form to default valuesNo action

Radio buttons

Starts the Library Browser


Basic Components of the Design Framework II Environment■ Command Interpreter Window – CIW

The console window for Design Framework II. You can enter SKILL input functions inthe CIW, and all output goes to the CIW. To exit from the Design Framework IIenvironment, you close the CIW. Choose Open ➝ Quit to close the CIW.

■ Library Browser

This graphic window displays all the libraries available to you. You access the librariesthat contain your design from the Library Browser. Do all design file manipulation fromthe Library Browser. Do not use any UNIX commands. You can set the librariesavailable for your session in your startup file .cdsinit or through Design Manager ➝ SetSearch Path from the CIW. A library contains your designs and your processtechnology.

■ Design Entry Windows

These are tool windows from which you can read and edit your designs. You open adesign and the appropriate design window opens.

■ Forms

Temporary windows used to enter data or choices for a command. You press the Tabkey or move the cursor to go from one field to the next. Clicking OK or pressing theReturn key activates the command.


Using a Form

Output Stream DB ASCII Dump

Cancel Apply HelpOK

Stream Out

Template File

Retain Reference Library

Defaults

Top Cell Name mux2

Library Name classLib

Radio Buttons

Text EntryArea

Toggle Button

Run Directory .

Load Save

Library Browser

View Name layout

Reference Library Search Path diva.master

Library Version 5.0 n

Cyclic Field


Using a Form

Forms provide a place to enter the information required by a command.

The top of the form has a titlebar and a set of banner buttons. The body of the form containsprompts that tell you which option is being set. Next to the prompt is one of the following:

■ radio button, for choosing one of several options

■ text entry area, for typing information

■ toggle button, for turning options on or off

■ cyclic field, for choosing one of many options. Initially only one option is shown, but ifyou move the pointer to the field and hold down the left mouse button, the other optionsappear.

The form might also have buttons such as Browse, which shows a browser window, or MoreOptions, which displays another form.

When you cannot change an entry on a form, the name appears in gray instead of black, andthe text entry area is shaded. You cannot move the cursor into the text entry area.

■ Press the Tab key or mouse to move to the next text entry field.

■ Use the left and right arrows on the keyboard to move the cursor in a text entry field.

Press Control-a to go to the beginning of a line; Control-e to go to the end of a line;Control-u to erase to the beginning of a line.


Lab Overview

Lab 2-1 Starting the Design Framework II Environment


Lab Overview

Lab 2-1 shows you how to start the Design Framework II environment.


Getting HelpYou can get help with Cadence software from these sources

■ Help button on forms and windows

■ OpenBook utility

■ Installation manuals and Product Notes

■ Known Problems and Solutions (KP&S)

■ Reference manuals

■ Training guides

■ Customer Response Center (CRC)


Getting HelpOnline Help

■ The help button on Design Framework II windows and forms shows the referencemanual pages corresponding to the window or form. The help pages are subsets of thecomplete online reference manuals. Help pages are set up when you install theapplication software.

■ You start OpenBook from a UNIX shell. OpenBook lets you look at all the onlinereference manuals. The OpenBook utility is sent with the application software and mustbe installed separately from the application software.

Hardcopy

■ Installation manual, product notes and KP&S are hardcopy that is sent with the productshipment to the customer contact for your site.

■ Reference manuals are on CD-ROM or in hardcopy format. You can copy the referencemanuals from CD-ROM to a file system. You can view the reference manuals onCD-ROMs or on a file system using OpenBook.

■ Training guide (this manual is an example) can supplement reference manual.

Personal Contact

■ If you cannot find the necessary information with any of the above methods, you can callthe Customer Response Center at 1-800-CADENC2.


OpenBook■ Utility for reading

— Online Reference Manuals

— Known Problems and Solutions (KP&S)

— Installation instructions

— Product Notes

— User manuals

■ Finds manuals using

— Menus

— Keywords

— Text search

■ Electronic user notes to add information to documentation


OpenBook■ The online documentation is shipped as compressed PostScript files. The OpenBook

utility can read the compressed format. You can read and print all online manuals in thisformat.

■ Your documentation files can be anywhere on your network but must be accessible tothe OpenBook utility.

■ Access documents by menu, text search or keyword.

■ Keyword example:

openbook anasim - opens the Analog Artist Simulation EnvironmentReference

Keywords are in the Appendix of the OpenBook User Guide.

■ Text search is limited to a single document.

■ Full-Text Search spans the complete document set.

— You can restrict full-text search using boolean operation, proximity controls, andattribute selection.

— Full-Text Search examples:

analog artist |analog workbench - boolean operation

<TITLE analog artist> - attribute selection

analog:simulation - proximity control. Finds pages with the word analogclose to the word simulation.


Software Hierarchy

<install_dir>

tools.sun4

share license

license scripts<license file>aliases.localclientskeymapprerequisites

binetcframedoc/helpsamplescdsuserlocal

dfII

cds_rootopenbooklicense daemons

bin

tools

symboliclink

other productsdoc


Software Hierarchy■ All Cadence products are installed under a single hierarchy.

■ All products use the same licensing scheme.

■ Required files

— <install_dir>/tools/bin/cds_root - returns installation directory.Used by all products to help the product find the license directory.

— License daemons are in <install_dir>/tools/bin

■ The products are in <install_dir>/tools.<platform_architecture>/product.

■ As part of the software installation, you create the symbolic link <install_dir>/tools topoint to <install_dir>/tools.<platform_architecture>.

■ OpenBook

— startup script is <install_dir>/tools/bin/openbook

— The documentation and other setup files are in <install_dir>/share/doc


Lab Overview

Lab 2-2 Using OpenBook


Lab Overview

Lab 2-2 Use OpenBook to find information from the online reference manuals.


What Is a Project?

■ Designs

■ Team members

■ Roles each team member plays


What Is a Project?Designs

You might have one or more designs that make up this project. Each design can go throughdifferent stages, such as

design entrysimulationintegrated circuit layout

You need at least one library to hold your design.

Team Members

You might have different team members work on different parts of your design and ondifferent stages in the design process. For example:

Design Engineers perform design entry and simulation.

Mask designers perform IC layout and design rule checks.

Each stage of your design can be in a single library or different libraries.

In this section, you will look at how to keep your project in a single library.

Roles each team member plays

The roles of the team members help define the access they need to design file information. Thelevels of access include read, write, and delete privileges.


Creating a LibraryYou need to consider the following before you create your library

■ Physical path to the library

■ Other libraries needed for reference

■ Technology, including layers and design rules

■ Project team

■ Access permissions

You can change or add all of this information to the library after you create thelibrary.


Creating a LibraryPhysical Path to Libraries

You must define the library search path to create your project library and locate your referencelibraries. Keep your project library in a design directory instead of your login directory tree.

The following SKILL function defines the library search path to look in two locations to findDesign Framework II libraries.

dmSetLibPath(“/usr/mnt/designs /usr/mnt/references”)

Technology Data

■ Schematic design You can use the default layers supplied with the software.

■ IC design Must have process technology loaded into the library by this stage.

Project Team

■ Decide on team members and type of access required (read or edit).

■ If necessary, create a UNIX group entry for team members (root access required).

■ Enter the name of the team members or the UNIX group name in the library workinggroup or in the user group.

■ Define working group and user group access permissions (read, edit, delete).


The Library Structure

LIBRARYAttached

Technology FileCatalog File

cell A cell Ccell B

version

cellviewcellview cellview

viewTypeprop

version version


The Library StructureContents

A cell library is a collection of related cells. Each library corresponds to a specificprocess technology. The cells within that library are related because they all share thesame technology.

Technology File

Attached to every library is a technology file. This file is a large data file which specifiesall of the technology-dependent parameters associated with that particular library. Masklayer names and colors, design rules, symbolic device definitions, parasiticvalues—these technology-specific parameters are common to all cells in the library.

Reference and Design Libraries

Reference libraries typically contain well-characterized cells that you can instantiatein many different designs. Since one reference cell can be shared among multipledesigns, duplicate storage is eliminated. Design libraries contain cells currently underdevelopment by a particular user or group.

Fully Flat

Although a particular chip can include many levels of cell hierarchy, none of thishierarchical complexity is reflected in the libraries themselves. A library is simply aflat collection of cells. Details of design hierarchy exist inside the cellviews, whereveran instance of a lower level cell is contained in a cell. The library treats all cells thesame.


Accessing an Existing LibraryAll commands in the Library Browser

Caution

Do not use UNIX commands to manipulate designs. Use UNIX only to back up, copy, or move anentire library.


Accessing an Existing Library■ Choose Design Manager ➝ Library Browser from the CIW.

The libraries in the search path list appear on the Library Browser. You can expandthese libraries to show all the cells in the library. You can expand each cell to show thecellviews and versions of cellviews.

■ Press the middle mouse button on the library object and choose a command from thepull-down menu.

The two menus at the top part of the Library Browser have further data managementcommands. Commands ➝ Purge Versions allows the deletion of unwanted cellviewversions. Set Options ➝ Checkout Access allows you to specify access control onchecked out cellviews. (A checked out cellview is a cellview that is being edited.)

■ Backing up or moving your library

Back up or move your library directory tree and the catalog file <libname>.lib.


Lab Overview

Lab 2-3 Creating a Library


Lab Overview

Lab 2-3 creates a library using the default technology data provided by the system. You willuse this library for the remaining modules of the course.


SummaryYou have learned to

■ Create a new library for your project.

■ Find more information on how to do things by using OpenBook.


Summary

In this module, you have created a new library. You will use this library for the designs youcreate during this course.

You also learned how to use OpenBook. Use OpenBook as a resource during the course to findadditional information.

Design Entry 3-1

Design Entry

Objectives

■ Create schematics in the Cadence environment.

■ Check a schematic.

■ Generate cellviews from existing cellviews.

■ Plot schematics.



SRC Schematic Rules Checker

HDL Hardware Description Language

instance Component placement in a schematic

Design Entry 3-3

Contents of a Schematic

Pin

Component Instance

Wire


Contents of a Schematic

Schematics include component instances, pins, and wires.

Component instances represent lower levels of abstraction in a design. Component instancesare generally instances of the symbol view of a cell. An instance is identified by the cell itrepresents and the instance name. The instance name must be unique within a schematic. Thetable below describes the parameters and their values in the example:

Pins are the inputs and outputs of a schematic. Each pin is identified by its name. In theexample, pin C is one of the input pins. Pins with the same name in one schematic areconnected.

Wires connect the instance pins and schematic pins. You can use wide wires to indicatemultiple signals on a wire, but the system does not force or check that wide wires are used torepresent multiple signals. You can draw wires at any angle, but users frequently limit the useof wires to orthogonal lines.

Parameter Value in example

Library Name samples (not displayed by default)

Cell Name and2

View Name symbol (not displayed by default)

Instance Name I2

Design Entry 3-5

Schematic Entry Flow

Save

Check

Add Wires

Add Pins

Add Component Instances

Open Design


Schematic Entry Flow

You perform the following steps when creating a schematic.

1. Open the design, which can be a new or existing schematic.

2. Add component instances by placing symbols from libraries.

3. Add pins to indicate connections outside of this schematic.

4. Connect the components and pins using wires.

5. Check the design to ensure that it is correct.

Checking a schematic will be discussed later in this module.

6. Save the design to disk.

You generally add instances, pins, and wires in an iterative manner. You can add instances,pins, and wires in any order as you create your schematic.

Design Entry 3-7

Checking a Schematic■ Update connectivity

— Updates the connectivity of the schematic

— Allows you to make a netlist of the schematic

■ Schematic Rules Check

— Logical checks

— Physical checks

— Name checks

■ Cross-View Checker

— Checks for pin consistency between different views of a cell

— Pin names

— Pin direction


Checking a Schematic

Checking a schematic involves three operations:

■ Update connectivity includes naming each net in the schematic and checking that netwidths are consistent. For example, a connectivity check verifies that a 4-bit busconnects to a 4-bit pin. You must correct connectivity problems prior to going on to thenext design phase.

■ Schematic Rules Check checks the schematic against the rules you choose. The checksinclude

— logical checks, such as Floating Input Pins and Shorted Output Pins— physical checks, such as Unconnected Wires and Overlapping Instances— name checks such, as Verilog HDL Syntax and Net Name Expressions

■ Cross-View Checker checks the pin consistency between different views of the cell.You have control over which views are checked. Pin consistency checks

— Pin names

— Pin direction

Design Entry 3-9

Examples of Schematic Rule Checks

Logical Checks

ignored warning error

Physical Checks

Name Checks

Floating Input Pins

ignored warning errorShorted Output Pins

ignored warning errorUnconnected Wires

ignored warning errorOverlapping Instances

ignored warning errorName Collision

ignored warning errorVerilog HDL Syntax

Percent Overlap Allowed 20


Examples of Schematic Rule Checks

Logical Checks

Physical Checks

Name Checks

Floating Input Pins Checks for instance input pins and schematic output pins that are notconnected to instance output pins, schematic input pins, or I/O pins.

Floating Output Pins Checks for instance output pins and schematic input pins that are notconnected to instance input pins, schematic output pins, or I/O pins.

Unconnected Wires Checks for wire segments with end points that do not physicallyconnect to either a pin or other wire segments.

OverlappingInstances

Checks for instances that overlap other instances. Enter thePercent Overlap Allowed.

Percent OverlapAllowed

Sets the percentage of overlap between two instances.

Name Collision Checks for net names and instance names that match, such as aninstance named “ABC” and a net named “ABC”.

Verilog HDL Syntax Checks signal or instance names that collide with Verilog HDLreserved words or that are not valid Verilog HDL identifiers.

Design Entry 3-11

Schematic Check Severity■ Ignore

Check is not performed.

■ Warning

Check is performed.

Violations are reported and marked.

Problem does not have to be corrected before moving on to the next phaseof design.

■ Error

Check is performed.

Violations are reported and marked.

Problem must be corrected prior to moving on to the next phase of design.


Schematic Check Severity

There are three possible severities for the Schematic Rule Checks and the Cross-View Check.These severities are ignore, warning and error.

■ Ignore indicates that the check should not be run.

■ Warning runs the check, reports and marks violations. You do not have to correct theseproblems prior to moving on to the next design phase. These are non-fatal violations.

■ Error runs the check, reports and marks violations. You must correct these problemsprior to moving on to the next design phase. These are fatal violations.

Design Entry 3-13

Cross-View CheckerChecks for pin mismatches among the different views of a design.

module Decoder (XYZ, A1, A2, A3);output [0:7] XYZ;input A1;input A2;input A3;•••

endmodule

DecoderA1A2A3

XYZ<0:7>


Cross-View Checker

The Cross-View Checker checks the consistency of pins between the different cellviews of adesign. Each pins name and direction is checked.

Any mismatches found are marked in the design you run the Cross-View Checker from. Theerror will indicate where the mismatch exists.

In the example, the Cross-View Checker checks for the existence of the following pins:

Pin Name Pin Direction

A1 input

A2 input

A3 input

XYZ<0:7> output

Design Entry 3-15

Hierarchical Schematic

data<0:2>

012

01234567

DecoderA1A2A3

out<0>out<1>out<2>out<3>out<4>out<5>out<6>out<7>

IO

out<3:7>

out<0:2> A

INV_B

Y

I1<0:2>

O<0:2>


Hierarchical Schematic

You create hierarchy by placing instances in schematics. This is true for both top-down andbottom-up design styles. Your design is complete when all schematic hierarchy has beencompleted to primitive design components.

Hierarchy is represented in schematics by referencing the lower level cell with instances ofsymbols representing those cells. There is no limit on the number of levels of hierarchy youcan have in a schematic.

You can simplify your designs by using hierarchy.

Design Entry 3-17

Textual Design EntryHDL descriptions are included as part of the design hierarchy and library.

Typical view names include functional, behavioral, and system.

Cross-View Checker runs after editing HDL cellviews.

HDL descriptions can also be stored as text files outside of the DesignFramework II environment.


Textual Design Entry

You can include Verilog HDL descriptions in the Design Framework II libraries.

Typical view names include functional, behavioral, and system.

The Cross-View Checker and Verilog syntax check automatically runs when you completeedits on HDL views. If the symbol cellview does not exist, you can automatically generate itwhen you finish editing the HDL cellview.

Design Entry 3-19

Examples of a Functional Cellview

module adder4bit (Cout, S, A, B, Cin);output Cout;output [0:3] S;input [0:3] A;

•••

always @(A or B or Cin)beginSUM[0:4] = A+B+Cin;S = SUM [0:3];Cout = SUM[4];

endendmodule


Examples of a Functional Cellview

The example below is a Verilog description for a 4-bit adder.

module adder4bit (Cout, S, A, B, Cin);output Cout;output [0:3] S;input [0:3] A;input [0:3] B;input Cin;

reg [0:4] SUM;reg [0:3] S;reg Cout;wire [0:3] A, B;

always @(A or B or Cin)begin

SUM[0:4] = A+B+Cin;S = SUM [0:3];Cout = SUM[4];

endendmodule

Design Entry 3-21

Automatic Cellview Generation Flow

Existing CellviewInstancePin List

New Cellview

Cell Name andPin Information


Automatic Cellview Generation Flow

Automatic cellview generation helps you create various views of a design. The cellviews thatcan be created are schematic, symbol, functional, behavioral, and system.

Generated symbol cellviews include pins, rectangular graphic, and labels. Other generatedcellviews include only pin information. A generated schematic contains a sheet border andpins. Verilog HDL cellviews (functional, behavioral, or system) include a template Verilogdescription containing the module statement and the input and output pin declarations. Youmust complete the generated cellviews as you would if you created them from scratch.

Design Entry 3-23

Plotting SchematicsPlots are hardcopy output of your schematic.

Plotting options include

■ Plot Whole Cellview

■ Current Window

■ Plot Range for Current Cell

■ Hierarchy Scope

■ Start Plotting


Plotting Schematics

Schematics are plotted to generate hardcopy for communication and documentation purposes.When you are plotting, you have options which affect the plot generation. The plotting optionsinclude

Plot Option Plot Action

Plot Whole Cellview Plots the entire cellview

Current Window Plots the view area of the window

Plot Range for Current Cell Allows specification of current sheet, all sheets, or arange of sheets

Hierarchy Scope Allows specification of the levels of hierarchy to plot

Start Plotting Allows for plotting to be delayed until a later date

Design Entry 3-25

Lab Overview

Lab 3-1 Creating a Schematic with Fixed Menus

Lab 3-2 Automatically Creating a Symbol

Lab 3-3 Creating and Modifying a Hierarchical Schematic

Lab 3-4 Using Hierarchy Commands

Lab 3-5 Checking a Schematic

Lab 3-6 Creating a Verilog HDL Cellview

Lab 3-7 Plotting a Schematic (Optional)


Lab Overview

Lab 3-1 Create a schematic using the fixed menus.

Lab 3-2 Automatically create a symbol for use in hierarchical schematics.

Lab 3-3 Create and modify a hierarchical schematic.

Lab 3-4 Traverse the hierarchy of a schematic.

Lab 3-5 Check a schematic and analyze schematic connectivity, SRC, and cross-view checkresults.

Lab 3-6 Create a Verilog HDL cellview.

Lab 3-7 Generate a hardcopy of the full adder schematic.

Creating Schematic Symbols 4-1

Creating Schematic Symbols

Objectives

■ Create a symbol cellview with the symbol editor.

■ Create a symbol automatically.



TSG Text-to-Symbol Generator

interpreted label Labels that display the value of properties


Contents of a Symbol

YA

inv

[@ instanceName]

Selection box

Pin

Label

Symbol graphic


Contents of a Symbol

Schematic symbols include pins, symbol graphics, labels, and a selection box.

Pins are the inputs and outputs of a symbol. Each pin is identified by its name in the exampleabove, pin A is an input pin. The name and direction of pins in the symbol must match theinputs and outputs of the other cellviews of the same cell.

Symbol graphics define what you will see when this symbol is used in a schematic. The shapeof the symbol can indicate the way the cell functions, as in the inverter symbol above. Thesymbol graphic shape can be any size or shape that you like.

Labels in the symbol add to the documentation of the design. Labels commonly include thecell name and an interpreted label to display the instance name. Interpreted labels will bediscussed later in this module.

Selection box in the symbol defines the area of the symbol in which an instance can beselected. Generally, the selection box includes the complete symbol graphic and bisects thepins of the symbol. When the symbol is placed in a schematic, the cursor must be inside theselection box to select that instance. The wire router does not add wires inside the selectionbox. The selection box is not visible in schematics, but it is highlighted when the instance isselected. The selection box is also used as the symbol area during the schematic rule aboutoverlapping instances.


Symbol Creation Flow

Save

Check

Add Selection Box

Add Labels

Add Pins

Add Symbol Graphic

Open Design


Symbol Creation Flow

You perform the following steps when creating a symbol.

1. Open the design, which can be a new or existing symbol.

2. Add the symbol graphic.

3. Add pins to indicate connections to this cell.

4. Add labels to your symbol. These labels can be normal text or interpreted labels.

5. Add the selection box.

6. Check the symbol by running the Cross-View Checker.

This will check the consistency of the pins in your symbol and other cellviews of thesame cell.

7. Save the symbol to disk.

You generally add symbol graphics, pins, and labels in an iterative manner. You can addsymbol graphics, pins, and labels in any order as you create your symbol.


Interpreted LabelsInterpreted labels display property values as listed in the property list of theinstance.

YA

inv

[@ instanceName]

YA

inv

I0

OUTIN

Interpreted LabelDisplays Property Value


Interpreted Labels

Interpreted labels display the value of a property rather than the label text itself. This is a formof substitution expression. An interpreted label is created by the label text and the label type.The label text indicates which property value to display. The label type must be set toNLPLabel.

The most common use of interpreted labels in symbols is the instance label. The instance labeldisplays the name of the instance when you place it in the schematic. This label is created withthe [@instanceName] label text and the label type of NLPLabel.

In the example above, the instance name is I0.


Symbol Pins

A squareB roundC actHiD commActLoE ieeeActLoF block


Symbol Pins

The pin name and direction define the pin connectivity. The pins of a symbol must match thename and direction of the pins in the other cellviews of the cell.

You have choices about the pin types used in your symbols. The pin type visually modifies thesymbol. The pin types include square, round, actHi, commActLo, ieeeActLo, and block.


Automatic Symbol Generation Flow

ExistingText FilePin List

New Symbol

Text-to-Symbol

Cellview

Generator


Automatic Symbol Generation Flow

Automatic symbol generation helps you create symbols. An automatically generated symbolcellview includes pins, a rectangular graphic, and labels. You can modify an automaticallygenerated symbol by using the symbol editor. The primary ways to automatically createsymbols are: from another cellview, from a pin list, and from a text file.

■ Creating a symbol cellview from an existing cellview is the quickest way to create asymbol when another cellview of the cell exists. Creating a symbol from and existingcellview also ensures that the pins match between the cellviews.

■ Creating a symbol from a pin list is helpful when you are performing top-down designand want to create the symbol and use it in a higher level schematic. When you create asymbol from a pin list, you specify the pins (by pin type), library name, cell name, andview name of the cellview to be created.

■ Creating symbols from a text file is useful when creating a new library for which youhave a textual description of the cells including inputs and outputs. You create a text filein the TSG format. This file is then used to create your symbol. You can modify the textfile and regenerate the symbol if necessary. Refer to the Design Entry: ComposerReference Manual for more information about TSG.

When you create a symbol from an existing cellview or from a pin list, the systemautomatically generates a text file in the Text-to-Symbol Generator (TSG) format and usesTSG to create the symbol. You can optionally save the TSG file, modify it, and regeneratethe symbol from this text file.


Creating Block Diagrams

REG

I0OUT<0:3>

B<0:3> B<0:3>

ADDER

I1

A<0:3>A<0:3>

CL

K

CLK

regIn<0:3>SUM<0:3> pin<0:3>


Creating Block Diagrams

Creating a block diagram is useful with top-down design. You add a block to the high-levelschematic. As you add wires touching the edge of the block, pins are added to the symbolmaster. After the pins are added, you can modify the block pins from the schematic. The blockthat is created is the symbol for the lower level cellview.

When you begin the block creation, you indicate the library name, cell name and view nameto create. You have control over the block shape and size with different block samples.Additionally, you can indicate freeform and create a rectangle of any size.

After the pins have been added to your block diagram, you can modify each pin name anddirection by modifying the properties of the block instance.


Labs

Lab 4-1 Creating a Schematic Symbol with Fixed Menus

Lab 4-2 Creating a Symbol from an Existing Cellview

Lab 4-3 Creating Block Diagrams


Labs

Lab 4-1 Create a schematic symbol using the fixed menus.

Lab 4-2 Create and modify a symbol for use in hierarchical schematics.

Lab 4-3 Create a block diagram.

Using Verilog Integration 6-1

Using Verilog Integration

Objectives

■ Understand how to set up a Verilog simulation.

■ Understand the simulator options.

■ Know how to analyze simulation results.

■ Understand how to use the Design Hierarchy Browser.

■ Know how to compare simulation results.

■ Know how to import Verilog descriptions.



Verilog Language Hardware Description Language that has become the de factostandard.

Verilog-XL The Verilog simulator.

Verilog Interface The interface that runs Verilog-XL in the Design Framework IIenvironment.

SHM Simulator History Manager

DHB Design Hierarchy Browser

Verilog In The translator to import Verilog designs into the DesignFramework II environment


Using Verilog-XL in the Design Framework IIEnvironment

d<0:2>

012

<0><1><2><3><4><5><6><7>

A<2:0>

I1

out<7:0>

Decoder2

INV_B

Y

I3

P<0:4>

A YI4<0:3>

4

3:0In<3:6>

In<0:2>

Ad<3>

out2<0:7>

DecoderA1A2A3

out<0>out<1>out<2>out<3>out<4>out<5>out<6>out<7>

I0

INV_B

// Functional model for Decoder2

module Decoder2 (out, A);

output [7:0] out;

input [2:1] A;

endmodule


Using Verilog-XL in the Design Framework II Environment

You can create mixed-level design structures in the Design Framework II environment.Different blocks can be characterized in different ways. For example, the design structure maycontain behavioral, functional or system descriptions as well as schematic description.

The behavioral, functional, and system description are located in the corresponding text view.

The Verilog interface allows you to simulate a mixed-level design structure.


Simulation Flow

NetlistCreate Input

Stimuli

Simulate Select Nodes

Start Simulator

Set Options&

ViewWaveforms

ViewWaveforms

Compare

Schematic/TextWindow


Simulation Flow

Once you have created the schematic/text inside the Design Framework II environment, youneed to perform the following steps to run a simulation:

1. Bring up the simulator from the schematic or CIW.

2. Set the Options for netlisting, simulation, and waveforms.

3. Run the netlist. After running this step, the netlist is created. A testfixture file templateis also created to help the user create circuit stimulus.

4. Create the input stimuli - Edit a new testfixture file. The system copies the testfixturetemplate to this file.

5. Simulate - Run Verilog

6. View the simulation results - Look at the waveforms.

7. Compare waveforms: 1) Manually - by opening another waveform window (from aprevious run). 2) Automatically - the verilog interface has a compare command whichwill compare two waveforms and output the simulation differences to a file.

The user interface allows you to perform all of the above operations.


Starting the Simulator

■ Bring up simulator—execute command to start the Verilog-XL simulator.

■ Initialize a Run Directory—creates a UNIX run directory to store files.

■ Set OptionsThere are 3 main options to consider.

— Netlisting

— Simulation

— Waveform


Starting the Simulator

1. Bring up simulator. Execute the Verilog-XL simulator from (a) the CIW or (b) theTools menu inside a schematic/Text window.

2. Initialize a Run Directory. When you execute Verilog-XL (to bring up the simulator),an Initialization form pops up so you can to enter a run directory name. The RunDirectory is where all the information (files) relative to the current analysis run is goingto be stored.

When you enter a run directory name and OK the Initialization form, a UNIX rundirectory is created. This run directory stores all the files you need for the simulationrun (netlist file, stimulus file, log files and other). If the Run Directory already exists,then you are just setting up the pointers to work with that particular Run Directory.

By default, the run directory is created in the directory where you have started thesoftware from. You only need to enter the name of the run directory. Alternatively, youcan provide a full pathname and create the run directory anywhere in the UNIXhierarchy.

3. Set Options. There are 3 main options to consider: Netlisting, Simulation andWaveform.


Verilog Netlisting Options

Some of the options include

■ Netlist automatically to simulate design changes

■ Generate pin map

Important options

■ Netlist these views - functional behavioral schematic symbol

■ Stop netlisting at views - functional behavioral symbol


Verilog Netlisting Options

Netlisting produces a Verilog text description of your design. The Verilog-XL simulator usesthe netlist to produce the simulation results.

The Verilog-XL simulator automatically netlists your design before starting simulation, if itneeds to do so. If a netlist exists already and the design has not changed since the netlist wasproduced, the simulator does not netlist the design.

Generate Pin Map creates the pin mapping necessary to apply backannotation delay files forthis simulation.

Netlist These Views indicates the order of preference to use when netlisting the design, if acertain cell has more than one view. This view list defines which cellview is netlisted for eachcell in the design. For each cell, the netlister searches for a cellview from the list, in the orderof the list. It netlists the first cellview it finds that is in the view list.

The Stop Netlisting at Views controls the level of hierarchy at which netlisting stops. Afternetlisting a cellview, the Netlister checks if the view is on the Stop list. If it is, the netlisterstops expansion of the design for this cell. The stop list is not order specific.


Verilog Simulation Options

Some of the Simulation options include

■ Acceleration - (accelerate simulation of gates, switches, and/or other)

■ Delay - (control the Mode and Type)

■ Pulse Control - (how to handle pulses shorter than module delay)

■ Library Files - (path to file which contains verilog models - .v files)

■ Library Directories - (path to directory which contains verilog models)

■ Verilog-XL Executable - (path to the Verilog executable)


Verilog Simulation Options

Use Setup–Simulation to set standard Verilog options for enhancing your simulation. Theseoptions define how the simulation handles acceleration, delays, and pulses.

Acceleration allows you to specify the accelerated simulation of your design. Delays allowsyou to specify the delay mode and delay type. Pulse Control specifies how to handle pulsesshorter than or equal to a module path delay.

In addition, you can enter other standard Verilog options on the form displayed by thiscommand, and you can identify:

The Verilog executable that you want to use.

The Verilog libraries used in your design.


Verilog Waveform Options

Waveform Display Packages

■ cWaves

■ gr_waves

Save Signal Options

■ All Signals

■ Top Level Primary I/O

■ The Same Signals - signals that you saved during the previous simulationin this run directory

■ Design Selections - if you are simulating a schematic, the signals that arecurrently selected on the schematic


Verilog Waveform Options

The waveform database contains the signals that you can view with your waveform package.

Use Setup–Record Signals to select the signals to be saved in the waveform database

Select signals on the schematic, so that you can specify the selected set as the signals tobe saved with Setup–Record Signals.

Setup–Record Signals lets you choose between saving

All signals

The top-level primary I/O

The signals that you saved during the previous simulation in this run directory

If you are simulating a schematic, the signals that are currently selected on the schematic.


Test Fixture File Template

‘timescale 1ns / 1ns

module test;wire CarryHi, CarryLo;reg CLK, CLR;wire [15:0] Q;

COUNTER top(CLK, CLR, Q, CarryLo, CarryHi);

// Default verilog stimulusinitialbegin

CLK = 1’b0; CLR = 1’b0;end

// Enter additional stimulus here

endmodule

Stimulus

Edit or Create

Test fixture

Netlister

produces

test fixture

template


Test Fixture File Template

The module that applies stimulus during simulation is called a test fixture. In the Verilogsimulation environment, you can create and maintain multiple test fixtures in one rundirectory, edit test fixtures, and switch among them as appropriate for each simulation run.

A test fixture template is created after the netlister runs. To create the test fixture file, you canuse this template, which provides an instance of the top-level module and default inputs (setto zero).


The Verilog Window


The Verilog Window

The Verilog window appears after you execute the Setup Environment form. You use theVerilog window to access all the commands for running and controlling simulation.

In the Verilog window, you can see the Verilog-XL executable version and all the files thathave been compiled. It also displays the Verilog-XL simulation output and lets you interactwith the simulator.

The Menus in the Verilog window is where you access Verilog-XL Integration commands.You can also type in Verilog interactive commands on the bottom line of the window.

The Icons are used for executing interactive simulation commands. Most of the icons aregrayed out when you first enter the simulation environment because the simulator is not yetrunning.


Adding Breakpoints


Adding Breakpoints

Use the Set Breakpoint form to set multiple breakpoints.The breakpoints can be all of the same type or of different types.Click on one or more of the four breakpoint type buttons to set breakpoints of those types.

Time Sets a time-based breakpoint. You specify it in simulation time units. You can specify atime-based breakpoint as an Absolute or Relative value. In addition you can specify thebreakpoint to occur Before or After the indicated time. The Verilog-XL system task equivalentsare $db_breakbeforetime and $db_breakaftertime.

Transition Sets a transition-based breakpoint. The Verilog-XL system task equivalents are:$db_breakonposedge, $db_breakonceonposedge, $db_breakonnegedge,$db_breakonceonnegedge, $db_breakwhen, and $db_breakoncewhen.

Signal Specifies the name of the Verilog-XL object on which the transition is taking place.You can specify the active edge of the signal at which the breakpoint should occur:Positive Edge, Negative Edge or Any Edge.

Value Sets a value-based breakpoint. The Verilog-XL system task equivalents are $db_breakwhen and$db_breakoncewhen.

Source Sets a source line-based breakpoint. The Verilog-XL system task equivalents are$db_breakatline and $db_breakonceatline.

Line # Specifies the line number of the Verilog-XL source text at which the breakpoint isbeing defined.

File Specifies the full pathname of the file that contains the Verilog-XL source text atwhich the breakpoint is being defined.

Scope Specifies the scope of the Verilog-XL source text at which the breakpoint is beingdefined.


Adding Patches


Adding Patches

Patchtool ➝ Commands

■ Add a patch.

■ Delete a patch.

The Add command adds a patch to the patch list.

Signal Specifies the name of the net or register on which the patch is being placed.

Value Specifies that the net or register is being forced to:

0 a logical zero.

1 a logical one.

X a value of unknown.

Z specifies that the net or register is being forced to a value of highimpedance.

Other Specifies the exact value or function that the net or reg. is being forced to.


Run Directory Contents

Environment Information si.env

Stimulus files testfixture.v

Netlist information ihnl directory

Models Directory hdlFilesDir

Simulation History shmDir

Miscellaneous files simout.tmp, verilog.key.


Run Directory Contents

In the run directory, you will have the information corresponding to the current run.

Environmentinformation

design information (library name, cell name, view name, simulator,library path, view list, stop list, etc.). All of this information is kept in thesi.env file.

Stimulus files You have the option to create a stimulus by using a testfixture templatecreated in the run directory as a file referred to as: testfixture.template.First, you have to netlist the design for the interface to pick up theinformation relative to the ports of the design.

Note: Alternatively you may use STL (Simulation and Test Language) to generate thestimulus, which is then compiled and targeted to Verilog. The way the simulationworks in this case is controlled by the “control” file. This control file is created inthe run directory when you execute the initialization command.

NetlistInformation

The Verilog netlister is hierarchical and works in an incremental form. Ifafter the netlister runs for the first time, you need to modify part of yourdesign, the netlister, when reinvoked takes care of the differences.

Models directory In the hdlFilesDir directory, you will find an updated version of themodels being used in the current simulation.

SimulationHistory

Management information is stored in the shmDir directory. This is thedatabase for the current simulation and is used by cWaves to showgraphically the results of the simulation.


The ihnl Directory

cds0 cdsncds1

netlistnetlist netlist

ihnl

...

...


The ihnl Directory

Use the Incremental Hierarchical Netlister to renetlist an entire design or the individualsubblocks that you modify. When you debug a design, it provides a fast way to update thenetlist.

When you run the netlist command, in your run directory, the ihnl directory is generated,containing one subdirectory for every subblock in the design. These subdirectories are namedcds0, cds1, ... cdsn.

Each cdsn directory contains the netlist file that corresponds to that part of the design.

When you resimulate a design, the netlister creates or updates the netlist automatically. Do notmodify the individual netlist files directly.


Lab Overview

Lab 6-1 Running a Verilog-XL Simulation

Lab 6-2 Simulating a Schematic with Verilog-XL


Lab Overview

Lab 6-1 Simulate the 4-bit adder functional cellview and analyze the simulation results.

Lab 6-2 Simulate a hierarchical schematic and view the results.


The Hierarchy BrowserThe Hierarchy Browser displays the hierarchy of a design.

test

I3Mux 16

I2AB_ShiftReg

I1 I0Pulse Counter

SH2 SH3 SH4 SH1AB_ShiftR AB_ShiftR AB_ShiftR AB_ShiftR

top

Top_Level


The Hierarchy Browser

The Hierarchy Browser displays the hierarchy of module instances in a design. The commandsin the Hierarchy Browser window change the display, display the contents of modules in theSource Text Viewing or Schematic Editing windows, and display information about thenetlist, modules, and UDPs in the design. You can select a module instance in the HierarchyBrowser to set scope, focus, or synthesis constraints in another window.

The commands in the Hierarchy Browser window select modules for viewing in the Schematicwindow or Source Text View window (STV) to show a text description.


Simulation ComparisonCompare two simulation runs automatically.

Current Run Directory

cWaves Database

Golden Run Directory

cWaves DatabaseSimCompare . . . .. . . .

Results File

.

.

Specify Compare

Cycle TimeStrobe OffsetStrobe Width

Primary Outputs

Probed NodesPrimary I/O


Simulation Comparison

The Simulation Comparison command compares two cWaves databases in two different rundirectories (from the current run directory to a golden run directory). The cWaves database fileis called shm.db. It is located under shmDir.

UNIX structure:

Run Directory

shmDir

shm.db


Simulation Comparison Variables

CLK

DATA

strobeoffset

cycletime

strobewidth

= comparison area


Simulation Comparison Variables

You specify the cycle time, strobe offset, and strobe width used for the simulation resultscomparison.

Cycle Time Length of simulation time during which a singlecomparison occurs

Strobe Offset Moment (in simulation time) within the cycle timewhen a comparison begins.

Strobe Width Simulation time within the cycle time that thecomparison (strobe comparison) takes tocomplete


Importing Verilog Descriptions■ Imports existing Verilog HDL designs.

■ Imports Verilog text libraries.

UNIX OperatingSystem

Design Framework IIEnvironment

Mixed LevelVerilog Design/Verilog Library

Schematic

Symbol

FunctionalVerilogImport

Netlist


Importing Verilog Descriptions

The Verilog In translator brings in a mixed-level (structural and behavioral) HDL text filefrom a UNIX directory into the Design Framework II environment. It can translate an HDLdesign or library files.

The translator imports the HDL file module by module. If a module to be imported isbehavioral, it is installed as a functional cellview. If the module is structural, an equivalentschematic is created and installed as a schematic cellview.

If a module to be imported does not have a corresponding cell, a cell is created in the targetlibrary with the same name as the module and a symbol is created for the cell based on themodule I/O.

If a cell corresponding to the module is found in a reference library, port checking between themodule and the existing cell is performed, but the module is not imported.


Inputs to Verilog In■ Target library

■ Reference libraries

■ Verilog design files

■ Log file name


Inputs to Verilog In

The inputs to Verilog In include,

Input Function

Target Library Design Framework II library name for Verilog In output to beplaced in

Reference LIbraries List of libraries containing Design Framework II cellsreferenced by the design being translated

Verilog Design Files List of Verilog HDL files to be translated

Log file name File name for the Verilog In log file


Outputs of Verilog InThe Verilog In translator produces these outputs

■ symbol cellview for each module

■ schematic cellview for each structural description

■ functional cellview for each behavioral description

■ Log file summarizing the translation results


Outputs of Verilog In

Verilog In generates a symbol for each module in the Verilog input files. These symbols arerectangular symbols similar to those generated by the automatic cellview generationcommands. These symbols may be modified after creation, but if you modify any of the pinlocations, the schematics containing the symbols must be modified as well.

Each structural Verilog description results in a schematic. Cells that exist in the referencelibraries are used in the schematic. You can modify the generated schematic using theschematic editor.

Each behavioral Verilog description is translated into a functional cellview in the library.

The log file summarizes the translation results. It is typically saved in the current workingdirectory.


Netlist Flow

Netlist Current Cellview

Top Level

StoppingView?

Netlist Complete

No

No

Yes

Yes

No

No

Yes

Yes

Traverse intoInstance

Go Up One Level

All CellsNetlisted?

TopLevel? Top

Level?


Netlist Flow

A design is netlisted by starting at the top level of the hierarchy and generating a netlist filefor each cell in the hierarchy. Certain views are indicated as stopping views, and anorder-specific list of views control the hierarchy traversal.

1. The netlister traverses into a cellview existing in the view list.

2. This cellview is used for netlisting the cell.

3. A view list and a stop list control the hierarchy expansion.

4. When a netlist is generated for a cellview in the stop list, hierarchy traversal stops.

5. If a cellview is not in the stop list, then the system uses the view list to determine thecellview to descend into.

6. This process is repeated for all cellviews in the design.


View List and Stop View List

■ View list controls which cellviews are selected to netlist.

■ View list is order specific.

■ Example view list: functional behavioral schematic symbol

■ Stop view list controls which cellviews hierarchy traversal is complete.

■ Stop view list is not order specific.

■ Example stop view list: functional behavioral symbol


View List and Stop View List

The view list controls which cellviews are selected to netlist. Beginning with the first cellviewin the list, the netlister traverses the view list in order until an existing cellview is found. Thiscellview is then used for netlisting the cell.

The view list is order specific. Modifying the order of the view list can modify the resultingnetlist.

An example view list

functional behavioral schematic symbol

The stop view list controls which cellviews hierarchy traversal is complete. After the netlist isgenerated for a cellview, it is checked against the stop view list. If the current cellview is inthe stop view list, then the netlister stops expansion of the design at this level.

Stop view list is not order specific. Only the existence of the cellview is checked.

Example stop view list

functional behavioral symbol


Netlisting Example

■ view list = behavioral schematic symbol

■ stop list = behavioral symbol

■ Symbol view exists for all cells

A

C

fun beh beh

F

sch sch

fun beh

G

beh fun

B D

E E

sch

behbeh


Netlisting Example

The netlist for the above example will include the following:

A, schematic

B, schematic

E, behavioral

F, behavioral

C, behavioral

D, behavioral

Because behavioral exists in the view list before schematic, the D behavioral cellview isnetlisted rather than D schematic and its contents.


Netlisting ExerciseWhich cellviews will be netlisted given the following view list and stop list?

■ view list = functional schematic behavioral symbol

■ stop list = behavioral functional symbol

■ Symbol cellview exists for all cells.

A

C

fun beh beh

F

sch sch

funbeh beh

G

beh fun

B D

E E

sch

beh


Netlisting Exercise

List the cellviews that will be netlisted from the above view list and stop list.


Lab Overview

Lab 6-3 Comparing Verilog-XL Simulations

Lab 6-4 Using Verilog In

Lab 6-5 Simulating a Mixed-Level Design


Lab Overview

Lab 6-3 Compare the results of two simulation runs.

Lab 6-4 Import an existing mixed-level verilog design.

Lab 6-5 Simulate a mixed-level design and view the results.

Using Synergy Interface 7-1

Using Synergy Interface

Objectives

■ Understand the basics of logic synthesis.

■ Interface to the Cadence HDL Synthesizer and Optimizer.

— Synthesize HDL blocks.

— Understand how external conditions affect synthesis results.



synthesize Converts HDL design files to logic-level implementation.

optimize Maps a design to a specific technology. The implementation canbe optimized to meet specific design goals.


What Is Synthesis?Translate register transfer level (RTL) and structural level designs into a librarycell netlist.

b

s’out

a

N23N31

out = s’(a+b) + sab

HDL Synthesis

Technology-SpecificOptimization and Mapping

out = s’b + s’a + sab

Technology-IndependentOptimization

module s_o_a (out, a, b, s);output out; input a,b,s;reg out;

always @(a or b or s)case (s)

1’b0 : out = a | b;1’b1 : out = a & b;

endcaseendmodule


Logic Synthesis

Synthesis integrates two processes: translation and optimization.

■ During the translation step, a gate-level circuit netlist is translated and synthesized.

■ During the optimization step, the gate-level netlist is refined for area and speedrequirements that the designer specifies in a constraint file. Then the netlist is mappedinto gates based upon the given design constraints.


Logic Synthesis Steps

■ Synthesize a design.

■ Display reports.

■ Display a synthesized schematic.

■ Install a synthesized schematic into the Cadence library.

Text file gate-level schematic

Optimize area and timing


Logic Synthesis Steps■ Synthesize a design in one or both of these ways:

— Convert a text design file to a gate-level schematic and a gate-level netlist.

— Optimize a hierarchical gate-level schematic to improve design timing, chip area, orboth.

■ Display reports.

■ Display synthesized schematic.

■ Display synthesized schematic into the Cadence library.

Typically design synthesis is performed iteratively, exploring design trade-offs by varyingdesign synthesis constraints.


Cadence Synthesis Interface

OptimizedSchematic

Reports

schematic

symbol

functional VerilogNetlist

OptimizedNetlist

SourceLibrary

TargetLibrary

SymbolLibrary

Netlister Synthesis

SchematicGeneration


Cadence Synthesis Interface

A completed schematic, behavioral, or mixed-level design is automatically netlisted for theVerilog software before entering the HDL Synthesizer . The synthesis and optimizationprocess produces an optimized netlist which can be generated to an optimized schematic.

The synthesis libraries involved are

Source library defines the function of a cell in the source design

Target library defines the functionality, timing and cost for the targettechnology

Symbol library symbols that correspond to the cells defined in the target library,referenced during schematic creation. If no symbol libraryexists, the system generates generic symbols.


Synthesis Library■ Source library defines the functionality of each cell in the source design.

■ Target library defines the functionality, timing and cost for each cell in thetarget library.

■ Sample synthesis library definition

module Inv(Y,A);input A;output Y;

specifyspecparam cell_area=155.52;specparam block_delay=0.27;(A=>Y)=(block_delay, block_delay);specparam resistance$Y=0.6;specparam slope$Y=0.1;specparam capacitance$A=0.055;

endspecify

not(Y,A);endmodule


Synthesis Library

Source Library is the library that HDL Synthesizer searches to determine the function ofmodule instances used in your HDL source description.

Target library is the library that your design is mapped to during optimization.

Synthesis libraries are Verilog libraries that are created or modified for use with synthesis.Library developers add timing and cost information to each cell, and if necessary, modify thecell’s functional description so that it meets the synthesis style guidelines.

Library developers also compile the library to insure that all the cells can be recognized by theHDL Synthesizer and Optimizer software, and to verify that there is sufficient cost and timingdata for each cell to guarantee good optimization of the design. This translation process createsa synthesis view of the library that is used by HDL Synthesizer and Optimizer duringoptimization and mapping.

The Synthesis Style Guide describes how to use Verilog constructs in creating models to besynthesized by HDL Synthesizer. When writing models for synthesis, you are not restricted toa subset of Verilog constructs however, the way you use the constructs determines the type ofoutput you get from HDL Synthesizer. The guide introduces the key concepts of themixed-level synthesis modeling style (modeling combinational and sequential logic).


HDL Synthesizer and Optimizer

RTL, Structural,or Mixed Level

Verilog HDL

OptimizedVerilog Netlist

HDLSynthesizer

LogicLevel

Results

OptimizedSchematic

SDFConstraints

Optimizer

StructuralVerilog Netlist

SPF


HDL Synthesizer and Optimizer

HDL Synthesizer and Optimizer are the Cadence products that allow you to perform synthesisand optimization tasks in a mixed-level design flow.

HDL Synthesizer and Optimizer share a common interface and can function together as asingle seamless tool or separately, allowing you to customize your design flow for specificapplications.

HDL Synthesizer synthesizes Register Transfer Level (RTL) or mixed-level HDL designs andpasses logic level results to the Optimizer. The Optimizer then optimizes and maps theseresults to a technology-specific library an d generates a netlist.

Used alone, the Optimizer optimizes a Verilog netlist while attempting to meet the goals setfor cost parameters such as area and timing. The Optimizer then maps the optimized design toa technology-specific library and generates a netlist.

The Optimizer can read in a Standard Parasitic File (SPF) generated by the Preview

floorplanner software.


Synthesizer/Optimizer User Interface

Using the synthesizer/optimizer user interface you can:

■ Set up your work session environment.

■ Netlist a Composer design for Synergy.

■ Set design constraints.

■ Execute synthesis and optimization runs.

■ View results.


Synthesizer/Optimizer User Interface

You can bring up the window from either a Source Text Viewing (STV) window or theschematic editor.


Categories of Constraints

Complex Operator

■ Control arithmetic operations in your design.

■ Share resources of adders and subtracters.

Module Generation

■ Partition a section of a module in your design.


Categories of Constraints■ Complex Operator

Arithmetic operations require significant hardware. You can use the complex operatorconstraint to require HDL Synthesizer and Optimizer to share resources such as adders,comparators and subtractors.

■ Module Generation

The HDL synthesizer lets you generate different implementations for complexoperators and memory. With a module generation constraint, you can:

— Generate a different implementation if your target library does not containappropriate parts or parts with the correct bit-width for a particular operation.

— Create behavioral modules to partition the sections of your design you do not wantsynthesized.

— Experiment with different implementations of your designs.


Categories of Constraints (continued)

Attributes

Synthesize Design flattened and synthesized.

Preserve Selected objects not synthesized.

Preserve Hierarchy Tree Selected objects synthesized and optimizedseparately downward through hierarchy.

Preserve Hierarchy Selected objects synthesized and optimizedseparately.

Expand Hierarchy Tree Selected objects flattened.



Attributes

Synthesize Indicates that the selected objects will be flattened and synthesizedwith the rest of the design.

PreserveHierarchy

Indicates that the selected objects, such as modules, moduleinstances or functions, will be synthesized and optimized separatelyfrom the rest of the design. This constraint does not apply down thedesign hierarchy.

PreserveHierarchy Tree

Indicates that the selected objects, either modules or moduleinstances, will be synthesized and optimized separately from the restof the design. This constraint applies down the design hierarchy.

ExpandHierarchy Tree

Used in conjunction with the preserve hierarchy tree constraint andindicates that the selected objects, either modules or moduleinstances, will be flattened, synthesized, and optimized with the restof the design. This constraint applies down the design hierarchy.

Preserve Indicates that the selected objects, such as modules, moduleinstances, registers, or wires, will be retained without modification inthe synthesized design. This constraint applies down the designhierarchy.



■ Finite state machine

Implicit and explicit modelling

■ Preferred library parts

Restricts target library parts that the HDL Synthesizer uses to implementyour design.



Finite State Machines

In a sequential circuit, the outputs of the circuit are a function not only of its external inputs,but also the present condition or state of the circuit. If a circuit has more than one state, thereis a state register to hold an encoded representation of the current state. The contents of thestate register and any external inputs determine the activity that occurs in the internal dataregisters of the circuit and on its outputs when a clock transition occurs.

A Finite State Machine (FSM) description enumerates all possible states of a sequential circuitand the conditions under which each state occurs. HDL Synthesizer recognizes two types ofFSM descriptions — implicit and explicit. For an implicit FSM description, you describe onlythe activity that takes place within each state; HDL Synthesizer creates a state register for youand extracts from your description the control logic that determines state transitions. For anexplicit FSM description, you specify the state register and control the sequence of states bymaking explicit assignments to the state register within each state.

Preferred Library Parts

Selecting preferred library parts permits you to enable and disable specific parts in the targetlibrary. This might have the added benefit of cutting down on run time; by limiting the numberof choices for implementing a design, you might shorten the time it takes HDL Synthesizer tomap your design to library parts.



■ Cost

Sets an upper area limit

■ Timing

— Input (rise and fall edges of input signal arrival)

— Output (rise and fall edges of output signal)

■ Report

Allows you to control the generation of timing reports for objects in yourdesign, and to specify the level of detail in each report.



CostSets an upper limit on the area of the selected modules or the entire design (global). The constraint is agoal rather than a control, however, so the synthesized design may be in violation of this constraint. Inthis case, the violation is noted in the synthesis reports. The value you choose must be consistent withthe unit of measurement of the target library.

TimingArrival Rise/Fall Delay specifies when the rising/falling edge arrives on the selected module inputs. Thisconstraint overrides the default arrival rise time set in the Global Constraint form. It is a control, so thesynthesized design will never violate.Required Rise/Fall Delay specifies when the rising/falling edge arrives on the selected module outputs.This constraint overrides default required rise time set in the Global Constraint form.

ReportBy default, Optimizer outputs a timing report for a single object in your design, the top-level module.The timing report includes the longest and shortest path for each end point in the top-level module. Anend point is the end of a timing path, including such points as data inputs to storage devices, inputs toblack boxes, or primary outputs.

You can generate reports for any module or module output port in your design, regardless of its level inthe design hierarchy. You can also specify whether you want the short or detailed timing report formatand what types of paths you want reported: longest, or shortest, or both. For modules, you can alsospecify the maximum number of end points to be reported.


Applying ConstraintsYou can apply constraints at the following scopes:

■ Global

■ Modules

■ Module Instance

Constraint Types and Scope:

Constraint Goal Control Global Module Instance

Cost

Timing

Attribute

FSM

Preferred Parts

Complex Operators

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X X


Applying Constraints

You can direct and control the synthesis process by setting constraints on design objects.Constraints function as either goals or controls during the synthesis and optimization process.

The constraint goals you can set include maximum cost and maximum delay for your design.HDL Synthesizer and Optimizer produce a design that meets these goals as closely as possible;however, sometimes these constraints cannot be met. For example, a maximum cost constraintof zero is not attainable for any design. In this case, HDL Synthesizer and Optimizer producea design with the smallest possible cost, and the constraint violation appears in the reports.

The constraint controls you set affect the way HDL Synthesizer and Optimizer synthesizeportions of your design. For example, when you preserve portions of your design, theseobjects pass without modification into the synthesized design. HDL Synthesizer andOptimizer never produce a circuit that is in violation of these controls.


Timing-Driven Synthesis■ Constraints ➝ Read SPF

■ Using a Standard Parasitic File (SPF) from the floorplanner, HDLSynthesizer and Optimizer generates a timing-driven synthesizedimplementation of your design.

Reduced SPF

Preview

Floorplanner

HDL

Synthesizer &

Optimizer


Timing-Driven Synthesis

HDL Synthesizer and Optimizer working with Preview (Cadence’s Advanced DesignPlanner) produce more efficient synthesized designs. Using a Standard Parasitic File (SPF)from the floorplanner, HDL Synthesizer and Optimizer generate a timing-driven synthesizedimplementation of your design. This allows you to meet timing considerations in your designfaster and more accurately than ever.

HDL Synthesizer and Optimizer take the extracted interconnect capacitance from the SPF andthe value of the Universal Input Load and places a constraint on the output port of the selectedcell. HDL Synthesizer and Optimizer use the largest load value of any instantiated module.

The design flow for this new integration is as follows:

1. HDL Synthesizer and Optimizer generate a netlist and schematic from your HDLdesign.

2. Preview reads the schematic to produce a floorplan.

3. Preview extracts interconnect capacitance information from the floor plan andgenerates an SPF in a SPICE-like format.

4. HDL Synthesizer and Optimizer read in the SPF information from which a timing-basednetlist/schematic and an SDF is generated.

5. Preview then reads in the optimized schematic and generates a better floorplan.

6. Cadence’s layout tools, Gate Ensemble and Cell3 reads the SDF for place and route.


Layout Intelligent OptimizationYou can run the Optimizer software in a “layout intelligent” fashion to address thefollowing Place and Route (P&R) issues:

■ Routability

■ P&R runtime

■ Die size (standard cell designs)


Layout Intelligent Optimization

Layout Intelligent Optimization (LIO) performs optimization using technology libraryinformation but without access to a P&R tool. It generates netlists that can subsequently beplaced and routed using Gate Ensemble, Cell3 or Cell Ensemble.

LIO optimizes the circuit, choosing cells and cell combinations that are likely to lead to lessinterconnect and that are likely to cause less congestion on the chip. When it synthesizes adesign, it considers the impact of interconnect on placement and routing, and how easy thecells are to route over (how “porous” the cells are). By making such considerations, it tends toproduce: (1) less congestion and more routable designs (so the P&R runtime is shorter) (2)smaller die sizes for standard cell designs (since less area is devoted to interconnect) (3)shorter wires (which can lead to faster designs).


Types of Synthesis Runs

Type of Run Application

Normal Synthesizes and optimizes an RTL design, oroptimizes and maps a structural design.

Trade-Off Curve Identifies a range of potential circuits that trade offcost and timing.

Select Point Generates a circuit for one of the points of a trade-offcurve.

Map-Only Maps an RTL or structural design to a library withouttechnology-independent optimization.

PresynthesisReports

Generates timing and cost reports or purely structuraldesigns. You use reports to compare with optimizeddesign.


Types of Synthesis Runs

ToolRequirements Type of Run Application

Synthesizer-RTLdesignsOptimizer-Optimization

Normal Synthesizes and optimizes an RTL design,or optimizes and maps a structural design.

Optimizer Trade-Off Curve Identifies a range of potential circuits thattrade off cost and timing.

Optimizer Select Point Generates a circuit for one of the points of atrade-off curve.

Synthesizer-RTLdesigns

Map-Only Maps an RTL or structural design to alibrary without technology-independentoptimization.

Optimizer PresynthesisReports

Generates timing and cost reports or purelystructural designs. Use reports to compareoptimized designs.

Synthesizer Synthesis-Only Synthesizes and maps an RTL design to alibrary without optimization.


Lab Overview

Lab 7-1 Using Synergy Integration

Lab 7-2 Creating a Trade-Off Curve


Lab Overview

Lab 7-1 Use Synergy to synthesize a design.

Lab 7-2 Create a trade-off curve and synthesize one point from the curve.

Managing Design Data 8-1

Managing Design Data

Objectives

■ Understand version control.

■ Understand how to checkout and checkin design data.

■ Understand the different types of configurations.

■ Understand how to set up and use entry configurations.



Version A copy of an object at a particular time. As the design objectevolves, you can keep more than one version of the same object.

Entry configuration A grouping of specific cellviews and versions of design entrydata.

Run configuration A grouping of analysis run data and an entry configuration.

Design configuration A grouping of entry and run configurations.


Numbered Cellview Versions

1.0 1.9 2.0 3.0...

Each versioncorresponds to anactual design file.

Schematic LatestCreation

TimeCheck-In

Time

•••

Time

0.0

Versionsof

InverterSchematic


Numbered Cellview Versions

Versions are numbered to tell them apart. Usually the most recent, is the highest-numbered.To keep track of all the different cell versions, a two-level numbering scheme is used:

m.n

The primary index m is advanced by toggling the Advance Primary Index on the VersionCheckin form. Secondary index n is advanced automatically whenever a revised cell ischecked back in to its library. The secondary index is set to 0 whenever the primary index isadvanced.

The initial version number, given to a newly created cell, is 0.0. When the cell is subsequently,edited and checked in for the first time, its version number becomes 0.1 (or 1.0 if the primaryindex is advanced explicitly).

When you access a cell for editing, without explicitly specifying a version number, theframework uses the current checked-out version or the last checked-in version (if no versionis checked out).

Each numbered version corresponds to an actual design file. The design files are managedautomatically by Design Data Management System (DDMS).


Data Management of Cellviews

Virtual Memory(Design Window)

Versions Checked In

Read/edit

Save

Checkout

Version Being Edited

1.0

1.1

2.0

??

1.1

1.1

Checkin

MEMORY

DISK First Edit(implicit checkout)

1.1%

co@<user>

(checked out)


Data Management of Cellviews■ A checkin operation is like an archival operation. Checked-in versions are never

modified. Only a copy is edited.

■ Checkout is a process of creating a copy of a cellview for edit. A cellview can bechecked out by editing the cellview when there are only checked-in versions (implicitcheckout) or by explicitly checking out a cellview version. The checkout owner and theuser can control access to the checked-out copy.

■ You can edit only one version of a cellview at a time. The edited cellview must bechecked in as a new version or the edits cancelled and the checked out file deleted beforeyou can edit any other version of the same cellview.

■ A cellview version gets a definite version number only when it is checked in. This isgenerally done when a design milestone is met.

■ If a checked-in version is deleted, the version number is not used again.


Version Browser

0.0 1.0

1.1

2.0


Version Browser

The Version Browser shows the versions of each cellview and the relationship betweenversions.

In the example above, 1.1 and 2.0 are based on version 1.0.

Each version is stored independently from each other. You can delete an intermediate versionwithout affecting the others.


Lab Overview

Lab 8-1 Using Version Control

Lab 8-2 Copying a Cell


Lab Overview

Lab 8-1 Create multiple versions of a design.

Lab 8-2 Copy a cell between libraries using the library browser commands.


Configuration Management■ A configuration is a collection of design objects/data, grouped for a specific

task.

■ Configurations are saved in a library under a single name.

■ A configuration may reference other configurations.

■ You can create three types of configurations

— Entry configuration

— Run configuration

— Design configuration


Configuration Management

Configuration management is a means of logically grouping related design data. and savingthat data grouping under a single name. A configuration is a snapshot of your design at aparticular stage of development. Configurations are saved in the design library.Configurations allow you to retrieve specific design data at any time.

A configuration may reference other configurations in the same library, or in other libraries.The configuration that is referenced is referred to as a sub-configuration. There is nothingabout a configuration that makes it a sub-configuration beyond it being reference by anotherconfiguration.

There are three types of configurations: Entry, Run and Design.

Once you have created a configuration, you can open the library with the configuration. Thisrestricts access to only those library elements which are included in the configuration. Once aconfiguration is opened, it is used until the configuration is closed. This can be done manually,and is automatically done when you close the library.


Types of Configurations

Entry

Configuration

Entry

Configuration

Design

Configuration

Simulation Run

Configuration

Synthesis Run

Configuration


Types of Configurations

Entry Configuration

Entry configurations specify which cellviews and versions are used in your design at aparticular time. Entry configurations are a snapshot of design entry data, which can be acombination of schematics and HDL descriptions. Entry configurations allow you to specifyspecific levels of abstraction for the various cells in your design, effectively masking out otherdesign data. An entry configuration may reference other configurations either in the samelibrary or other libraries (sub-configurations).

Run Configuration

Run configurations save analysis run directory information in a library. You can associate runconfigurations with a particular entry configuration (sub-configuration). This allows you toautomatically maintain consistency between the design and the analysis data.

Design Configuration

Design configurations are created in order to export design data to a new library. Designconfigurations allow the entire design to be grouped to track development progress and torelease the completed design. You can group configurations into a single design configuration.When exported, the cellviews and analysis data in the design configuration are copied into anew library. In order for data to be combined from several libraries, design configurations canbe exported to the same library.


Entry Configuration

■ Allows individual cellviews and versions to be selected.

■ A library can be opened with a configuration.

Restricts access to only elements included in the configuration.

■ Expansion by view list or by specified cells.

Entry

Configuration

Cell A, functional& symbol views

Cell B, behavioral& symbol views

Cell C, schematic& symbol views


Entry Configuration

An entry configuration contains different levels of abstraction (cellviews) for each cell. Anentry configuration allows you to select the cellviews and versions used during analysis ofyour design. The cellviews can be mixed and matched, overriding the view list generally usedfor netlist creation. Generally, the symbol and one other cellview per cell is included.

You can add cellviews to an existing configuration.

You might have several levels of abstraction expressed with Verilog HDL text and graphicalschematics which you wish to combine for an analysis run. The entry configuration, in theabove example, includes: A functional, B behavioral and C schematic cellviews.

The entry configuration may be created in a number of ways. Manual addition and deletion ofcellviews and versions, hierarchy expansion using a view list and a combination of a view listand selective expansion of the hierarchy.


View List Hierarchy Expansion■ View list indicates views to be expanded into.

■ View list is order specific.

■ Example View List

behavioral functional schematic symbol

■ Expansion includes

— top-level schematic

— symbol for each instance in the top level and subsequent levels ofhierarchy

— First view, as specified in view list, for each cell in top level andsubsequent levels of hierarchy


View List Hierarchy Expansion

If the expansion is by view list, then the configuration is created that includes

the current schematicsymbols for all instances contained in the top levelthe first view, as specified in the view list, for each cell in the top level and subsequentlevels of hierarchy.

Hierarchical expansion is performed for each hierarchical cellview found. Hierarchyexpansion by view list is similar to the hierarchy traversal used during netlist generation.

With the example view list of behavioral, functional, schematic, symbol, for each instance inthe top level,

if a behavioral cellview exists, it is included.if behavioral does not exist, and functional does, it is included.if functional does not exist, and schematic does, it is included.if schematic does not exist, then the symbol is included.

Each hierarchical design is expanded as the top level is. Expansion stops when no additionalhierarchy exists.


Selective Hierarchy Expansion

■ You override the search sequence for specific cells.

■ Selective expansion allows a choice of views for each indicated cells.

■ Symbol cellview is automatically included for each cell.

■ Cells for override can be chosen directly (Secondary Cells).

■ All cells contained in a cell can be chosen (Primary Cells).

■ Limitation - the cellview for each primary cell is chosen by the view list.


Selective Hierarchy Expansion

You override the view list hierarchy expansion by using selective expansion. Selectiveexpansion allows you to choose which view to use for each specified cell. Cells are specifieddirectly by including the individual cell in the Secondary Cell list. All cells contained in ahigher level cell are selected when the higher level cell is included in the Primary Cell list.

One limitation of selective hierarchy expansion is that the cellview for each primary cell ischosen by the view list and does not use selective expansion. Additions and deletions can bemade to configurations after they have been created.


Entry Configuration Selection

C

fun beh beh

F

sch sch

behsch beh

H

beh fun sch

schfunbeh beh

B D

E G

J Z

Xkey

= Select view for cell

A

sch

view list = behavioral schematic symbol

Primary cells = A B

Secondary cells = J


Entry Configuration Selection

Primary and Secondary cells are used to specify expansion.

In the example above, the primary cells are A and B. The view for each cell contained in cellsA and B will be selected individually, overriding the view list. Under A, you select which viewfor C and D are included in the configuration. Under B, you select which view of E and F areincluded in the configuration.

J is a secondary block. The view for J is selected rather than using the view list.

All remaining blocks (G, H and Z) were not selected, so the view list will be used to expandtheir hierarchy.


Version Binding in Configurations■ Specific version number (static)

■ Most recent by time (dynamic)

■ Most recent by major version number (dynamic)

■ For example:

■ Initial version binding is based on checkin/checkout status.

■ You can modify version binding.

0.0 0.1 1.01.1

2.0

Most Recent by Major Version Number

Most Recent by Time


Version Binding in Configurations

Cellviews may include a specific version of a cellview, or use the most recent version.

The most recent version may be determined by time, or by major version number. If version1.1 is created after 2.0, then 1.1 would be the most recent by time, and 2.0 is the most recentby major version number.

Static binding refers to the use of specific version in a configuration. Dynamic binding refersto the use of the most recent version in a configuration. Dynamic binding includes most recentby time and most recent by major version number.

The initial version binding is determined based on the checkin/checkout status of eachcellview in the configuration. You can modify the version binding after the configuration hasbeen created.


Static and Dynamic Binding

Yes

Fixed Version

of Cellview

Accessed

Create Configuration

NoCellview

Checked

In

?

(Static Binding)

Most “Recent”

Version

Accessed

(Dynamic Binding)


Static and Dynamic Binding

If a cellview is checked in when you create a configuration, static binding is used for thatcellview.

If you have a cellview checked out when you create a configuration, the most recently savedversion of that cellview is accessed.This is most recent by time dynamic binding. As thatcellview is modified, the configuration automatically uses the newer versions.


Configuration Browser

dataCounter.entry

eventCounter,schematic

Counter,symbol,0.1

FA,symbol,1.1

Register,symbol,0.1

Counter,schematic

adder4bit,schematic,0.1

Register,schematic,1.1

adder4bit,symbol,0.2


Configurations and the Library Browser

Configuration Browser

The configuration browser is similar to the library browser. The configuration browserdisplays the contents of a particular configuration and includes commands related to managingconfigurations.

Versions for cellviews using static binding can be displayed in the configuration browser. Thisgives a quick visual indication of cellviews using static and dynamic binding.

Using a Configuration Open Library

When you open a library with a specific configuration, you can read or edit only the cellviewsincluded in that configuration. The Library Browser allows you to expand the all cellviews inthe library, but those cellviews that are not included in the current configuration can beaccessed. You must close the configuration (or the library) to access cellviews not included inthe configuration.


Lab Overview

Lab 8-3 Creating Entry Configurations


Lab Overview

Lab 8-3 Create use entry configurations to control design use.

Using the Veritime Interface 9-1

Using the Veritime Interface

Objectives

■ Introduction to timing analysis

■ Veritime interface

— Perform path analysis.

— Perform hybrid analysis.



Verilog Language Hardware Description Language for both behavioral andstructural modelling.

Veritime Cadence timing analyzer.

Veritime Interface The interface used to run Veritime from the Design Framework IIenvironment.


Introduction to Timing Analysis■ Process of verifying that the internal timing constraints

(setup time, hold time, minimum pulse width etc.)are satisfied over the full range of min and max delays.

■ Commonly divided in to two categories:

Dynamic Timing Analysis

■ Simulation-based

■ Simulation propagatesa full range of min tomax times for eachtransition.

Static Timing Analysis

■ No logic simulation

■ All possible paths aretraced. May displaypessimistic results.

FF2

clk

d1 d2FF1


Introduction to Timing Analysis

The timing analysis objectives are 1) to ensure that in the intended operation of the circuit, allof the internal timing constraints (setup time, hold time, pulse width, etc.) will be met 2) ensurethat the timing constraints are met over the circuit’s full range of minimum to maximumdelays.

In the case of dynamic timing analysis, the simulation propagates a full range of min to maxtimes for each transition. The events are scheduled in the event list and are evaluated one byone. Hence a dynamic timing verifier can be considered as a enhanced algorithm of a logicsimulator. User must have a complete knowledge of critical paths required for full analysis.

In the case of static timing analysis, simulation is not important. The critical paths areidentified by tracing the connections in the design and adding up the worst case delays. Thestatic timing verifier works on the entire circuit and hence may display pessimistic results.

The Veritime software offers variety of capabilities to meet the needs of the timing analysis.It uses the same models used by the Verilog-XL software. The Veritime software performstwo general types of timing analysis: path analysis and hybrid analysis.


Overview of Veritime

Veritime Timing Analysis Methods

■ Path analysis

Static timing verification

■ Hybrid analysis

Simulation-assisted static path analysis


Overview of Veritime

Veritime uses a technique that falls in between the realms of pure static analysis and dynamicanalysis to accomplish the goals of static timing analysis. Veritime users construct a simpletemplate comprised of the system tasks that completely verify the timing of their designs.Veritime uses some simulation results in conjunction with path analysis to run the timinganalysis. The algorithm it uses to do this is termed Hybrid Analysis.

With hybrid analysis, Veritime takes into consideration the arrival time of each path trace.This is done in parallel with a simulation of the design. The simulation tells Veritime preciselywhen each path is used. This information is used to establish the relative timing between pathsand to verify timing checks in the component models. The simulation also provides values thatcan be used to eliminate false paths.

During path analysis, Veritime performs purely static timing verification. Veritime findscritical paths that run between a specified set of begin points and a specified set of end points.


Performing Path Analysis

As a path calculation tool, the Veritime software provides two basic forms offunctionality.

■ It displays the longest and shortest paths between any given set of beginand end points.

■ It produces a histogram that shows the distribution of path delays for allpossible paths between those begin and end points.


Performing Path Analysis

The path calculation features of the Veritime software provide the commands to find thecritical paths through a circuit, where critical paths are the longest or shortest paths throughthe circuit. These critical paths are the logic paths that could possibly degrade the performanceof the circuit by requiring a slower clock frequency, or by causing signals to arrive out of phasewith the rest of the data.


Performing Path Analysis (continued)

To perform path analysis, we can:

■ Define a region of interest with a set of begin points and end points.To select begin and end points from your design, select Begin/End At fromthe Path Analysis menu

or click on the Begin/End Points icon.

■ Calculate the longest paths in your design.To select Longest Path from the Path Analysis menu.

or click on the Longest Path icon.

Note:If you have not selected begin/end points, the Longest Path icon selects points for you. Forbegin points, the default is all inputs to the design and all storage device outputs. For endpoints, the default is all design outputs and all storage device inputs.

Begin/End At...Path Analysis ➾

Longest Path...Path Analysis ➾


Performing Path Analysis (continued)

Begin/End At Sets your begin and end points for the path calculation.

Stimulus Sets logic value on inputs during analysis.

Inhibit Inhibits nodes or paths during path tracing.

Longest Path Instructs Veritime to calculate the longest path between the beginand end points of your design.

Shortest Path Calculates the shortest path between the begin and end point of yourdesign.

Show Paths Lists the paths found by the path calculation commands duringanalysis.

Path Distribution Produces a histogram of all path lengths between begin and endpoints.

Display Paths Displays the paths found by the path calculation commands.Veritimewill create flight lines with Rise and Fall times in the schematic.

Write Constraints Creates a Standard Delay File (SDF) for forward annotation. Thelayout tool uses this information while routing critical nets.


Performing Hybrid Analysis

Hybrid Analysis

■ Simulation-assisted static path analysis.Complete but not pessimistic static analysis. Eliminates false paths.

■ Determines min/max arrival times of each path trace.

■ Evaluates storage device timing checks based upon the arrival times ofeach path trace.


Performing Hybrid Analysis

For many designs, the most effective means of verifying proper timing is to use Veritime’shybrid mode of analysis. In this approach, timing analysis is performed in parallel with asimulation of the design. Logic simulation is used to determine the state of control logic andto simulate various forms of clock signals—functions that pure static analysis methods finddifficult to handle.

To better understand the concept of hybrid analysis, think of it as an automated form of pathcalculation mode to define the regions where critical path tracing should be performed.Instead, Veritime picks the begin and end points automatically, based on the informationcontained in your model.

To verify the timing checks in a design, Veritime uses critical path tracing to determine themin/max timing at each storage device input. The timing checks provide the informationVeritime needs in order to choose the end point for each critical path trace. As for the beginpoints, some are chosen automatically by Veritime, while others must be defined by the user.These begin points are also called trigger points, since they are the points in the circuit wherepath tracing is automatically triggered.

For Veritime, it is not enough to know where each path trace should begin; it is equallyimportant to know when each path trace should be triggered. The ‘when’ part of this equationis the part that logic simulation contributes to hybrid analysis. That is, in hybrid analysis,simulation can be used to give different begin times to different critical path traces. Veritimeuses the absolute begin times that simulation provides to establish the relative timing betweenpath traces to the same timing check.


Performing Hybrid Analysis (continued)

To perform hybrid analysis:

■ Define primary inputs to specify which part of your circuit should besubjected to the full min/max analysis used by the Veritime software.

To select primary inputs for a hybrid analysis, select Primary Inputs fromthe Hybrid Analysis menu.

Primary Inputs...Hybrid Analysis ➾



Primary Inputs Specifies the primary inputs for the hybrid analysis.

Timing Checks Enables or disables timing checks in your design. Can also showwhich checks are enabled and disabled.

Tolerance Sets or shows the current tolerance for specified type of timingchecks in your design.

Inhibit Inhibits the selected nodes or paths in your design.

Stimulus Sets constant logic values, creates periodic clock waveforms andstable/changing waveforms as stimulus during analysis.

Run Analysis Sets the duration of the analysis in time units, cycles or until aspecific event occurs.

Monitor Selects nodes for monitoring during hybrid path tracing.

Summary Displays statistics about hybrid analysis in either a table or textformat.

Violation Display Lists violations detected during the hybrid analysis.

Slack Time Reports slack times associated with individual timing checks thatwere evaluated during analysis.



■ Defining end points and path segments.

Veritime automatically selects path tracing end points based on the locationof storage devices and timing checks in the design.

■ In hybrid analysis, the Veritime software automatically selects path tracingend points based on the location of storage devices and timing checks in thedesign. For this purpose, the Veritime software recognizes a storage deviceas any of the following objects:

— any sequential user defined primitive (UDP)

— any module that contains an edge-sensitive module path

— any circuit region declared as a storage device



The clock and data inputs to each storage device are automatically chosen as end points. TheVeritime software also establishes end points at all inputs governed by timing checks.Whenever a hybrid path trace is triggered, the simulation is temporarily suspended to allowthe path trace to proceed.

Each path trace begins at a primary input and fans out to various destinations throughout thecircuit. Any path that does not lead to a timing check, a storage device clock or data input, ora monitor point is trimmed and excluded from the analysis. Veritime will stop each branch ofa path trace when it reaches a clock or data input to a storage device. When there are no morepath traces pending, the simulation is allowed to resume.

Then, when the simulation reaches the point in time when a change would propagate throughthe storage device, a new begin point is established at its output and a new path trace istriggered to the next storage device, timing check or monitor point.

Thus, a path from a primary input to a particular storage device may actually pass throughseveral intermediate storage devices before reaching its intended destination.

In effect, the entire path is composed of several smaller combinational path segments—whereeach segment runs from the output of one storage device to the input of the next and eachsegment is derived from a separate path trace.

Path segments play an important role in understanding how the Veritime software reportstiming violations.


Veritime Encapsulation WindowThe key to the Veritime Interface is the Veritime Integration Control window, orsimply the Veritime window, as shown in this figure.

Run Directory

Design Library-Cell-Cellview

Menu Banner

Output Window

Icons

Status LineCommand Input Line


Veritime Encapsulation Window

The Veritime Interface lets you use the Veritime timing analyzer in the Cadence designenvironment, while maintaining the same high performance of the stand-alone Veritimeanalyzer. It has the following features:

Menu Banner: Provides options that support your Veritime session, such as file management,netlisting, test fixture creation, and session configuration. The menu banner expands toprovide analysis options when you enter an interactive Veritime session.

Icons: Provide quick access to common interactive timing analysis tasks. Icons may be activeor inactive depending on the state of your analysis. For example, only the View Waveforms,Start Interactive, and Read Delays icons are active until you start an interactive session.

When you place the mouse cursor over an active icon, the icon name appears under the icon.

The Output Window: Displays equivalent Veritime commands each time you select a menuitem. The Output Window is also the area in which Veritime displays the textual results ofyour analysis, including histograms, tables, and report summaries.

A Status Line: Provides status information, such as an input prompt when Veritime is waitingfor you to perform some action, or an error message when a command has executedimproperly.

The Command Input Line: Provides an alternative to the menu banner for Veritime input.The Command Input Line is a small area at the bottom of the Veritime window that allows youto enter manually Veritime commands or scripts that you want to execute.


Veritime Data Flow

Verilog Netlist Verilog Libraries Stimulus File

Veritime

Reports

(optional)

Analyze

Netlist

Create stimulus

(optional)

Start Veritime


Veritime Data Flow

There are three input sources to the Veritime software

1. Verilog netlist

2. Verilog Libraries (containing timing models)

3. Stimulus File (verilog vector file)

Verilog Libraries must have built-in timing checks to run Veritime.

Stimulus Files are the test vectors written in the Verilog language to test the circuit.

Veritime generates the report of the timing violations in a log file.


Delay Annotation

You can read in an SDF delay file.

Verilog-XLVeritime

SDFDelays


Delay Annotation

In the Composer Verilog and Veritime environments, you can annotate a delay file beforeyou start your analysis (or interactively during a session). The Composer software recognizesannotation files written in SDF (Standard Delay Format).

You must turn on the option for creating a pin map in the Netlisting Options form before younetlist your design. The pin map ensures that pin names in the delay file can be mapped to thepin names in the netlist.


Lab Overview

Lab 9-1 Using the Veritime Integration


Lab Overview

Lab 9-1 Use Veritime integration for long path analysis.

Running Circuit Simulation 10-1

Running Circuit Simulation

Objectives

■ Understand how to set up and run circuit simulation.

■ Understand how to set component parameters for simulation.

■ Understand the basics of the Simulation and Test Language.



Simulation and TestLanguage (STL)

Language used to generate simulation vectors and automatic testequipment stimulus

CDF Component Description Format


Simulation Flow

NetlistCreate Input

Stimulus

View Waveforms

Simulate

CompletedSchematic

Add Probes

and Text Outputs


Simulation Flow

You perform the following steps to run simulation on a completed design.

1. Create the input stimulus using the simulator native language or the Simulation and TestLanguage.

2. Netlist the design to create the textual description of the design in the simulator’ssyntax.

3. Run the simulation.

Simulations can be run either in the background or not. If you run a simulation in thebackground, then you can perform other activities or log off while the simulation isrunning. When you run in the foreground, then you must stay in the DesignFramework II environment, and you cannot use the system for other activities while thesimulation is running. Background simulation is useful for large analysis. Foregroundsimulation is most useful for small simulation analysis.

4. View textual and waveform output data.


Parameterizing Schematic Components

■ Two methods for parameterizing schematic elements

— Cellview and instance properties

— CDF properties

■ Cellview and component properties may be added at any time. Advantageis that less preparation is required.

■ CDF properties require more in depth setup. Advantages are that CDFproperties prompt you for values/settings, display default values, and maylimit user to specific choices for values.

■ Properties are name-value pairs.

■ Property names are simulator specific.

■ Simulation interface documentation contains details about the propertiesused for each simulation.

■ Typical examples of simulation properties for transistors include width (w)and length (l).


Parameterizing Schematic Components

There are two methods for parameterizing schematic elements. The first is by adding cellviewand instance properties. The second is by adding CDF properties.

Cellview and component properties may be added at any time. They do not require preparationprior to use. One disadvantage is that as you are adding the properties, you must know thenames and data type required for the netlister. Another disadvantage is that users may setvalues that are not allowed for certain components.

CDF properties require setup prior to use. The advantages are that CDF properties then promptyou for values/settings, it is easy to see default values, possible to limit user choices on values.

All properties are name-value pairs.

Property names are simulator specific. Simulation interface documentation contains detailsabout the properties used for each simulator and the type of data that the simulator is lookingfor.

Typical examples of simulation properties for transistors include width (w) and length (l) forcircuit simulation. Logic simulators typically look for rise time (tr) and fall time (tf).


The Component Description Format (CDF)

2Schematic EditorWindow Edit Schematic

Label1Label2Label3

Add Component

Textual CDFSkillSkillSkill

Simulation Environment

Schematic Editor

CDF


The Component Description Format (CDF)

CDFs are attached to components and libraries in the Design Framework II environment. Thedesign entry and simulation environment can reference CDF to gain information about designcomponents by:

■ Prompting for parameterization information on components as you add them to theschematic.

■ Displaying and using default values for a cell.

■ The Add Component command reads the CDF to display a component’s parameters onthe Add Component form. The CDF determines default value, type and units. CDF canbe used to limit available choices for component parameters. Typical componentparameters include device parameterization for circuit simulation and delay informationfor logic simulation.


Types of CDF

Library

Resistor A

Resistor B

Resistor C

Library

NPN device

Capacitor C

Capacitor A

CDF

CDF CDF

CDF

CDF Attached to a Library CDF Attached to Components in a Library

+ =

Library Cell Effective Cell


Types of CDF

When you attach a description to a library, all components in the library inherit the description.When you attach a description to a component, you attach the description to the component’scell. Library level CDF data is shared by all cells in the library. Cell level CDF data creates oroverwrites library level data.

Library CDF is the lowest level. Cell CDF overlaps the Library CDF to produce the EffectiveCell CDF as illustrated. Note that Cell CDF overrides Library CDF adding additionalquantities and redefining Library CDF quantities. Effective Cell CDF is the CDF used by thesystem. You view Effective CDFs to see the combined Library and Cell CDFs.


Property Inheritance

■ Properties can pass through the hierarchy.

■ A higher level property can set a lower-level property value.

— For example,

w=[@pw:%:10u]

(type=NLPExpr)

— The value of w is set by the value of property pw higher in the hierarchy.

— If pw is not defined in the hierarchy, then the value 10u is used.

— The property type NLPExpr directs the system to use a propertysubstitution.


Property Inheritance

You can assign property values at various levels of your design hierarchy. Lower levels in thehierarchy can inherit these values.

An example is setting the pmos transistor width to a default value, but allowing individualgates to override the default. The pmos transistor must include the property w=[@pw:%:10u],and the property type NLPExpr. The @pw indicates that the value of a property pw, higher inthe hierarchy, is used for the value of w. If pw is not defined, then the value of w is set to thedefault of 10u.


Simulation and Test Language

■ Generates stimulus for simulation.

Support logic and circuit simulators.

■ Generates test patterns for Automatic Test Equipment.

■ Require knowledge of only a few commands to use.

■ Uses a high-level language, IL, for advanced users.

■ Uses a single STL file for multiple simulators and testers.

■ Lets you verify simulation results against predicted output values.


Simulation and Test Language

The Simulation and Test Language (STL) generates stimulus for logic and circuit simulation,test patterns for Automatic Test Equipment (ATE), and verifies simulation results againstpredicted values. You can use a single STL file to generate vectors for multiple simulators andtesters.

STL is easy to use as only a few commands are required. STL is based on the IL language. ILprovides the high-level programming constructs that let you create complex STL files.


Compiling an STL File

Compile an STL input file for each target simulator and tester.

■ Compiled output is in the simulators syntax.

■ You can compile the STL file when you create it or at simulation time.


Compiling an STL File

Compile the STL input file for each target simulator and tester. The compilation process takesthe STL file and interprets it for the target program. The output from this compilation is a setof files in the target simulator (or tester) language.

Usually, STL files are compiled when they are created to allow you to verify that the file doesnot contain syntax errors. Once the file has been compiled, it does not need to be recompiledfor that simulator unless the file changes. If the file has not been compiled or has changed sincelast compiled, it will be compiled automatically when simulation begins.


Sample STL File

stlinit

defpin A in tr=1e-09 tf=1e-09

defpin B in tr=1e-09 tf=1e-09

defpin C in tr=1e-09 tf=1e-09

deftiming 1ns 10ns 80ns

deftest

xv(0 0 0)

xv(0 1 0)

xv(1 1 0)

xv(1 1 1)

endtest


Sample STL File

Command Description

stlinit Indicates the start of an STL file. This command beginseach STL program

defpin A in tr=1e-09 tf=1e-09 Defines A as an input pin with 1ns rise and fall time fortransient analysis input signal definitions. In general, defpindefines input and output signal names and characteristics.Each input pin must be included. Output pins must beincluded if expected output values will be included.

deftiming 1ns 10ns 100ns Defines timing for simulation and test.

deftest Defines the start of a functional test program.

xv (0 1 0) Sets the inputs as follows A=0, B=1 and C=0. In general,xv defines a single test vector (execute vector). Each vectorcorresponds to one test period. Default order of values mustmatch the order of the defpin commands.

endtest Defines the end of a functional test program. Always thelast line of the STL file


STL Timing Descriptions

Timing in STL is defined by the deftiming command

■ Three components to the deftiming command

— resolution

— time unit

— test period

■ Example usage of deftiming command

deftiming 1ns 10ns 80ns

■ Each xv command specifies the functional data for one test period


STL Timing Descriptions

The STL timing definition includes resolution, time unit, and test period.

Resolution sets the time scale value or step size for simulation.

Time unit defines strobes and clocks. The time unit must be a multiple of the resolution value.

Test period is the length of time for each test. Inputs are applied and outputs are measuredduring each test period. The test period must be a multiple of the time unit.

In the example above, the resolution is 1 ns, basic time unit is 10 ns and the test period is 80ns. For a circuit simulation, the simulator will step in 1 ns time units, strobes and clocks canbe defined to happen in 10 ns resolution in each test period, and each set of vectors is used for80 ns of the simulation time.


Lab Overview

Lab 10-1 Adding Parameters for Simulation

Lab 10-2 Running a Circuit Simulation Using Spice


Lab Overview

Lab 10-1 Add parameters for Spice simulation with and without CDFs.

Lab 10-2 Run and view the results of a circuit simulation using Spice 2G.6.

Comparing Layouts and Schematics 11-1

Comparing Layouts and Schematics

Objectives

■ Understand how to compare a layout and schematic.



extracted cellview Layout based cellview which contains connectivity informationsimilar to schematic connectivity

LVS Layout Versus Schematic – compares a physical layout design tothe schematic from which it was designed.


Layout Versus Schematic Data Flow

deviceextract

LPE/PRE

LVS

Extractorlayout

schematic

extracted


Layout Versus Schematic Data Flow

Layout Versus Schematic (LVS) comparison and postlayout simulation.

You must extract connectivity and devices from the original layout for LVS. Extraction is notan end in itself, but a means to an end. The extractor creates an extracted cellview for yourdesign. It visually looks similar to the layout, but it includes connectivity information similarto a schematic.

Schematic data is used with the extracted cellview for LVS.


Extractor

deviceextract

LPE/PRE

layout extracted

drcExtractRules Procedure


Extractor

You use the extractor to generate the extracted cellview of your design. This cellview includesdevice and connectivity information based on the layout data. The extracted cellview is usedfor LVS.

The inputs to the extractor are the layout and extraction rules in the technology file.

The output from the extractor is an extracted cellview including designed and parasitic devicesand connectivity.

You can create backannotation of layout netlists with parasitic components for simulationanalysis.


Layout Versus Schematic

NetlistCreation

lvsRulesProcedure

Probing/Explain

NetlistCreation

LVS

extracted

NetlistComparison

Error Data

schematic


Layout Versus Schematic

Layout Versus Schematic checks the consistency of connectivity and devices between theextracted cellview of a layout and the schematic it was designed from. Any combination ofcellviews, extracted or schematic, can be checked.

The lvsRules from the technology file are used during the comparison.

View the summary reports to analyze errors, or by cross probe the errors between the extractedand schematic cellviews.


Lab Overview

Lab 11-1 Comparing a Schematic with an Extracted Layout


Lab Overview

Lab 11-1 Run an LVS and analyze the results with and without errors.

User Customization 12-1

User Customization

Objectives

■ Learn how customize your Design Framework II environment



context A context is a binary representation of the internal SKILLstructures that define a collection of SKILL procedures. EachSKILL application is associated with one or more context.

autoload To autoload a function refers to loading the definition of thefunction automatically upon demand, that is, when the function isfirst invoked.

callback SKILL code that is called when some event in the user interfacehappens.

bindkey A relationship between an application type and keyboard ormouse event and a SKILL expression. Used to reduce typing.


Defining Bindkeys

■ Example of bindkey definitions

hiSetBindKey(“Schematics” “<Btn1Down>(2) EF”“mouseFinishPt()”)

hiSetBindKey(“Schematics” “<Btn1Down>(2)”“mouseAddSelectPt()”)

■ Example to find if a key is bound to a function in an application

hiGetBindKey(“Schematics” “<Btn1Down>(2)”)

■ The same key can be bound to two SKILL functions—Command functionand Enter function.

■ Enter function bindkeys are enabled when you are in data entry mode suchas creating a wire or path.

■ Use Utilities ➝ Bind Keys to view the list of bindkeys for variousapplications.


Defining Bindkeys

The syntax to create bindkeys ishiSetBindKey("application_type" "key" "skill_funtion")

Typical applications are "Command Interpreter", "Layout", and"Schematics".

The key argument consists of"modifier_list<key or button operator>(occurrences)"

An enterfunction bindkey is indicated by the key argument ending with “EF”.

You can type the following SKILL function to find the bindkeys defined for your currentwindow.

hiShowBindKeys(hiGetCurrentWindow())

Caution

Any key or button bindings defined in the X environment override any Design Framework II definitions.

Event Description Meaning

"<Btn1Down>" click the left mouse button

"<Key>a" press the a key

"Shift Ctrl<Btn2Down>(2)" hold down shift and control keys anddouble click the middle mouse button


Design Framework II Initialization Sequence

■ Autoload files are loaded.

■ Startup context files are loaded.

■ The Environment files are loaded in the following order

— <install_dir>/tools/dfII/local/etc/tools/<application>/.cdsenv

— <install_dir>/tools/dfII/local/.cdsenv

— $HOME/.cdsenv

All environment files are loaded if they are present.

■ The user customization file .cdsinit is loaded.

The search order for the .cdsinit file is:

— <install_dir>/tools/dfII/local

— the current directory "."

— the home directory

Once a .cdsinit file is found, the search stops.

■ Previously saved session and log files are loaded if specified in thecommand line.


Design Framework II Initialization Sequence

Contexts

Most applications are partitioned into one or more contexts that are loaded upon demand. Thisloading mechanism is called the autoload mechanism. A context is binary file that stores theinternal representations of a collection of SKILL functions and associated data structures. Thesystem loads the <install_dir>/tools/dfII/etc/context/*.al files. These files correlate theSKILL function names with the contexts that contain them.

Environment Files

The .cdsenv environment files are used to initialize the Design Framework II and some DesignFramework II tools. The Utilities ➝ Save Environment command will create and save thisfile and should be used following the setup of the environment.

Session File

You can save the window locations in a session to a session file using theUtilities ➝ Save Session command. The session can be restored when you start the softwareby using:

icds -restore cdsSession.save &

You can also execute a SKILL file or replay a log file when you start the software.icds -restore cdsSession.save -replay $HOME/CDS.log.old &


The .cdsinit File■ The site administrator has three ways of controlling the user

customization.

■ Consult the <install_dir>/tools/dfII/cdsuser/.cdsinit file for example usercustomization.

Policy Customization Strategy

All customization done bythe site administrator.

The <install_dir>/tools/dfII/local/.cdsinitcontains all customization commands.There are no ./.cdsinit or ~/.cdsinit filesinvolved.

Some site customizationdone by the administratorand then the userscustomize further

The <install_dir>/tools/dfII/local/.cdsinit filecontains a command to load the ./.cdsinitor ~/.cdsinit files

All the customization doneby the user

The <install_dir>/tools/dfII/local/.cdsinit filedoes not exist.All customization handled by either the./.cdsinit or ~/.cdsinit files.


The .cdsinit File

If you have a site .cdsinit, you can put the following SKILL commands in it to load the .cdsinitin your working or login directory.

if( isFile("./.cdsinit") then

loadi("./.cdsinit")

else

if( isFile("~/.cdsinit") then

loadi("~/.cdsinit") )

)


Customizing Strategy■ Create site customization file

— Sample files provided by Cadence

For a new user <install_dir>/tools/dfII/cdsuser

For site customization <install_dir>/tools/dfII/samples/localcdsinitconfiguration filesbind key definition files

— Copy <install_dir>/tools/dfII/samples/local/cdsinit to<install_dir>/tools/dfII/local/.cdsinit and modify for site customization.

— Functions performed by site customization

Load bindkey definitions and customized configuration.

Start on-line help in the background.

Invoke user customization file.

■ Create user customization file

— Copy <install_dir>/tools/dfII/cdsuser/.cdsinit to login or working directory

— Add to .cdsinit

■ Save session and environment from a Design Framework II session.


Customizing StrategySite customization - <install_dir>/tools/dfII/local

Sample files are in the <install_dir>/tools/dfII/samples/local directory.

The configuration files settings are the same as the default configurations and need not beloaded. If you want to change the default configuration, you should copy the configurationfiles into <install_dir>/tools/dfII/local, modify them and load them from the site .cdsinit file.

If the configuration changes are small, you can cut and paste the necessary sections from theconfiguration files directly into the .cdsinit file.

User Customization

Sample files are in <install_dir>/tools/dfII/cdsuser. This directory also contains dot files forUNIX and X customization. You can copy the .cdsinit file to your login or working directoryand customize it. If you have a site customization file, the user customization file should beloaded by the site customization file.

You can also save your environment variables using Utilities➝ Save Environment andUtilities ➝ Save Session and automatically read the saved file when you start the DesignFramework II environment again.

Example:cds3 -restore cdsSession.save &

The environment file is saved in .cdsenv in your login directory and is loaded automatically.


Defining Basic Tasks in the .cdsinit File

■ Set the library search path.

dmSetLibraryPath("/mnt/designs /mnt/reflibs")

■ Set the SKILL search path.

setSkillPath(strcat(". /mnt/techfile/masters

/mnt/programs/skill "prependInstallPath("samples/local ")

))

■ Load software supplied bindkey definitions.

loadi("schBindKeys.il")

■ Defining your text editor within the Design Framework II environment.

editor = "xterm -geometry 80x40 -e vi"editor = "xedit"editor = "xterm -e emacs"


Defining Basic Tasks in .cdsinit File

■ Set the library search path.

■ If you start building many SKILL source files, you might want to keep them in a centrallocation and allow all users to read them. You can set the SKILL search path to locateSKILL source files.

Load standard schematics bindkey definitions located in the<install_dir>/tools/dfII/samples/local/schBindKeys.il directory.

dmSetLibPath(strcat("~/ICcae "

prependInstallPath( "samples/cdslib" ))

)

if( isFile( "schBindKeys.il" ) load( "schBindKeys.il" ))


Specifying Optional Tasks in the .cdsinit File

■ Load utilities written in SKILL.

load("myAlgorithm.il")loadi("newMenus.il")

■ Define new bindkeys.

hiSetBindKey("Layout" "<Key>F8" "dmbOpenLibBrowser()")


Specifying Optional Tasks in .cdsinit File■ Setting user preferences

You can set user preferences by defining values for the fields of the form hiSysProps.You can also set the preferences using Utilities ➝ User Preferences from the CIW andsave the values into the environment file $HOME/.cdsenv using Utilities ➝ SaveEnvironment.

■ Loading SKILL files

You can define variables or procedures in SKILL files and load these SKILL fileswhen you start the software. The load command loads a file but stops loading the fileif it encounters an error. The loadi command continues loading the rest of the file evenif there is an error in a line.


Lab Overview

Lab 12-1 Defining Bindkeys

Lab 12-2 Adding Bindkeys to the .cdsinit

Lab 12-3 Saving the Environment


Lab Overview

Lab 12-1 Learn how to define bindkeys for the CIW and application windows. Bindkeysincrease productivity by reducing key strokes.

Lab 12-2 Learn how to add information to customize your Design Framework II environmentby modifying the .cdsinit file.

Lab 12-3 Set and save some environment settings for use in future Design Framework IIsessions.


Module Summary

In this module, you learned

■ How to find SKILL functions associated with menu choices and key clicks inthe Design Framework II environment.

■ The SKILL functions to add to the .cdsinit file to automate tasks you need toperform when you start the Design Framework II environment.


Module Summary

Edge Database Translation 13-1

Edge Database Translation

Objectives

■ Understand the database conversion flow.

■ Understand how to translate an Edge database.



Edge Old version of the Design Framework environment.


Translation Programs

Program Description

translate Edge database to Design Framework II database

tcTranslate Edge technology to the Design Framework II environment

pdvtodiva Conversion of PDV design rules and abstract extractionrules

ruletrans Cell ensemble rule.tech and contact.tech translation

skilltrans Edge SKILL to Design Framework II SKILL procedures


Translation Programs

A number of translation programs are available for users making the transition from Edge toDesign Framework II (DFII). Each of these programs performs translation of design data,technology information or SKILL translation. The translation programs include the following:

The technology file data is most important for physical design database translation. Thedefault technology file can be used for design entry data translation.

Program Purpose

translate Edge database to Design Framework II database translation. Thisis the most important translation program from a design entryperspective.

tcTranslate Edge technology to Design Framework II library technology filetranslation

pdvtodiva Conversion of PDV design rules and abstract extraction rules

ruletrans Cell Ensemble rule.tech and contact.tech translation

skilltrans Edge SKILL to Design Framework II SKILL translation


Conversion Flow

Design Framework IILibrary

translateEdgeBlocks

Edge

FileLayers

Design

TechnologyFile

Framework II


Conversion Flow

Translating from the Edge database to the Design Framework II database takes Edge libraries,Edge layers files and a Design Framework II technology file and creates Design Framework IIlibraries. This translation is performed UNIX environment by the translate program.

A Design Framework II library is created for each Edge library encountered during thetranslation. If a Design Framework II library exists in a search path directory, then thatdirectory is not translated instead, the Design Framework II library is used as a referencelibrary during the translation.

Some Edge layers are mapped to new layer purpose/pairs in the Design Framework II library.

Each Edge block/representation/revision is converted into a cell/cellview/version in a DesignFramework II library.


Additional Translation Inputs

■ Number of levels of UNIX hierarchy to translate.

■ Search path to Edge directories (block path) and Design Framework IIreference libraries.

■ Representations to translate as

— schematics

— schematic symbols

■ Database unit information (if not defined in the technology file).

■ User unit information (if not defined in the technology file).

■ Design Framework II library name for each Edge library directory.


Additional Translation Inputs

Additional translate program inputs include

■ Number of levels of UNIX hierarchy searched for revisions to be translated.

■ Path to Edge blocks to be translated and Design Framework II reference libraries, if aDesign Framework II exists in a directory, the library is used as a reference library andnone of the contents of the directory are translated. If translation is complete with anincomplete search path (that is, not all cellviews are found), then you need to retranslatewith the complete search path or update the affected cells individually.

■ Representations to translate as schematic lets you translate different Edgerepresentations as schematic diagrams. Typical examples include: schematic, cmos.sch,gate.sch.

■ Representations to translate as schematicSymbol, allows you to translate different Edgerepresentations as schematic symbols. The most common example is symbol.

■ userUnits per database unit for views not defined in the technology file.

■ User Units (userUnits) for any view not defined in the technology file.

■ The Design Framework II library name for each Edge library directory found must bespecified when running translate. A Design Framework II library is created in eachdirectory containing Edge blocks, but not already containing a Design Framework IIlibrary. You will be prompted for the name of each library created.


Connectivity Differences

■ The Edge environment and the Design Framework II environment havedifferences in the connectivity models.

— The path connectivity in the Design Framework II environment is basedon the center line rather than the edge.

— They have different algorithms for naming wire segments.

■ The SKILL routine, fixEdgeSch.il, accounts for connectivity differences.

■ The fixEdgeSch.il file is located in the tools/dfII/etc/tools/schematicdirectory.

■ Run fixEdgeSch.il prior to checking translated schematics.


Connectivity Differences

The connectivity models in the Edge and Design Framework II environments are similar, butnot identical. Wide wires in Edge connect to any other pin, wire, or path if these objectintersect the edge of the path. In the Design Framework II environment, wide wires connectto objects if the object intersects the center line of the wide wire.

Wire segments are named somewhat differently in the Edge and Design Framework IIenvironments. These differences may effect the success of a schematic connectivity update inthe Design Framework II environment, even though the schematic was successfully extractedin the Edge software.

The database translator does not correct these problems. The SKILL routine, fixEdgeSch.il,corrects these problems. The fixEdgeSch.il SKILL program is located in thetools/dfII/etc/tools/schematic directory.

The fixEdgeSch.il SKILL program should be run on the translated database, in DesignFramework II environment, prior to your checking of the translated database. If you update theconnectivity, then this program will not work correctly.


Lab Overview

Lab 13-1 Converting an Edge Schematic Database to Design Framework II


Lab Overview

Lab 13-1 Convert an Edge schematic database into Design Framework II.


Appendix A

Setup and Customization Files

Setup and Customization Files Appendix A

10/5/95 Cadence Design Systems, Inc. A-1

The .cdsinit File; Set library search path

dmSetLibPath(strcat(". " prependInstallPath("samples/cdslib ") prependInstallPath("samples/cdslib/asicWB ") prependInstallPath("etc/cdslib ") prependInstallPath("etc/cdslib/sheets ")))

hiGetCIWindow()->infix=t

simVerilogBreaktoolWindowLocation = '((634 288) (1024 588))

info("** End autoload of \".cdsinit\" **\n")

;END OF USER CUSTOMIZATION

Sun 4 .cshrc File#.cshrc for SUN3 and SUN4

#Cadence Training Database setup for the 9401 release

#

#Shell information + basic settings - C shell, file protection mask,

#no core file, enable file name expansion by pressing the ESCAPE key.

#

set SHELL = /bin/csh

set prompt = "‘hostname‘> "

umask 022

limit coredumpsize 0

set filec

#

#**********************************************************************#

#If a window session is running, find out if it is X of sunview

#

set window_type = X

# If this is a Sun Workstation, then find out if using Sunview or X

if ( -e /bin/sun ) then

set window_type = ‘ps -ac | egrep '(X|xnews)' | awk '{print $5}'‘

if ( $window_type != "" ) then

#echo "Using the X Window System"

set window_type = sunX

else

#echo "Using Sun Windows"

set window_type = sunview

endif

endif

#**********************************************************************#


A-2 Cadence Design Systems, Inc. 10/5/95

#Set the path variable and window setup

#

#This file assumes that the Cadence Suite of products are in the

#hierarchy /usr/cadence/9401.

#

#If the Cadence products are installed elsewhere change the

#variable CDS_INSTDIR to point to the correct path

#

#**********************************************************************#

setenv OPENWINHOME /usr/openwin

setenv XPATH /usr/bin/X11

#

setenv CDS_INSTDIR /usr/cadence/9401

setenv CDS_INST_DIR $CDS_INSTDIR # TDM requires this

setenv tangat $CDS_INSTDIR/tools/tangate

setenv cell $tangat

setenv VERDIR $CDS_INSTDIR/tools/vtools

setenv CDSDIR $CDS_INSTDIR/tools/dfII

setenv DRACDIR $CDS_INSTDIR/tools/dracula

#setenv VALIDDIR $CDS_INSTDIR/tools/valid ??? not yet implemented

setenv VALIDDIR /usr/valid/tools

setenv veritools $VERDIR

setenv CDS_VHDL $CDS_INSTDIR/tools/leapfrog

#

#**********************************************************************#

#Product specific information - must define LEMACS_ROOTDIR for use

#in path.

#End user must specify the correct directory if this is not the

#correct directory.

#**********************************************************************#

#

#LEAPFROG

#

setenv LEMACS_ROOTDIR /usr1/lemacs19.6

#

#**********************************************************************#

#

set path= (. ~ \

$OPENWINHOME/bin $OPENWINHOME/bin/xview $OPENWINHOME/demo \

$XPATH \

$CDS_INSTDIR/tools/bin\

$CDSDIR/bin \

$VALIDDIR/bin \

$VALIDDIR/fet/bin \



$VALIDDIR/pcb/bin \

$CDS_VHDL/bin \

$LEMACS_ROOTDIR/lemacs/bin \

$VERDIR/vlog/exe \

$VERDIR/vtime/bin \

$VERDIR/vfault/exe \

$CDSDIR/etc/te \

$tangat/lib \

$cell/lib $cell/lib/cell3 \

$DRACDIR/bin \

$CDS_INSTDIR/share/license \

/bin /usr/bin \

/usr/local /usr/ucb /usr/hosts /usr/etc )

#

#Search path for the command cd

#

set cdpath=(~ .)

#

#Set path based on window environment. Only for suns

#

if ( $window_type == "sunview" ) then

set path= ( /bin /usr/bin \

$path )

endif

set X = "OPENWINDOWS"

if ( -e $OPENWINHOME/bin/xnews ) then

set X = "OPENWINDOWS"

else if( -e $XPATH/xnews ) then

set X = "OPENWINDOWS")

else if( -e $XPATH/xinit ) then

set X = "X11"

endif

setenv EXINIT 'set wm=5 tabstop=4 number lisp'

setenv DEFAULT_FONT "/usr/lib/fonts/fixedwidthfonts/screen.r.16"

setenv EDITOR 'xterm -geometry 85x40 -e vi'

setenv DISPLAY unix:0

#setenv NOPSWM

if("$X" == "X11") then

alias xwin 'set path = ($XPATH $path);xinit'

else



alias xwin 'clear_colormap;set path = ($OPENWINHOME/bin $path);openwin -noauth > &/dev/null'

endif

#

#

#**********************************************************************#

#Product specific information

#**********************************************************************#

#

#CONCEPT and ALLEGRO

#

setenv VALID_EDITOR CONCEPT

setenv TELENV $VALIDDIR/pcb/text/env

setenv VEC $VALIDDIR/pcb/vec

set GLOBAL = $VALIDDIR/pcb/text

set TELMSG = $GLOBAL/allegro.msg

#**********************************************************************#


#**********************************************************************#

#

#DRACULA - is this still needed

#

setenv DRACLIB4 $DRACDIR

setenv DRACHELP4 $DRACDIR

#**********************************************************************#


#**********************************************************************#

#

#SPICE 2G.6 - needs Fortran run time libraries

#TDM requires some Cadence supplied libraries

#Leapfrog requires some libraries

#

setenv LD_LIBRARY_PATH/usr/lib:/usr/lang/SC1.0:${CDS_INSTDIR}/tools/lib:${CDS_VHDL}/lib

#**********************************************************************#


#**********************************************************************#

#

#VERITOOLS



setenv ver_install $veritools/vlog

setenv vef_install $veritools/vfault

setenv vet_install $veritools/vtime

alias verifault $vef_install/exe/verifault -a

#**********************************************************************#


#**********************************************************************#

#

#TEAM DESIGN MANAGER (TDM)

#

setenv MANPATH $CDS_INSTDIR/share/man:/usr/man

setenv XKEYSYMDB $CDS_INSTDIR/share/dtsetup/XKeysymDB

setenv XNLSPATH $CDS_INSTDIR/share/dtsetup/nls

#

#

#**********************************************************************#

#Frameviewer should be in $CDSDIR/frame in order to use online

#help.

#If Frameviewer is not in $CDSDIR/frame and you do not have the

#privilege to create a symbolic link, set the variable

#

# FMHOME

#

#to point to the Frameviewer/maker installation path

#

#setenv FMHOME /Frame

#**********************************************************************#

#**********************************************************************#

#Useful aliases - most of these are set in instructors' login accounts

#**********************************************************************#

#

#

alias . suspend

alias cl clear

alias hi history 20

alias l ls -sF

alias ll ls -lasF

alias pd pushd

alias pev printenv



alias po popd

alias so source

alias lo logout

alias mail Mail

if ( $?prompt ) then

set prompt="‘whoami‘@‘hostname‘ [\!]> "

endif

set history = 100

set savehist=100

#

#

#

#**********************************************************************#

# If you have problem bringing up X which is related to not being

# able to recognize the graphics hardware device, set the following

# variable to the correct hardware device.

#

# The command /etc/dmesg | grep cg will list the line containing

# the name of the color graphics device

#

# The command /etc/dmesg | grep bw will list the line containing

# the name of the monochrome graphics device

#

#

#setenv FRAMEBUFFER /dev/<graphics>

#

#Entries for the IRVINE training center

#

#Uncomment as necessary

#

#setenv PRINT /usr/transcript/sparc

#setenv PRINTER lwFront

#setenv alias print enscript

#set path=($PRINT/bin $path)

#

#END OF THE .cshrc file

#

#**********************************************************************#

HP .cshrc File#!/bin/csh

#.cshrc for HP 700


#





#


umask 022

#limit coredumpsize 0

set filec

stty erase ^H

#

#**********************************************************************#


#



#



#

#**********************************************************************#


#


setenv TANGAT $CDS_INSTDIR/tools/tangate

setenv CELL $CDS_INSTDIR/tools/tancell




setenv VALIDDIR $CDS_INSTDIR/tools/valid

setenv OLDVALIDDIR /usr/valid



#

#**********************************************************************e


#in path.


#correct directory.

#**********************************************************************#

#

#LEAPFROG

#


#

#**********************************************************************#

#

set path= (. ~ \

$XPATH \




$CDSDIR/bin \

$VALIDDIR/bin \

$OLDVALIDDIR/tools/bin OLDVALIDDIR/tools/framework/bin \

$OLDVALIDDIR/tools/fet/bin OLDVALIDDIR/tools/fet/fetsetup \

$OLDVALIDDIR/tools/pcb/bin OLDVALIDDIR/tools/fet/fetsetup \

$CDS_VHDL/bin \


$VERDIR/vlog/exe \

$VERDIR/vtime/bin \


$CDSDIR/etc/te \

$TANGAT/lib \

$CELL/lib \

$DRACDIR/bin \

/te /cell/lib /cell/lib/cell3 /tangat/lib \


/bin /usr/bin \


#




#

#**********************************************************************#


#**********************************************************************#

#


#


setenv TELENV $OLDVALIDDIR/tools/pcb/text/env

setenv VEC $OLDVALIDDIR/tools/pcb/vec

set GLOBAL = $OLDVALIDDIR/tools/pcb/text


#**********************************************************************#


#**********************************************************************#

#


#



#**********************************************************************#


#**********************************************************************#



#


#

setenv LD_LIBRARY_PATH /usr/lib:/usr/lang/SC1.0

#**********************************************************************#


#**********************************************************************#

#

#VERITOOLS

#




#

#**********************************************************************#


#help.



#

# FMHOME

#


#


#**********************************************************************#

#

#**********************************************************************#


#**********************************************************************#

#

#

alias . suspend

alias cl clear

alias hi history 20

alias l ls -sF

alias ll ls -lasF

alias pd pushd

alias pev printenv

alias po popd

alias so source

alias lo logout

alias mail Mail





endif

set history = 100

set savehist=100

#

#

#**********************************************************************#

#


#

#**********************************************************************#

DEC .cshrc File#!/bin/csh

#.cshrc for DECstations


#



#


umask 022


set filec

#

#**********************************************************************#


#



#



#

#**********************************************************************#


#













#

#**********************************************************************e


#in path.


#correct directory.

#**********************************************************************#

#

#LEAPFROG

#


#

#**********************************************************************#

#

set path= (. ~ \

$XPATH \


$CDSDIR/bin \

$VALIDDIR/bin \




$CDS_VHDL/bin \


$VERDIR/vlog/exe \

$VERDIR/vtime/bin \


$CDSDIR/etc/te \

$TANGAT/lib \

$CELL/lib \

$DRACDIR/bin \



/bin /usr/bin \


#




#

#**********************************************************************#


#**********************************************************************#

#




#






#**********************************************************************#


#**********************************************************************#

#


#



#**********************************************************************#


#**********************************************************************#

#


#


#**********************************************************************#


#**********************************************************************#

#

#VERITOOLS

#




#

#**********************************************************************#


#help.



#

# FMHOME

#


#


#**********************************************************************#

#

#**********************************************************************#




#**********************************************************************#

#

#

alias . suspend

alias cl clear

alias hi history 20

alias l ls -sF

alias ll ls -lasF

alias pd pushd

alias pev printenv

alias po popd

alias so source

alias lo logout

alias mail Mail



endif

set history = 100

set savehist=100

#

#

#**********************************************************************#

#


#

#**********************************************************************#

IBM RS/6000 .cshrc File#!/bin/csh

#.cshrc for IBM RS/6000


#



#


umask 022

limit coredumpsize 0

set filec

#

#**********************************************************************#


#





#



#

#**********************************************************************#


#











#

#**********************************************************************#


#in path.


#correct directory.

#**********************************************************************#

#

#LEAPFROG

#


#

#**********************************************************************#

#

set path= (. ~ \

$XPATH \


$CDSDIR/bin \

$VALIDDIR/bin \




$CDS_VHDL/bin \


$VERDIR/vlog/exe \

$VERDIR/vtime/bin \




$CDSDIR/etc/te \

$TANGAT/lib \

$CELL/lib \

$DRACDIR/bin \



/bin /usr/bin \


#



setenv EDITOR 'aixterm -geometry 85x40 -e vi'

setenv DISPLAY unix:0

#setenv NOPSWM

alias xwin 'set path = ($XPATH $path);xinit -bs'

#

#**********************************************************************#


#**********************************************************************#

#


#






#**********************************************************************#


#**********************************************************************#

#


#



#**********************************************************************#


#**********************************************************************#

#




#


#**********************************************************************#


#**********************************************************************#

#

#VERITOOLS




#**********************************************************************#


#help.



#

# FMHOME

#


#


#**********************************************************************#

#**********************************************************************#


#**********************************************************************#

#

#

alias . suspend

alias cl clear

alias hi history 20

alias l ls -sF

alias ll ls -lasF

alias pd pushd

alias pev printenv

alias po popd

alias so source

alias lo logout

alias mail Mail



endif



set history = 100

set savehist=100

#

#

#**********************************************************************#

#


#

#**********************************************************************#

The .login File#!/bin/csh -f

#

###############################################################

#

# Copyright 1992

#

# CADENCE DESIGN SYSTEMS INCORPORATED

#

# The copyright notice appearing above is included to provide statutory

# protection in the event of unauthorized or unintentional public disclosure

# without written consent of an officer of Cadence Design Systems Incorporated.

#

#######################################################################

#

# If the file .cds_started exists do nothing - The user has already

# logged into this account once and has made his/her choices.

# Do not modify anything

# If the file does not exist, find the platform type.

# If the platform is a sun ask user to choose Motif or OPENLOOK as the

# window manager.

# Then copy the correct .cshrc and X files from the platform specific

# files in dotfiles.

#

#

set platform="unknown"

set winmanager="unknown"

if (! -e $HOME/.cds_started) then

echo " "

echo " "

echo " "

echo "****************************************************************"

echo "You have not installed the dot files for this class"



echo "This procedure will install all the dot files"

echo "****************************************************************"

echo " "

echo " "

cp $HOME/.login $HOME/.login.save

$HOME/dotfiles/class_install

cp $HOME/.login.save $HOME/.login

else

set platform=‘grep Platform .cds_started | awk '{print $2}'‘

set winmanager=‘grep WindowManager .cds_started | awk '{print $2}'‘

echo "****************************************************************"

echo " "

echo "Your course directory has already been set up for a $platform machine"

#if("$winmanager" != "sunview") then

# echo "to run the X Window System using the $winmanager Window Manager."

#else

echo "to run $winmanager."

#endif

echo " "

echo "The Cadence software is installed under the directory"

echo " $CDS_INSTDIR "

echo " "

echo "To start the X Window System, type xwin"

echo " "

echo " "

echo "If you want to change the set up, delete the file ~/.cds_started"

echo " "

echo " Example: rm ~/.cds_started"

echo " "

echo " "

echo "and log out and log back in."

echo " "

echo "****************************************************************"

endif

# Initialization complete

#

#Do any platform specific initialization such setting terminal type

set ignoreeof

set time=15

set notify

set deftty=M2


set a = ""

set tty=‘tty‘



if ( $tty !~ /dev/tty[pq]* ) then

if ( -e /bin/uname ) then

set a=$deftty;

endif

if ( -e /bin/sun ) then

set a=sun

endif

if ( -e /com/rbak ) then

set a=apollo_color

endif

if ( -e /bin/mdterm ) then

set a=xterm

endif

else

set a=‘printenv TERM‘

endif

if ( -d /usr/spool/mail ) then

alias ts 'set noglob; eval ‘tset -s -I -Q \!*‘; stty crt dec ; unset noglob'

else

alias ts 'set noglob; eval ‘tset -s -I -Q \!*‘; stty echoe dec ; unset noglob'

endif

if($platform == "decds") then

ts $a

endif

unset deftty

if ( $tty !~ /dev/ttyp* ) then

echo you are on terminal ‘tty‘\; the time is ‘date‘.

endif

#uptime

unset tty

The .Xdefaults File

! ************.Xdefaults****************

!

! The following are examples of Resources that

! the user may wish to set.

!

! The "!" character is a comment. To activate a resource,

! you can remove the ! character at the beginning of a line.

!



! A lot of .Xdefaults files use "#" as the comment character,

! this should be avoided.

!

! Remember that you need to run the "xrdb" program to

! have a resource take effect once the X server has been started.

! You can invoke it as "xrdb ~/.Xdefaults"

! xrdb reads the new .Xdefaults file into the server.

!

! For Opus, beware of loose bindings (eg "Opus*resource:") as they may

! cause a conflict with some things that you set in Skill.

!

! All Opus resources are Opus.<resource>:

!

! ********************************************************

! * These resources set the default position of the CIW. *

! ********************************************************

!

!Opus.x: !!!(screen_width - Opus.width)/2

!Opus.y: 0

!Opus.width: 725

!Opus.height: 130

! *** Or you can use the geometry specification

! *** if you don't want to use the x,y,width,height

! *** resources independently

!Opus.geometry:

! **********************************************

! * These resources allow you to set the fonts *

! **********************************************

!Opus.labelFont: -*-helvetica-bold-r-*-*-12-*

!Opus.textFont: -*-courier-medium-r-*-*-12-*

! ****************************************************

! * This resource lets you specify which text editor *

! * you want to use. *

! ****************************************************

!Opus.textEditor:

! **************************************

! * This resource lets you set the *

! * colors used by the user interface. *

! **************************************

!Opus.foreground: #800000

!Opus.background: #e0e0e0

!Opus.borderColor: #0000c0

!Opus.recessColor: #bfbfbf

!Opus.activeBannerColor: #bdcccc

!Opus.inactiveBannerColor: #cccccc

!Opus.textColor: #333333



!Opus.attentionTextColor: #333333

!Opus.flashColor: #ff00ff

!Opus.topShadowColor: #ffffff

!Opus.bottomShadowColor: #999999

!Opus.buttonColor: #800000

!Opus.editorBackground: #000000

!**************************************

! ****************************************************

! * These resources allow you to specify the default *

! * positions for forms. *

! ****************************************************

!Opus.formPlacement: one of top,bottom,left,right, or center

!Opus.formRelativeTo: one of screen,currentWindow, or CIW

!Opus.optionFormPlacement: one of top,bottom,left,irhgt or center

!Opus.optionFormRelativeTo: one of screen,currentWindow, or CIW

!

! ** END OPUS RESOURCES

!

! Here are some defaults for the xterm

XTerm*foreground:yellow

XTerm*background:darkslategrey

XTerm*border:turquoise

XTerm*cursorColor:yellow

XTerm*sunFunctionKeys:True

XTerm*jumpScroll:True

XTerm*pointerColor:red

XTerm*scrollBar:True

XTerm*saveLines:120

XTerm*scrollKey:True

XTerm*font:9x15

!

! Remove cpmment on next line for MIPS

!XTerm*TtyModes:erase ^H kill ^U intr ^C

! Here are some defaults for the IBM aixterm

aixterm*foreground:yellow

aixterm*background:darkslategrey

aixterm*border:turquoise

aixterm*cursorColor:yellow

aixterm*sunFunctionKeys:True

aixterm*jumpScroll:True

aixterm*pointerColor:red

aixterm*scrollBar:True

aixterm*saveLines:120



aixterm*scrollKey:True

aixterm*font:9x15

OpenWindows.WorkspaceColor: #40a0c0

OpenWindows.WindowColor: #cccccc

OpenWindows.IconLocation: bottom

OpenWindows.DragRightDistance: 100

OpenWindows.SelectDisplaysMenu: False

OpenWindows.SetInput: followmouse

OpenWindows.Beep: always

OpenWindows.ScrollbarPlacement: right

OpenWindows.PopupJumpCursor: True

OpenWindows.MultiClickTimeout: 4

Scrollbar.JumpCursor: True

OpenWindows.ColorFocusLocked:True

OpenWindows.Palette:fall

!

!

! SAMPLE .Xdefaults RESOURCE SPECIFICATIONS FOR MWM

!

!

! component appearance resources

!

Mwm*clientAutoPlace:False

Mwm*colormapFocusPolicy:explicit

Mwm*keyboardFocusPolicy:pointer

Mwm*InteractivePlacement: False

Mwm*menu*background:CadetBlue

Mwm*menu*foreground:Yellow

Mwm*foreground:white

Mwm*background:SteelBlue

Mwm*fontList:9x15

Mwm*backgroundTile:background

Mwm*activeBackground:CadetBlue

Mwm*transientDecoration: titlebar + resize - menu

Mwm*buttonBindings:SampleButtonBindings

Mwm*windowMenu:SampleWindowMenu

Mwm*keyBindings:SampleKeyBindings

Mwm*focusAutoRaise:False

Mwm*enforceKeyFocus:False

Mwm*saveUnder:True

Mwm*useIconBox:False

Mwm*frameBorderWidth:3

Mwm*resizeBorderWidth:5

Mwm*cleanText: True



Mwm*positionIsFrame: False

Mwm*xclock.clientDecoration: border

Mwm*Clock.clientDecoration: border

Mwm*mailtool.clientDecoration: border

Mwm*xbiff.clientDecoration: title border

!Mwm*Opus*transientDecoration: titlebar + resize - menu

!Mwm*opus3*transientDecoration: titlebar + resize - menu +minimize

!#########################################################################

! Following are the .Xdefaults additions recommended for

! FrameMaker 2.1X:

! Frame 2.1X Specific defaults

Maker.doubleClickTenths: 10

Maker.useBackingStore: True

Maker.cmdEscape: True

Maker.autoBackupOnSave: True

Maker.autoSave: True

Maker.autoSaveTime: 5

Maker.autoSaveIdleTime: 10

Maker.greekSize: 7

Maker.foreground: white

Maker.background: turquoise

Maker.console: True

Maker.noViewerFile: True

Maker.colorDocs:True

Maker.colorImages:True

Maker.olwmClickType: False

Maker.printerName: lw

!

!

xterm*loginShell: True

sm.windowManagerName:mwm

sm.create_terminal:0

sm.AutoStart:Xterm

sm.Xterm.command:xterm -title "Cadence" -geometry +0+0

sm.num_AutoStart:1

sm.confirm_endsession:1

!#include $CDS_VHDL/files/X/cdsApp



HP .xinitrc File for the Motif Window Manager#.xinitrc for #SUN4/SUN3 using Motif as the window manager

#Cadence training course

#Set backward compatability if X11R4 only - remove comment on next line

#xset bc &

#

xterm -sb -font 9x15 -C -n "console" -geometry 80x10-0-0 &

#

xclock -geometry 80x80-0+0 &

xterm -geometry 85x40 -title "Cadence" &

mwm

Sun 4 .xinitrc File for the Motif Window Manager#.xinitrc for #SUN4/SUN3 using Motif as the window manager



#xset bc &

#


#

clock -geometry 80x80-0+0 &


mwm

IBM RS 6000 .xinitrc File for the Motif Window Manager#.xinitrc for IBM RS/6000 using Motif as the window manager



#xset bc &

#

aixterm -sb -fn 9x15 -name Console -geometry 80x10-0-0 &

#

xclock -geometry 80x80-0+0 &

aixterm -geometry 85x40 -title "Cadence" &

mwm



OPEN LOOK .xinitrc File for the Motif Window Manager#.xinitrc for #SUN4/SUN3 using Motif as the window manager



#xset bc &

#


#



olwm

Sun 4.xinitrc File for the Motif Window Manager#.xinitrc for #SUN4/SUN3 using Motif as the window manager



#xset bc &

#


#



mwm

Appendix B

Reference Materials

Reference Materials Appendix B

10/5/95 Cadence Design Systems, Inc. B-1

adder4bit Functional Descriptionmodule adder4bit (Cout, S, A, B, Cin);

output Cout;

output [3:0] S;

input [3:0] A;

input [3:0] B;

input Cin;

reg [4:0] SUM;

reg [3:0] S;

reg Cout;

wire [3:0] A, B;

always @(A or B or Cin)

begin

SUM[4:0] = A+B+Cin;

S = SUM [3:0];

Cout = SUM[4];

end

endmodule


B-2 Cadence Design Systems, Inc. 10/5/95

dff2 Functional Descriptionmodule dff2(q,qb,d,clk,clr);

input d;

input clk,clr;

output q,qb;

reg regi;

always @(posedge clk)

if (clr)

regi= 0;

else

regi=d;

assign #1 q = regi;

assign #2 qb = ~q;

endmodule



REGCTR Functional Description// Verilog HDL for msqLib, REGCTR _functional

module REGCTR(R,D,RLD_,Load_,Decrement,CP);

output [11:0] R ;

input [11:0] D ;

input RLD_,Load_,Decrement,CP;

reg [11:0] reg_i ;

assign R = reg_i ;

always @(posedge CP)

begin

if ((Load_ && RLD_) == 0)

reg_i = D ;

if (Decrement)

reg_i = reg_i - 1 ;

end

endmodule


B-4 Cadence Design Systems, Inc. 10/5/95

counter.v File// This is a Verilog description of a 5-bit counter.

module counter(cnt,clk,cntIn,data,rst,le);

input clk,cntIn,rst,le;

input [4:0] data;

output [4:0] cnt;

dff2 u0(cnt[0],,d0,clk,rst);





mux u5(d0,data[0],cntIn,le);

mux u6(d1,data[1],b1,le);




xor (b1,cnt[0],cnt[1]);

xor (b2,cnt[2],t2);

xor (b3,cnt[3],t3);

xor (b4,cnt[4],t4);

and (t2,cnt[0],cnt[1]);

and (t3,cnt[0],cnt[1],cnt[2]);

and (t4,cnt[0],cnt[1],cnt[2],cnt[3]);

endmodule

// -----------------------------------------------

module dff2(q,qb,d,clk,clr);

input d;



input clk,clr;

output q,qb;

reg regi;

always @(posedge clk)

regi= 0;

else

regi=d;

assign #1 q = regi;

assign #2 qb = ~q;

endmodule

// ------------------------------------------------

module mux(out,a,b,sel);

input a,b,sel;

output out;

not (a1,sel);

and (z1,a,a1);

and (z2,b,sel);

or (out,z1,z2);

endmodule

// --------------------------------------------------

Appendix C

Lab Example Designs

Lab Example Designs Appendix C

10/5/95 Cadence Design Systems, Inc. C-1

HA Schematic

FA Schematic


C-2 Cadence Design Systems, Inc. 10/5/95

FA Symbol



adder4bit Schematic



adder4bit Symbol

adder8bit Index Schematic



adder8bit Sheet 1



adder8bit Sheet 2



adder8bit Sheet 3



CounterSlice Schematic

CL

K

EN

CE

NT

PL

D D

UP

_DO

WN

Q

TC



eventCounter Schematic

Documents

IC/ASIC Design Composition and Analysisread.pudn.com/downloads109/doc/452371/Cadence及MEDICI使用/ICca… · IC/ASIC Design Composition and Analysis Table of Contents ... Lab 3-6