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Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
IC Tester at CERNIC Tester at CERN
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
Mixed Signal Tester at CERNMixed Signal Tester at CERNDigital Part: Tester channels: 128 ATS 200/125/100 Data Modules Test speed: 100 MHz / 200 MHz (2 X
mode) Test vector depth: 128K / 256K (2 X
mode) Repeat and looping capabilities of test
vectors. Timing resolution: 50 ps Number of timing generators: 11
(shared between channels) Different Timing formats: Per channel high and low driving levels
with 10 mV resolution Per channel high and low compare
levels with 10 mV resolution Programmable current load per
channel.
IMS Tester: Available since 1998 Digital 200 MHz Tester and VXI Extension for analog
instrumentation Clean Room with Karl Suss wafer prober
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
Configuration for Analog TestsConfiguration for Analog TestsAnalog Part:
VXI mainframe ( Tektronix VX1410) Slot 0 controller (National Instruments
VXIpc-850) 2 X 250 MHz arbitrary waveform
generator (Tektronix VX4792) 12 Channel 16 bit analog reference
generator (Tektronix VX4730) 2 channel 1GHz 8 bit digitizer (Tektronix
TVS621) 1 channel 20MHz 23/18 bit digitizer (HP
E1437A) Digital Volt Meter (HP E1411B ) 6 x ( 4 to 1) RF switch matrix (HP
E1472A) Synchronization module (MicroLEX VXI-
SYNC) Quad programmable power supply (HP
HP6624A)
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
NRZ
DNRZ
RZRZI
R1
RI
RC
SBC
2xRZ
2xR1
0 1 Z 0
Cycle start
Cycle boundary
Cycle boundary
Cycle boundary
High drive
Low drive
Cycle Time
width
delay
Data Format : RZ
Timing resolution 50 ps
Resolution 10 mV
Slew rates
09
IC tester: Operating ConditionsIC tester: Operating ConditionsForce groupsForce groups
~200 Hz - 200 MHz
Signals can be related by a formula, e.g.: DELAY(2) =DELAY(1)+30 ns
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
IC Tester: Operating ConditionsIC Tester: Operating ConditionsCompare Groups and Test VectorsCompare Groups and Test Vectors
High Thresh.
Low Thresh.Compare edgetime
Acquired dataForced data
Expected values
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
Expected testsExpected tests
• Chip debugging: ICT* • Crosstalk checks: ICT + LS• Timewalk: ICT• Double pulse resolution: ICT• “S” curves, threshold, delay scan: ICT(?) + LS• Tests with radioactive source: LS + MC based setup• Beam Tests: MC based setup• Possibility to use the Wafer prober at CERN:
– connection to ICT– connection to LS (BusTest soft.)
* ICT stands fot tester, LS stands for Lab Setup
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
VME-MXI-PCI Bridge and Bus VME-MXI-PCI Bridge and Bus ExtenderExtender
Extends VME to several mainframes Bidirectional VMEbus transfers Up to 8 VXI or VME chassis can be Connected using MXIbus Supports transparent interrupts
between mainframes
PCI-MXI2 bridge: the setup is controlled by using the CPU of the PC
DMA transfers at rates up to 38Mbytes/s using D64
Entirely software configurable Optional dual-ported DRAM expansion
up to 64 MB
PCI -MXI Interface Module
Additional MXI-2Cable
MXI-2
VME -MXI Module
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
DAQ Test SystemDAQ Test SystemVME Pilot card performs:
• data acquisition • zero suppression• event buffering
Trigger logic
DAQ adapter board
Test board
JTAG controller
PCI-MXI-2
External PS
The tasks performed by the DAQ system:
Full chip characterization (threshold scan, delay scan)
Tests with RA source Beam tests
Laboratory setup: PCI-VME bridge Labview software
Testbeam setup: MVME processor DATE - Alice DAQ software
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
DAQ BoardsDAQ Boards
Level adapter for JTAG
Level adaptionfor GTL/TTL
PS + BIAS
Detector
Free area
Buffering for observation
DAQ adapter board Test board
Pins to connect to ICTJTAG chain
Connection to Pilot
Connection to JTAG
BSD
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
Programming the HP 16500CProgramming the HP 16500C
Direct programming using the touch screen
Remote programming over LAN, GPIB or RS-232
Programming over LAN:
X11 interface for direct programming connection to /system/program directory
using FTP, MS networks mapping or NFS
TELNET connection Access to Port 5025
Example: The Pilot trigger sequence generated by HP16522A, captured by HP16550 and displayed over
X11 on a remote PC
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
JTAG Hardware ControllerJTAG Hardware Controller IEEE 1149.1/100f ISA bus PC card 4 TAP controllers or 3 TAP controllers + 1 RS422 port maximum TCK frequency 25 MHz maximum scanning data length: 232
bits
Bundled software: 100f SFL (Scan Function Library)
Win95/98/NT “C” library in form of a DLL module
Provides access to low level scanning functions
Callable from LabView
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
JTAG Test BoardJTAG Test Board Board layout:
– 16 chips (0…15)• 8 pixels/chip (0…7)• pixel matrix:
– 4 rows x 2 columns– 3 bits of THR / pixel– 2 (3) bits T/M / pixel
• 2 GR / chip (12 bit each) 5 “enable“ bits + “Bit_0, Bit_1”
Enable matrix:
Board
Chip
PixelBit_1 Bit_0 Sel
0 0 None
0 1 TH0 / T
1 0 TH1 / M0 1 TH2
Peter Chochula CERN-ALICE / Department Of Nuclear Physics MFF UK Bratislava
Pilot-Serlink Test SystemPilot-Serlink Test System
PCI-VME
Data Logger
Error Analyzer
Test Panel
VISA Layer
Ethernet
HP16500C
GPIBRX FiFo
RX FiFo
TX FiFo
TX FiFo
C/SR
C/SR
Test
Run
Test?
VME
BUS
Link
Yes No
Mode?