IBM z/Architecture Reference Summary

z/Architecture IBMr

Reference Summary

SA22-7871-10

.

z/Architecture IBMr

Reference Summary

SA22-7871-10

Eleventh Edition (September, 2019)

This revision differs from the previous edition by containing instructions related to the facilities marked by a bar under “Facility” in “Preface” and minor corrections and clari-fications. Changes are indicated by a bar in the margin.

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ii z/Architecture Reference Summary

PrefaceThis publication is intended primarily for use by z/Architecture™ assembler-language application programmers. It contains basic machine information summarized from the IBM z/Architecture Principles of Operation (SA22-7832), about the IBM z Systems™ processors. It also contains frequently used information from IBM ESA/390 Common I/O-Device Commands and Self Description (SA22-7204), IBM System/370 Extended Architecture Interpretive Execution (SA22-7095), The Load-Program-Parameter and the CPU-Measurement Facilities (SC23-2260), and IBM High Level Assembler for z/OS, z/VM & z/VSE Language Reference (SC26-4940). This publication will be updated from time to time. However, the above publications and others cited in this publication are the authoritative reference sources and will be first to reflect changes.

The following instructions may be uninstalled or not available on a particular model:

Facility Instruction

ASN-and-LX-reuse EPAIR, ESAIR, PTI, SSAIR

Compare-and-swap-and-store CSST

Configuration-topology PTF

Constrained-transactional-execution TBEGINC

DAT-enhancement 1 CSPG, IDTE

DAT-enhancement 2 LPTEA

Decimal-floating-point ADTR, AXTR, CDGTR, CDSTR, CDTR, CDUTR, CEDTR, CEXTR, CGDTR, CGXTR, CSDTR, CSXTR, CUDTR, CUXTR, CXGTR, CXSTR, CXTR, CXUTR, DDTR, DXTR, EEDTR, EEXTR, ESDTR, ESXTR, FIDTR, FIXTR, IEDTR, IEXTR, KDTR, KXTR, LDETR, LDXTR, LEDTR, LTDTR, LTXTR, LXDTR, MDTR, MXTR, QADTR, QAXTR, RRDTR, RRXTR, SDTR, SLDT, SLXT, SRDT, SRXT, SXTR, TDCDT, TDCET, TDCXT, TDGDT, TDGET, TDGXT

DEFLATE-conversion DFLTCC

DFP-rounding SRNMT

DFP-packed-conversion CDPT, CPDT, CPXT, CXPT

DFP-zoned-conversion CDZT, CXZT, CZDT, CZXT

Distinct-operands AGHIK, AGRK, AHIK, ALGHSIK, ALGRK, ALHSIK, ALRK, ARK, NGRK, NRK, OGRK, ORK, SGRK, SLAK, SLGRK, SLLK, SLRK, SRAK, SRK, SRLK, XGRK, XRK

Enhanced-DAT 1 PFMF

Enhanced-DAT 2 CRDTE

Execute-extensions EXRL

Execution-hint BPP, BPRP, NIAI

Expanded-storage PGIN, PGOUT

Extended-immediate AFI, AGFI, ALFI, ALGFI, CFI, CGFI, CLFI, CLGFI, FLOGR, IIHF, IILF, LBR, LGBR, LGHR, LGFI, LHR, LLC, LLCR, LLGCR, LLGHR, LLH, LLHR, LLIHF, LLILF, LT, LTG, NIHF, NILF, OIHF, OILF, SLFI, SLGFI, XIHF, XILF

Extended-translation 2 CLCLU, MVCLU, PKA, PKU, TP, TROO, TROT, TRTO, TRTT, UNPKA, UNPKU

Extended-translation 3 CU14, CU24, CU41, CU42, SRSTU, TRTR

Extract-CPU-time ECTG

Floating-point-extension ADTRA, AXTRA, CDFBRA, CDFTR, CDGBRA, CDG-TRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA, CEGBRA, CELFBR, CELGBR, CFDBRA, CFDTR, CFE-BRA, CFXBRA, CFXTR, CGDBRA, CGDTRA, CGEBRA, CGXBRA, CGXTRA, CLFDBR, CLFDTR, CLFEBR, CLFXBR, CLFXTR, CLGDBR, CLGDTR, CLGEBR, CLGXBR, CLGXTR, CXFBRA, CXFTR, CXGBRA, CXG-TRA, CXLFBR, CXLFTR, CXLGBR, CXLGTR, DDTRA, DXTRA, FIDBRA, FIEBRA, FIXBRA, LDXBRA, LEDBRA, LEXBRA, MDTRA, MXTRA, SDTRA, SRNMB, SXTRA

Floating-point-support-sign-handling CPSDR, LCDFR, LNDFR, LPDFR

FPR-GR-transfer LDGR, LGDR

iii

General-instructions-extension ASI, AGSI, ALSI, ALGSI, CRB, CGRB, CRJ, CGRJ, CRT, CGRT, CGH, CHHSI, CHSI, CGHSI, CHRL, CGHRL, CIB, CGIB, CIJ, CGIJ, CIT, CGIT, CLRB, CLGRB, CLRJ, CLGRJ, CLRT, CLGRT, CLHHSI, CLFHSI, CLGHSI, CLIB, CLGIB, CLIJ, CLGIJ, CLFIT, CLGIT, CLRL, CLHRL, CLGRL, CLGHRL, CLGFRL, CRL, CGRL, CGFRL, ECAG, LAEY, LTGF, LHRL, LGHRL, LLHRL, LLGHRL, LLGFRL, LRL, LGRL, LGFRL, MVHHI, MVHI, MVGHI, MFY, MHY, MSFI, MSGFI, PFD, PFDRL, RNSBG, RXSBG, RISBG, ROSBG, STHRL, STRL, STGRL

Guarded storage LGG, LGSC, LLGFSG, STGSC

HFP-multiply-and-add/subtract MAD, MADR, MAE, MAER, MSD, MSDR, MSE, MSER

HFP-unnormalized extensions MAY, MAYR, MAYH, MAYHR, MAYL, MAYLR, MY, MYH, MYL, MYR, MYHR, MYLR

High-word AHHHR, AHHLR, AIH, ALHHHR, ALHHLR, ALSIH, ALSIHN, BRCTH, CHF, CHHR, CHLR, CIH, CLHF, CLHHR, CLHLR, CLIH, LBH, LHH, LFH, LLCH, LLHH, RISBHG, RISBLG, SHHHR, SHHLR, SLHHHR, SLHHLR, STCH, STHH, STFH

IEEE-exception-simulation LFAS, SFASR

Insert-reference-bits-multiple facility IRBM

Interlocked-access LAA, LAAG, LAAL, LAALG, LAN, LANG, LAO, LAOG, LAX, LAXG, LPD, LPDG

Load-and-trap LAT, LFHAT, LGAT, LLGFAT, LLGTAT

Load-and-zero-rightmost-byte LLZRGF, LZRF, LZRG

Load/store-on-condition facility 1 LOC, LOCG, LOCGR, LOCR, STOC, STOCG

Load/store-on-condition facility 2 LOCFH, LOCFHR, LOCGHI, LOCHHI, LOCHI, STOCFH

Long displacement AHY, ALY, AY, CDSY, CHY, CLIY, CLMY, CLY, CSY, CVBY, CVDY, CY, ICMY, ICY, LAMY, LAY, LB, LDY, LEY, LGB, LHY, LMY, LRAY, LY, MSY, MVIY, NIY, NY, OIY, OY, SHY, SLY, STAMY, STCMY, STCY, STDY, STEY, STHY, STMY, STY, SY, TMY, XIY, XY

Message-security-assist KM, KMC, KIMD, KLMD, KMAC

Message-security-assist extension 3 PCKMO

Message-security-assist extension 4 KMCTR, KMF, KMO, PCC

Message-security-assist extension 5 PRNO

Message-security-assist extension 8 KMA

Message-security-assist extension 9 KDSA

Miscellaneous-instruction-extensions 1 CLT, CLGT, RISBGN

Miscellaneous-instruction-extensions 2 AGH, BIC, MG, MGH, MGRK, MSC, MSGC, MSGRKC, MSRKC, SGH

Miscellaneous-instruction-extensions 3 MVCRL, NCGRK, NCRK, NNGRK, NNRK, NOGRK, NORK, NXGRK, NXRK, OCGRK, OCRK, SELFHR, SELGR, SELR

Move-with-optional-specifications MVCOS

Parsing-enhancement TRTE, TRTRE

Perform-floating-point-operation PFPO

Population-count POPCNT

Processor-assist PPA

Reset-reference-bits-multiple RRBM

Store-clock fast STCKF

Store-facility-list extended STFLE

TOD-clock steering PTFF

Transactional-execution ETND, NTSTG, TABORT, TBEGIN, TEND

Test-pending-external-interruption TPEI


iv z/Architecture Reference Summary

For information about Enterprise Systems Architecture/390® (ESA/390™) architec-ture, refer to IBM Enterprise Systems Architecture/390 Principles of Operation, SA22-7201, and IBM Enterprise Systems Architecture/390 Reference Summary, SA22-7209.

Note: IBM, IBM Z, z/Architecture, eServer, zSeries, z Systems, Enterprise Systems Architecture/390, and ESA/390 are trademarks or registered trademarks of the Inter-national Business Machines Corporation in the United States, other countries, or both.

Vector-facility-for-z/Architecture LCBB, VA, VAC, VACC, VACCC, VAVG, VAVGL, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCKSM, VCLGD, VCLZ, VCTZ, VEC, VECL, VERIM, VERLL, VERLLV, VESL, VESLV, VESRA, VESRAV, VESRL, VESRLV, VFA, VFAE, VFCE, VFCH, VFCHE, VFD, VFEE, VFENE, VFI, VFLL, VFLR, VFM, VFMA, VFMS, VFPSO, VFS, VFSQ, VFTCI, VGBM, VGEF, VGEG, VGFM, VGFMA, VGM, VISTR, VL, VLBB, VLC, VLEB, VLEF, VLEG, VLEH, VLEIB, VLEIF, VLEIG, VLEIH, VLGV, VLL, VLLEZ, VLM, VLP, VLR, VLREP, VLVG, VLVGP, VMAE, VMAH, VMAL, VMALE, VMALH, VMALO, VMAO, VME, VMH, VML, VMLE, VMLH, VMLO, VMN, VMNL, VMO, VMRH, VMRL, VMX, VMXL, VN, VNC, VNO, VO, VPDI, VPERM, VPK, VPKLS, VPKS, VPOPCT, VREP, VREPI, VS, VSBCBI, VSBI, VSCBI, VSCEF, VSCEG, VSEG, VSEL, VSL, VSLB, VSLDB, VSRA, VSRAB, VSRL, VSRLB, VST, VSTEB, VSTEF, VSTEG, VSTEH, VSTL, VSTM, VSTRC, VSUM, VSUMG, VSUMQ, VTM, VUPH, VUPL, VUPLH, VUPLL, VX, WFC, WFK

Vector-enhancements facility 1 VBPERM, VFMAX, VFMIN, VFNMA, VFNMS, VMSL, VNN, VNX, VOC

Vector-enhancements facility 2 VLBR, VLBRREP, VLEBRF, VLEBRG, VLEBRH, VLER, VLLEBRZ, VSLD, VSRD, VSTBR, VSTEBRF, VSTEBRG, VSTEBRH, VSTER, VSTRS

Vector-packed-decimal VAP, VCP, VCVB, VCVBG, VCVD, VCVDG, VDP, VLIP, VMP, VMSP, VPKZ, VPSOP, VRP, VSDP, VSRP, VSP, VTP, VUPKZ, VLRLR, VLRL, VSTRLR, VSTRL


v

vi z/Architecture Reference Summary

Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiContents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiMachine Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Machine Instructions by Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Machine Instructions by Operation Code. . . . . . . . . . . . . . . . . . . . . . . . . 29Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Assembler Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

CNOP Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Extended-Mnemonic Instructions for Branch on Condition and

Branch Indirect on Condition . . . . . . . . . . . . . . . . . . . . . . . . . . 42Extended-Mnemonic Instructions for Relative-Branch Instructions 42Extended-Mnemonic Suffixes for Compare-and-Branch, and

Compare-and-Trap Instructions . . . . . . . . . . . . . . . . . . . . . . . . 43Extended-Mnemonic Suffixes for Load/Store-on-Condition

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Extended-Mnemonic Suffixes for Rotate-Then-Insert / AND / OR /

Exclusive OR-Selected-Bits Instructions . . . . . . . . . . . . . . . . . 43Extended-Mnemonics for Vector-Facility Instructions . . . . . . . . . . 44Summary of Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Assigned Storage Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45External-Interruption Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Program-Interruption Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Data-Exception Code (DXC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Vector-Exception Code (VXC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48PER Code, ATMID, and AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Translation-Exception Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Machine-Check Interruption Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

External-Damage Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Facility Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Floating-Point-Control (FPC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . 55Program-Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

z/Architecture PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Short-Format PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Dynamic Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Virtual-Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Address-Space-Control Element (ASCE) . . . . . . . . . . . . . . . . . . . 57Region-Table or Segment-Table Designation (RTD or STD) . . . . 57Real-Space Designation (RSD) . . . . . . . . . . . . . . . . . . . . . . . . . . 57Table Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Region-Table Entry (RTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Segment-Table Entry (STE, FC=0) . . . . . . . . . . . . . . . . . . . . . . . . 58Segment-Table Entry (STE, FC=1) . . . . . . . . . . . . . . . . . . . . . . . . 58Page-Table Entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ASN Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Address-Space Number (ASN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59ASN-First-Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59ASN-Second-Table Entry (ASTE) . . . . . . . . . . . . . . . . . . . . . . . . . 59

PC-Number Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Program-Call Number (20-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Program-Call Number (32-Bit, Bit 44=0) . . . . . . . . . . . . . . . . . . . . 60Program-Call Number (32-Bit, Bit 44=1) . . . . . . . . . . . . . . . . . . . . 60

vii

Linkage-Table Entry (LTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Linkage-First-Table Entry (LFTE) . . . . . . . . . . . . . . . . . . . . . . . . . 61Linkage-Second-Table Entry (LSTE) . . . . . . . . . . . . . . . . . . . . . . 61Entry-Table Entry (ETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Access-Register Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Access-List-Entry Token (ALET) . . . . . . . . . . . . . . . . . . . . . . . . . 62Dispatchable-Unit-Control Table (DUCT) . . . . . . . . . . . . . . . . . . . 62Access-List Entry (ALE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Linkage-Stack Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Entry Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Header Entry (Entry Type 0001001) . . . . . . . . . . . . . . . . . . . . . . . 64Trailer Entry (Entry Type 0001010) . . . . . . . . . . . . . . . . . . . . . . . 64Branch State Entry (Entry Type 0001100) and

Program-Call State Entry (Entry Type 0001101) . . . . . . . . . . . 64Trapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Trap Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Trap Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Trace-Entry Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Identification of Trace Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Branch in Subspace Group (if ASN Tracing on) . . . . . . . . . . . . . . 68Mode Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Mode-Switching Branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Program Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Program Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Program Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Set Secondary ASN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Operand of Store Clock and Store Clock Fast . . . . . . . . . . . . . . . . . . . . 73Operand of Store Clock Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Transaction Diagnostic Block (TDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Guarded-Storage Facility Registers and Parameters . . . . . . . . . . . . . . . 75

Guarded-Storage-Designation (GSD) Register . . . . . . . . . . . . . . 75Guarded-Storage Control Block. . . . . . . . . . . . . . . . . . . . . . . . . . . 75Guarded-Storage-Event Parameter List . . . . . . . . . . . . . . . . . . . . 75

Operation-Request Block (ORB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Command-Mode ORB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Transport-Mode ORB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Channel-Command Word (CCW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Format-0 CCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Format-1 CCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Indirect-Data-Address Word (IDAW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Format-1 IDAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Format-2 IDAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Modified-CCW-Indirect-Data-Address Word (MIDAW) . . . . . . . . . 78

Transport Control Word (TCW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Transport-Indirect-Data-Address Word (TIDAW) . . . . . . . . . . . . . 79

Transport Command Control Block (TCCB) . . . . . . . . . . . . . . . . . . . . . . 79Transport Command Area Header (TCAH) . . . . . . . . . . . . . . . . . 79Device-Command Word (DCW) . . . . . . . . . . . . . . . . . . . . . . . . . . 80Transport Command Area Trailer (TCAT) . . . . . . . . . . . . . . . . . . 81

CBC-Offset Block (COB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Transport Status Block (TSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Transport Status Header (TSH) . . . . . . . . . . . . . . . . . . . . . . . . . . 82

viii z/Architecture Reference Summary

I/O-Status TSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Device-Detected-Program-Check TSA . . . . . . . . . . . . . . . . . . . . . 83Interrogate TSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Subchannel-Information Block (SCHIB) . . . . . . . . . . . . . . . . . . . . . . . . . 85Path-Management-Control Word (PMCW) . . . . . . . . . . . . . . . . . . 85

Interruption-Response Block (IRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Command-Mode Subchannel-Status Word (SCSW) . . . . . . . . . . 86Transport-Mode Subchannel-Status Word (SCSW) . . . . . . . . . . . 87Extended-Status Word (ESW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Format-0 ESW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Format-0 ESW Word 0 (Subchannel Logout) . . . . . . . . . . . . . . . . 89Format-0 ESW Word 1 (Extended-Report Word) . . . . . . . . . . . . . 89Format-1 ESW Word 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Format-2 ESW Word 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Format-3 ESW Word 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Information Stored in ESW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Extended-Control Word (ECW) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Extended-Measurement Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Format 0 Measurement Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Format 1 Measurement Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Channel-Report Word (CRW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Error-Recovery Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Reporting Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

I/O Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Standard Command-Code Assignments

(CCW and DCW Bits 0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Standard Meanings of Bits of First Sense Byte . . . . . . . . . . . . . . . 93

Hexadecimal and Decimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . 94Powers of 2 and 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Character Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Control Character Representations . . . . . . . . . . . . . . . . . . . . . . 100Additional ISO-8 Control Character Representations . . . . . . . . . 100Formatting Character Representations . . . . . . . . . . . . . . . . . . . . 100Two-Character BSC Data Link Controls . . . . . . . . . . . . . . . . . . . 100Commonly Used Editing Pattern Characters . . . . . . . . . . . . . . . 100ANSI-Defined Printer Control Characters . . . . . . . . . . . . . . . . . . 101

ix

x z/Architecture Reference Summary

Machine Instruction Formats

E Op Code

0 15

I Op Code I

0 8 15

IE Op Code / / / / / / / / I1 I2

0 16 24 28 31

MII Op Code M1 RI2 RI3

0 8 12 24 47

RI-a Op Code R1 Op I2

0 8 12 16 31

RI-b Op Code R1 Op RI2

0 8 12 16 31

RI-c Op Code M1 Op RI2

0 8 12 16 31

RIE-a Op Code R1 / / / / I2 M3 / / / / Op Code

0 8 12 16 32 36 40 47

RIE-b Op Code R1 R2 RI4 M3 / / / / Op Code

0 8 12 16 32 36 40 47

RIE-c Op Code R1 M3 RI4 I2 Op Code

0 8 12 16 32 40 47

RIE-d Op Code R1 R3 I2 / / / / / / / / Op Code

0 8 12 16 32 40 47

RIE-e Op Code R1 R3 RI2 / / / / / / / / Op Code

0 8 12 16 32 40 47

RIE-f Op Code R1 R2 I3 I4 I5 Op Code

0 8 12 16 24 32 40 47

RIE-g Op Code R1 M3 I2 / / / / / / / / Op Code

0 8 12 16 32 40 47

RIL-a Op Code R1 Op I2

0 8 12 16 47

1

RIL-b Op Code R1 Op RI2

0 8 12 16 47

RIL-c Op Code M1 Op RI2

0 8 12 16 47

RIS Op Code R1 M3 B4 D4 I2 Op Code

0 8 12 16 20 32 40 47

RR Op Code R1 R2‡

0 8 12 15

RRD Op Code R1 / / / / R3 R2

0 16 20 24 28 31

RRE Op Code / / / / / / / / R1‡ R2‡

0 16 24 28 31

RRF-a,b Op Code R3 M4‡ R1 R2

0 16 20 24 28 31

RRF-c-e Op Code M3‡ M4‡ R1 R2

0 16 20 24 28 31

RRS Op Code R1 R2 B4 D4 M3 / / / / Op Code

0 8 12 16 20 32 36 40 47

RS-a Op Code R1 R3‡ B2 D2

0 8 12 16 20 31

RS-b Op Code R1 M3 B2 D2

0 8 12 16 20 31

RSI Op Code R1 R3 RI2

0 8 12 16 31

RSL-a Op Code L1 / / / / B2 D2 / / / / / / / / Op Code

0 8 12 16 20 32 40 47

RSL-b Op Code L1 B2 D2 / / / / / / / / Op Code

0 8 16 20 32 40 47

RSY-a Op Code R1 R3 B2 DL2 DH2 Op Code

0 8 12 16 20 32 40 47

2 z/Architecture Reference Summary

RSY-b Op Code R1 M3 B2 DL2 DH2 Op Code

0 8 12 16 20 32 40 47

RX-a Op Code R1 X2 B2 D2

0 8 12 16 20 31

RX-b Op Code M1 X2 B2 D2

0 8 12 16 20 31

RXE Op Code R1 X2 B2 D2 M3‡ / / / / Op Code

0 8 12 16 20 32 36 40 47

RXF Op Code R3 X2 B2 D2 R1 / / / / Op Code

0 8 12 16 20 32 36 40 47

RXY-a Op Code R1 X2 B2 DL2 DH2 Op Code

0 8 12 16 20 32 40 47

RXY-b Op Code M1 X2 B2 DL2 DH2 Op Code

0 8 12 16 20 32 40 47

S Op Code B2‡ D2‡

0 16 20 31

SI Op Code I2‡ B1 D1

0 8 16 20 31

SIL Op Code B1 D1 I2

0 16 20 32 47

SIY Op Code I2 B1 DL1 DH1 Op Code

0 8 16 20 32 40 47

SMI Op Code M1 / / / / B3 D3 RI2

0 8 12 16 20 32 47

SS-a Op Code L or L1 B1 D1 B2 D2

0 8 16 20 32 36 47

SS-b Op Code L1 L2 B1 D1 B2 D2

0 8 12 16 20 32 36 47

SS-c Op Code L1 I3 B1 D1 B2 D2

0 8 12 16 20 32 36 47

3

SS-d Op Code R1 R3 B1 D1 B2 D2

0 8 12 16 20 32 36 47

SS-e Op Code R1 R3 B2 D2 B4 D4

0 8 12 16 20 32 36 47

SS-f Op Code L2 B1 D1 B2 D2

0 8 16 20 32 36 47

SSE Op Code B1 D1 B2 D2

0 16 20 32 36 47

SSF Op Code R3 Op B1 D1 B2 D2

0 8 12 16 20 32 36 47

VRI-a Op Code V1 / / / / I2 M3‡ RXB Op Code

0 8 12 16 32 36 40 47

VRI-b Op Code V1 / / / / I2 I3 M4 RXB Op Code

0 8 12 16 24 32 36 40 47

VRI-c Op Code V1 V3 I2 M4 RXB Op Code

0 8 12 16 32 36 40 47

VRI-d Op Code V1 V2 V3 / / / / I4 M5‡ RXB Op Code

0 8 12 16 20 24 32 36 40 47

VRI-e Op Code V1 V2 I3 M5 M4 RXB Op Code

0 8 12 16 28 32 36 40 47

VRI-f Op Code V1 V2 V3 / / / / M5 I4 RXB Op Code

0 8 12 16 20 24 28 36 40 47

VRI-g Op Code V1 V2 I4 M5 I3 RXB Op Code

0 8 12 16 24 28 36 40 47

VRI-h Op Code V1 / / / / I2 I3 RXB Op Code

0 8 12 16 32 36 40 47

VRI-i Op Code V1 R2 / / / / / / / / M4 I3 RXB Op Code

0 8 12 16 24 28 36 40 47


VRR-a Op Code V1 V2 / / / / / / / / M5‡ M4‡ M3‡ RXB Op Code

0 8 12 16 24 28 32 36 40 47

VRR-b Op Code V1 V2 V3 / / / / M5‡ / / / / M4‡ RXB Op Code

0 8 12 16 20 24 28 32 36 40 47

VRR-c Op Code V1 V2 V3 / / / / M6‡ M5‡ M4‡ RXB Op Code

0 8 12 16 20 24 28 32 36 40 47

VRR-d Op Code V1 V2 V3 M5‡ M6‡ / / / / V4 RXB Op Code

0 8 12 16 20 24 28 32 36 40 47

VRR-e Op Code V1 V2 V3 M6‡ / / / / M5‡ V4 RXB Op Code

0 8 12 16 20 24 28 32 36 40 47

VRR-f Op Code V1 R2 R3 / / / / / / / / / / / / / / / / RXB Op Code

0 8 12 16 20 36 40 47

VRR-g Op Code / / / / V1 / / / / / / / / / / / / / / / / / / / / RXB Op Code

0 8 12 16 36 40 47

VRR-h Op Code / / / / V1 V2 / / / / M3 / / / / / / / / RXB Op Code

0 8 12 16 20 24 28 36 40 47

VRR-i Op Code R1 V2 / / / / / / / / M3 M4‡ / / / / RXB Op Code

0 8 12 16 24 28 36 40 47

VRS-a Op Code V1 V3 B2 D2 M4‡ RXB Op Code

0 8 12 16 20 32 36 40 47

VRS-b Op Code V1 R3 B2 D2 M4‡ RXB Op Code

0 8 12 16 20 32 36 40 47

VRS-c Op Code R1 V3 B2 D2 M4 RXB Op Code

0 8 12 16 20 32 36 40 47

VRS-d Op Code / / / / R3 B2 D2 V1 RXB Op Code

0 8 12 16 20 32 36 40 47

VRV Op Code V1 V2 B2 D2 M3‡ RXB Op Code

0 8 12 16 20 32 36 40 47

5

1, 2, 3, 4, 5, 6 Denotes association with first, second, third, fourth, fifth, or sixth operand

a, b, c, d, e, f Distinguishes among instances of the same basic instruction format

B1, B2, B3, B4 Base register designation fieldD1, D2, D3, D4 Displacement field (including DH and DL for long-displacement

forms)I, I2, I3, I4, I5 Immediate operand fieldL, L1, L2 Length fieldM1, M3, M4, M5, M6 Mask fieldR1, R2, R3 Register designation fieldRI2, RI3, RI4 Relative-immediate operand fieldRXB Most significant bits of vector registers designated by the V1, V2,

V3, V4 fields, respectivelyX2 Index register designation field‡ For certain instructions, this operand is not defined

VRX Op Code V1 X2 B2 D2 M3‡ RXB Op Code

0 8 12 16 20 32 36 40 47

VSI Op Code I3 B2 D2 V1 RXB Op Code

0 8 16 20 32 36 40 47


Machine Instructions by Mnemonic

Mne-monic Operands Name

For-mat

Op-code

Class&

NotesA R1,D2(X2,B2) Add (32) RX-a 5A cAD R1,D2(X2,B2) Add Normalized (LH) RX-a 6A ¤ cADB R1,D2(X2,B2) Add (LB) RXE ED1A ¤ cADBR R1,R2 Add (LB) RRE B31A ¤ cADR R1,R2 Add Normalized (LH) RR 2A ¤ cADTR R1,R2,R3 Add (LD) RRF-a B3D2 ¤ c TFADTRA R1,R2,R3,M4 Add (LD) RRF-a B3D2 ¤ c FAE R1,D2(X2,B2) Add Normalized (SH) RX-a 7A ¤ cAEB R1,D2(X2,B2) Add (SB) RXE ED0A ¤ cAEBR R1,R2 Add (SB) RRE B30A ¤ cAER R1,R2 Add Normalized (SH) RR 3A ¤ cAFI R1,I2 Add Immediate (32) RIL-a C29 c EIAG R1,D2(X2,B2) Add (64) RXY-a E308 c NAGF R1,D2(X2,B2) Add (6432) RXY-a E318 c NAGFI R1,I2 Add Immediate (6432) RIL-a C28 c EIAGFR R1,R2 Add (6432) RRE B918 c NAGH R1,D2(X2,B2) Add Halfword (6416) RXY-a E338 c MI2AGHI R1,I2 Add Halfword Immediate (6416) RI-a A7B c NAGHIK R1,R3,I2 Add Immediate (6416) RIE-d ECD9 c DOAGR R1,R2 Add (64) RRE B908 c NAGRK R1,R2,R3 Add (64) RRF-a B9E8 c DOAGSI D1(B1),I2 Add Immediate (648) SIY EB7A c GEAH R1,D2(X2,B2) Add Halfword (3216) RX-a 4A cAHHHR R1,R2,R3 Add High (32) RRF-a B9C8 c HWAHHLR R1,R2,R3 Add High (32) RRF-a B9D8 c HWAHI R1,I2 Add Halfword Immediate (3216) RI-a A7A cAHIK R1,R3,I2 Add Immediate (3216) RIE-d ECD8 c DOAHY R1,D2(X2,B2) Add Halfword (3216) RXY-a E37A c LDAIH R1,I2 Add Immediate High (32) RIL-a CC8 c HWAL R1,D2(X2,B2) Add Logical (32) RX-a 5E cALC R1,D2(X2,B2) Add Logical with Carry (32) RXY-a E398 c N3ALCG R1,D2(X2,B2) Add Logical with Carry (64) RXY-a E388 c NALCGR R1,R2 Add Logical with Carry (64) RRE B988 c NALCR R1,R2 Add Logical with Carry (32) RRE B998 c N3ALFI R1,I2 Add Logical Immediate (32) RIL-a C2B c EIALG R1,D2(X2,B2) Add Logical (64) RXY-a E30A c NALGF R1,D2(X2,B2) Add Logical (6432) RXY-a E31A c NALGFI R1,I2 Add Logical Immediate (6432) RIL-a C2A c EIALGFR R1,R2 Add Logical (6432) RRE B91A c NALGHSIK R1,R3,I2 Add Logical with Signed Immediate

(6416)RIE-d ECDB c DO

ALGR R1,R2 Add Logical (64) RRE B90A c NALGRK R1,R2,R3 Add Logical (64) RRF-a B9EA c DOALGSI D1(B1),I2 Add Logical with Signed Immediate (648) SIY EB7E c GEALHHHR R1,R2,R3 Add Logical High (32) RRF-a B9CA c HWALHHLR R1,R2,R3 Add Logical High (32) RRF-a B9DA c HWALHSIK R1,R3,I2 Add Logical with Signed Immediate

(3216)RIE-d ECDA c DO

ALR R1,R2 Add Logical (32) RR 1E cALRK R1,R2,R3 Add Logical (32) RRF-a B9FA c DOALSI D1(B1),I2 Add Logical with Signed Immediate (328) SIY EB6E c GEALSIH R1,I2 Add Logical with Signed Immediate High

(32)RIL-a CCA c HW

ALSIHN R1,I2 Add Logical with Signed Immediate High (32)

RIL-a CCB HW

ALY R1,D2(X2,B2) Add Logical (32) RXY-a E35E c LDAP D1(L1,B1),D2(L2,B2) Add Decimal SS-b FA ¤ cAR R1,R2 Add (32) RR 1A cARK R1,R2,R3 Add (32) RRF-a B9F8 c DO

7

ASI D1(B1),I2 Add Immediate (328) SIY EB6A c GEAU R1,D2(X2,B2) Add Unnormalized (SH) RX-a 7E ¤ cAUR R1,R2 Add Unnormalized (SH) RR 3E ¤ cAW R1,D2(X2,B2) Add Unnormalized (LH) RX-a 6E ¤ cAWR R1,R2 Add Unnormalized (LH) RR 2E ¤ cAXBR R1,R2 Add (EB) RRE B34A ¤ cAXR R1,R2 Add Normalized (EH) RR 36 ¤ cAXTR R1,R2,R3 Add (ED) RRF-a B3DA ¤ c TFAXTRA R1,R2,R3,M4 ADD (ED) RRF-a B3DA ¤ c FAY R1,D2(X2,B2) Add (32) RXY-a E35A c LDBAKR R1,R2 Branch and Stack RRE B240 ¤BAL R1,D2(X2,B2) Branch and Link RX-a 45 ¤BALR R1,R2 Branch and Link RR 05 ¤BAS R1,D2(X2,B2) Branch and Save RX-a 4D ¤BASR R1,R2 Branch and Save RR 0D ¤BASSM R1,R2 Branch and Save and Set Mode RR 0C ¤BC M1,D2(X2,B2) Branch on Condition RX-b 47 ¤BCR M1,R2 Branch on Condition RR 07 ¤BCT R1,D2(X2,B2) Branch on Count (32) RX-a 46 ¤BCTG R1,D2(X2,B2) Branch on Count (64) RXY-a E346 ¤ NBCTGR R1,R2 Branch on Count (64) RRE B946 ¤ NBCTR R1,R2 Branch on Count (32) RR 06 ¤ BIC M1,D2(X2,B2) Branch Indirect on Condition RXY-b E347 ¤ MI2BPP M1,RI2,D3(B3) Branch Prediction Preload SMI C7 ¤ EHBPRP M1,RI2,RI3 Branch Prediction Relative Preload MII C5 ¤ EHBRAS R1,RI2 Branch Relative and Save RI-b A75 ¤ BRASL R1,RI2 Branch Relative and Save Long RIL-b C05 ¤ N3BRC M1,RI2 Branch Relative on Condition RI-c A74 ¤ BRCL M1,RI2 Branch Relative on Condition Long RIL-c C04 ¤ N3BRCT R1,RI2 Branch Relative on Count (32) RI-b A76 ¤ BRCTG R1,RI2 Branch Relative on Count (64) RI-b A77 ¤ NBRCTH R1,RI2 Branch Relative on Count High (32) RIL-b CC6 ¤ HWBRXH R1,R3,RI2 Branch Relative on Index High (32) RSI 84 ¤ BRXHG R1,R3,RI2 Branch Relative on Index High (64) RIE-e EC44 ¤ NBRXLE R1,R3,RI2 Branch Relative on Index Low or Equal (32) RSI 85 ¤ BRXLG R1,R3,RI2 Branch Relative on Index Low or Equal (64) RIE-e EC45 ¤ NBSA R1,R2 Branch and Set Authority RRE B25A qBSG R1,R2 Branch in Subspace Group RRE B258 ¤ BSM R1,R2 Branch and Set Mode RR 0B ¤ BXH R1,R3,D2(B2) Branch on Index High (32) RS-a 86 ¤ BXHG R1,R3,D2(B2) Branch on Index High (64) RSY-a EB44 ¤ NBXLE R1,R3,D2(B2) Branch on Index Low or Equal (32) RS-a 87 ¤ BXLEG R1,R3,D2(B2) Branch on Index Low or Equal (64) RSY-a EB45 ¤ NC R1,D2(X2,B2) Compare (32) RX-a 59 cCD R1,D2(X2B2),M3 Compare (LH) RX-a 69 cCDB R1,D2(X2,B2) Compare (LB) RXE ED19 ¤ cCDBR R1,R2 Compare (LB) RRE B319 ¤ cCDFBR R1,R2 Convert from Fixed (LB32) RRE B395 ¤CDFBRA R1,M3,R2,M4 Convert from Fixed (LB32) RRF-e B395 ¤ FCDFR R1,R2 Convert from Fixed (LH32) RRE B3B5 ¤ CDFTR R1,M3,R2,M4 Convert from Fixed (LD32) RRE B951 ¤ FCDGBR R1,R2 Convert from Fixed (LB64) RRE B3A5 ¤ NCDGBRA R1,M3,R2,M4 Convert from Fixed (LB64) RRF-e B3A5 ¤ FCDGR R1,R2 Convert from Fixed (LH64) RRE B3C5 ¤ NCDGTR R1,R2 Convert from Fixed (LD64) RRE B3F1 ¤ TFCDGTRA R1,M3,R2,M4 Convert from Fixed (LD64) RRF-e B3F1 ¤ FCDLFBR R1,M3,R2,M4 Convert from Logical (LB32) RRF-e B391 ¤ FCDLFTR R1,M3,R2,M4 Convert from Logical (LD32) RRF-e B953 ¤ FCDLGBR R1,M3,R2,M4 Convert from Logical (LB64) RRF-e B3A1 ¤ FCDLGTR R1,M3,R2,M4 Convert from Logical (LD64) RRF-e B952 ¤ F


For-mat

Op-code

Class&

Notes


CDPT R1,D2(L2,B2),M3 Convert from Packed (To Long DFP) RSL-b EDAE PCCDR R1,R2 Compare (LH) RR 29 ¤ cCDS R1,R3,D2(B2) Compare Double and Swap (32) RS-a BB ¤ cCDSG R1,R3,D2(B2) Compare Double and Swap (64) RSY-a EB3E ¤ c NCDSTR R1,R2 Convert from Signed Packed (LD64) RRE B3F3 ¤ TFCDSY R1,R3,D2(B2) Compare Double and Swap (32) RSY-a EB31 ¤ c LDCDTR R1,R2 Compare (LD) RRE B3E4 ¤ c TFCDUTR R1,R2 Convert from Unsigned Packed (LD64) RRE B3F2 ¤ TFCDZT R1,D2(L2,B2),M3 Convert from Zoned (to long DFP) RSL-b EDAA ¤ ZFCE R1,D2(X2,B2) Compare (SH) RX-a 79 ¤ cCEB R1,D2(X2,B2) Compare (SB) RXE ED09 ¤ cCEBR R1,R2 Compare (SB) RRE B309 ¤ cCEDTR R1,R2 Compare Biased Exponent (LD) RRE B3F4 ¤ c TFCEFBR R1,R2 Convert from Fixed (SB32) RRE B394 ¤CEFBRA R1,M3,R2,M4 Convert from Fixed (SB32) RRF-e B394 ¤ FCEFR R1,R2 Convert from Fixed (SH32) RRE B3B4 ¤ CEGBR R1,R2 Convert from Fixed (SB64) RRE B3A4 ¤ NCEGBRA R1,M3,R2,M4 Convert from Fixed (SB64) RRF-e B3A4 ¤ FCEGR R1,R2 Convert from Fixed (SH64) RRE B3C4 ¤ NCELFBR R1,M3,R2,M4 Convert from Logical (SB32) RRF-e B390 ¤ FCELGBR R1,M3,R2,M4 Convert from Logical (SB64) RRF-e B3A0 ¤ FCER R1,R2 Compare (SH) RR 39 ¤ cCEXTR R1,R2 Compare Biased Exponent (ED) RRE B3FC ¤ c TFCFC D2(B2) Compare and Form Codeword S B21A i ¤ cCFDBR R1,M3,R2 Convert to Fixed (32LB) RRF-e B399 ¤ cCFDBRA R1,M3,R2,M4 Convert to Fixed (32LB) RRF-e B399 ¤ c F CFDR R1,M3,R2 Convert to Fixed (32LH) RRF-e B3B9 ¤ cCFDTR R1,M3,R2,M4 Convert to Fixed (32LD) RRF-e B941 ¤ c FCFEBR R1,M3,R2 Convert to Fixed (32SB) RRF-e B398 ¤ cCFEBRA R1,M3,R2,M4 Convert to Fixed (32SB) RRF-e B398 ¤ c FCFER R1,M3,R2 Convert to Fixed (32SH) RRF-e B3B8 ¤ cCFI R1,I2 Compare Immediate (32) RIL-a C2D c EICFXBR R1,M3,R2 Convert to Fixed (32EB) RRF-e B39A ¤ cCFXBRA R1,M3,R2,M4 Convert to Fixed (32EB) RRF-e B39A ¤ c FCFXR R1,M3,R2 Convert to Fixed (32EH) RRF-e B3BA ¤ cCFXTR R1,M3,R2,M4 Convert to Fixed (32ED) RRF-e B949 ¤ c FCG R1,D2(X2,B2) Compare (64) RXY-a E320 c NCGDBR R1,M3,R2 Convert to Fixed (64LB) RRF-e B3A9 ¤ c NCGDBRA R1,M3,R2,M4 Convert to Fixed (64LB) RRF-e B3A9 ¤ c FCGDR R1,M3,R2 Convert to Fixed (64LH) RRF-e B3C9 ¤ c NCGDTR R1,M3,R2 Convert to Fixed (64LD) RRF-e B3E1 ¤ c TFCGDTRA R1,M3,R2,M4 Convert to Fixed (64LD) RRF-e B3E1 ¤ c FCGEBR R1,M3,R2 Convert to Fixed (64SB) RRF-e B3A8 ¤ c NCGEBRA R1,M3,R2,M4 Convert to Fixed (64SB) RRF-e B3A8 ¤ c FCGER R1,M3,R2 Convert to Fixed (64SH) RRF-e B3C8 ¤ c NCGF R1,D2(X2,B2) Compare (6432) RXY-a E330 c NCGFI R1,I2 Compare Immediate (6432) RIL-a C2C c EICGFR R1,R2 Compare (6432) RRE B930 c NCGFRL R1,RI2 Compare Relative Long (6432) RIL-b C6C c GECGH R1,D2(X2,B2) Compare Halfword (6416) RXY-a E334 c GECGHI R1,I2 Compare Halfword Immediate (6416) RI-a A7F c NCGHRL R1,RI2 Compare Halfword Relative Long (6416) RIL-b C64 c GECGHSI D1(B1),I2 Compare Halfword Immediate (6416) SIL E558 c GECGIB R1,I2,M3,D4(B4) Compare Immediate and Branch (648) RIS ECFC ¤ GECGIJ R1,I2,M3,RI4 Compare Immediate and Branch Relative

(648)RIE-c EC7C ¤ GE

CGIT R1,I2,M3 Compare Immediate and Trap (6416) RIE-a EC70 GECGR R1,R2 Compare (64) RRE B920 c NCGRB R1,R2,M3,D4(B4) Compare and Branch (64) RRS ECE4 ¤ GECGRJ R1,R2,M3,RI4 Compare and Branch Relative (64) RIE-b EC64 ¤ GE


For-mat

Op-code

Class&

Notes

9

CGRL R1,RI2 Compare Relative Long (64) RIL-b C68 c GECGRT R1,R2,M3 Compare and Trap (64) RRF-c B960 GECGXBR R1,M3,R2 Convert to Fixed (64EB) RRF-e B3AA ¤ c NCGXBRA R1,M3,R2,M4 Convert to Fixed (64EB) RRF-e B3AA ¤ c FCGXR R1,M3,R2 Convert to Fixed (64EH) RRF-e B3CA ¤ c NCGXTR R1,M3,R2 Convert to Fixed (64ED) RRF-e B3E9 ¤ c TFCGXTRA R1,M3,R2,M4 Convert to Fixed (64ED) RRF-e B3E9 ¤ c FCH R1,D2(X2,B2) Compare Halfword (3216) RX-a 49 cCHF R1,D2(X2,B2) Compare High (32) RXY-a E3CD c HWCHHR R1,R2 Compare High (32) RRE B9CD c HWCHHSI D1(B1),I2 Compare Halfword Immediate (1616) SIL E554 c GECHI R1,I2 Compare Halfword Immediate (3216) RI-a A7E cCHLR R1,R2 Compare High (32) RRE B9DD c HWCHRL R1,RI2 Compare Halfword Relative Long (3216) RIL-b C65 c GECHSI D1(B1),I2 Compare Halfword Immediate (3216) SIL E55C c GECHY R1,D2(X2,B2) Compare Halfword (3216) RXY-a E379 c LDCIB R1,I2,M3,D4(B4) Compare Immediate and Branch (328) RIS ECFE ¤ GECIH R1,I2 Compare Immediate High (32) RIL-a CCD c HWCIJ R1,I2,M3,RI4 Compare Immediate and Branch Relative

(328)RIE-c EC7E ¤ GE

CIT R1,I2,M3 Compare Immediate and Trap (3216) RIE-a EC72 GECKSM R1,R2 Checksum RRE B241 ¤ cCL R1,D2(X2,B2) Compare Logical (32) RX-a 55 cCLC D1(L,B1),D2(B2) Compare Logical (character) SS-a D5 ¤ cCLCL R1,R2 Compare Logical Long RR 0F i cCLCLE R1,R3,D2(B2) Compare Logical Long Extended RS-a A9 ¤ cCLCLU R1,R3,D2(B2) Compare Logical Long Unicode RSY-a EB8F ¤ c E2CLFDBR R1,M3,R2,M4 Convert to Logical (32LB) RRF-e B39D ¤ c FCLFDTR R1,M3,R2,M4 Convert to Logical (32LD) RRF-e B943 ¤ c FCLFEBR R1,M3,R2,M4 Convert to Logical (32SB) RRF-e B39C ¤ c FCLFHSI D1(B1),I2 Compare Logical Immediate (3216) SIL E55D c GECLFI R1,I2 Compare Logical Immediate (32) RIL-a C2F c EICLFIT R1,I2,M3 Compare Logical Immediate and Trap

(3216)RIE-a EC73 GE

CLFXBR R1,M3,R2,M4 Convert to Logical (32EB) RRF-e B39E ¤ c FCLFXTR R1,M3,R2,M4 Convert to Logical (32ED) RRF-e B94B ¤ c FCLG R1,D2(X2,B2) Compare Logical (64) RXY-a E321 c NCLGDBR R1,M3,R2,M4 Convert to Logical (64LB) RRF-e B3AD ¤ c FCLGDTR R1,M3,R2,M4 Convert to Logical (64LD) RRF-e B942 ¤ c FCLGEBR R1,M3,R2,M4 Convert to Logical (64SB) RRF-e B3AC ¤ c FCLGF R1,D2(X2,B2) Compare Logical (6432) RXY-a E331 c NCLGFI R1,I2 Compare Logical Immediate (6432) RIL-a C2E c EICLGFR R1,R2 Compare Logical (6432) RRE B931 c NCLGFRL R1,RI2 Compare Logical Relative Long (6432) RIL-b C6E c GECLGHRL R1,RI2 Compare Logical Relative Long (6416) RIL-b C66 c GECLGHSI D1(B1),I2 Compare Logical Immediate (6416) SIL E559 c GECLGIB R1,I2,M3,D4(B4) Compare Logical Immediate and Branch

(648)RIS ECFD ¤ GE

CLGIJ R1,I2,M3,RI4 Compare Logical Immediate and Branch Relative (648)

RIE-c EC7D ¤ GE

CLGIT R1,I2,M3 Compare Logical Immediate and Trap (6416)

RIE-a EC71 GE

CLGR R1,R2 Compare Logical (64) RRE B921 c NCLGRB R1,R2,M3,D4(B4) Compare Logical and Branch (64) RRS ECE5 ¤ GECLGRJ R1,R2,M3,RI4 Compare Logical and Branch Relative (64) RIE-b EC65 ¤ GECLGRL R1,RI2 Compare Logical Relative Long (64) RIL-b C6A c GECLGRT R1,R2,M3 Compare Logical and Trap (64) RRF-c B961 GECLGT R1,M3,D2(B2) Compare Logical and Trap (64) RSY-b EB2B MI1CLGXBR R1,M3,R2,M4 Convert to Logical (64EB) RRF-e B3AE ¤ c FCLGXTR R1,M3,R2,M4 Convert to Logical (64ED) RRF-e B94A ¤ c FCLHF R1,D2(X2,B2) Compare Logical High (32) RXY-a E3CF c HW


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CLHHR R1,R2 Compare Logical High (32) RRE B9CF c HWCLHHSI D1(B1),I2 Compare Logical Immediate (1616) SIL E555 c GECLHLR R1,R2 Compare Logical High (32) RRE B9DF c HWCLHRL R1,RI2 Compare Logical Relative Long (3216) RIL-b C67 c GECLI D1(B1),I2 Compare Logical Immediate SI 95 cCLIB R1,I2,M3,D4(B4) Compare Logical Immediate and Branch

(328)RIS ECFF ¤ GE

CLIH R1,I2 Compare Logical Immediate High (32) RIL-a CCF c HWCLIJ R1,I2,M3,RI4 Compare Logical Immediate and Branch

Relative (328)RIE-c EC7F ¤ GE

CLIY D1(B1),I2 Compare Logical Immediate SIY EB55 c LDCLM R1,M3,D2(B2) Compare Logical Char. under Mask (low) RS-b BD cCLMH R1,M3,D2(B2) Compare Logical Char. under Mask (high) RSY-b EB20 c NCLMY R1,M3,D2(B2) Compare Logical Char. under Mask (low) RSY-b EB21 c LDCLR R1,R2 Compare Logical (32) RR 15 cCLRB R1,R2,M3,D4(B4) Compare Logical and Branch (32) RRS ECF7 ¤ GECLRJ R1,R2,M3,RI4 Compare Logical and Branch Relative (32) RIE-b EC77 ¤ GECLRL R1,RI2 Compare Logical Relative Long (32) RIL-b C6F c GECLRT R1,R2,M3 Compare Logical and Trap (32) RRF-c B973 GECLST R1,R2 Compare Logical String RRE B25D ¤ cCLT R1,M3,D2(B2) Compare Logical and Trap (32) RSY-b EB23 MI1CLY R1,D2(X2,B2) Compare Logical (32) RXY-a E355 c LDCMPSC R1,R2 Compression Call RRE B263 i ¤ cCP D1(L1,B1),D2(L2,B2) Compare Decimal SS-b F9 ¤ cCPDT R1,D2(L2,B2),M3 Convert to Packed (From Long DFP) RSL-b EDAC c PCCPSDR R1,R3,R2 Copy Sign (L) RRF-b B372 ¤ FSCPXT R1,D2(L2,B2),M3 Convert to Packed (From Extended DFP) RSL-b EDAD c PCCPYA R1,R2 Copy Access RRE B24D ¤ CR R1,R2 Compare (32) RR 19 cCRB R1,R2,M3,D4(B4) Compare and Branch (32) RRS ECF6 ¤ GECRDTE R1,R3,R2[,M4] Compare and Replace DAT Table Entry RRF-b B98F ED2

p cCRJ R1,R2,M3,RI4 Compare and Branch Relative (32) RIE-b EC76 ¤ GECRL R1,RI2 Compare Relative Long (32) RIL-b C6D c GECRT R1,R2,M3 Compare and Trap (32) RRF-c B972 GECS R1,R3,D2(B2) Compare and Swap (32) RS-a BA ¤ cCSCH Clear Subchannel S B230 p cCSDTR R1,R2,M4 Convert to Signed Packed (64LD) RRF-d B3E3 ¤ TFCSG R1,R3,D2(B2) Compare and Swap (64) RSY-a EB30 ¤ c NCSP R1,R2 Compare and Swap and Purge (32) RRE B250 p cCSPG R1,R2 Compare and Swap and Purge (64) RRE B98A p c DECSST D1(B1),D2(B2),R3 Compare and Swap and Store SSF C82 ¤ cCSXTR R1,R2,M4 Convert to Signed Packed (128ED) RRF-d B3EB ¤ TFCSY R1,R3,D2(B2) Compare and Swap (32) RSY-a EB14 ¤ c LDCU12 R1,R2[,M3] Convert UTF-8 to UTF-16 RRF-c B2A7 ¤ cCU14 R1,R2[,M3] Convert UTF-8 to UTF-32 RRF-c B9B0 ¤ c E3CU21 R1,R2[,M3] Convert UTF-16 to UTF-8 RRF-c B2A6 ¤ cCU24 R1,R2[,M3] Convert UTF-16 to UTF-32 RRF-c B9B1 ¤ c E3CU41 R1,R2 Convert UTF-32 to UTF-8 RRE B9B2 ¤ c E3CU42 R1,R2 Convert UTF-32 to UTF-16 RRE B9B3 ¤ c E3CUDTR R1,R2 Convert to Unsigned Packed (64LD) RRE B3E2 ¤ TFCUSE R1,R2 Compare until Substring Equal RRE B257 i cCUTFU R1,R2[,M3] Convert UTF-8 to Unicode RRF-c B2A7 ¤ cCUUTF R1,R2[,M3] Convert Unicode to UTF-8 RRF-c B2A6 ¤ cCUXTR R1,R2 Convert to Unsigned Packed (128ED) RRE B3EA ¤ TFCVB R1,D2(X2,B2) Convert to Binary (32) RX-a 4F ¤ CVBG R1,D2(X2,B2) Convert to Binary (64) RXY-a E30E ¤ NCVBY R1,D2(X2,B2) Convert to Binary (32) RXY-a E306 ¤ LDCVD R1,D2(X2,B2) Convert to Decimal (32) RX-a 4E ¤ CVDG R1,D2(X2,B2) Convert to Decimal (64) RXY-a E32E ¤ NCVDY R1,D2(X2,B2) Convert to Decimal (32) RXY-a E326 ¤ LD


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11

CXBR R1,R2 Compare (EB) RRE B349 ¤ cCXFBR R1,R2 Convert from Fixed (EB32) RRE B396 ¤ CXFBRA R1,M3,R2,M4 Convert from Fixed (EB32) RRF-e B396 ¤ FCXFR R1,R2 Convert from Fixed (EH32) RRE B3B6 ¤ CXFTR R1,M3,R2,M4 Convert from Fixed (ED32) RRE B959 ¤ FCXGBR R1,R2 Convert from Fixed (EB64) RRE B3A6 ¤ NCXGBRA R1,M3,R2,M4 Convert from Fixed (EB64) RRF-e B3A6 ¤ FCXGR R1,R2 Convert from Fixed (EH64) RRE B3C6 ¤ NCXGTR R1,R2 Convert from Fixed (ED64) RRE B3F9 ¤ TFCXGTRA R1,M3,R2,M4 Convert from Fixed (ED64) RRF-e B3F9 ¤ FCXLFBR R1,M3,R2,M4 Convert from Logical (EB32) RRF-e B392 ¤ FCXLFTR R1,M3,R2,M4 Convert from Logical (ED32) RRF-e B95B ¤ FCXLGBR R1,M3,R2,M4 Convert from Logical (EB64) RRF-e B3A2 ¤ FCXLGTR R1,M3,R2,M4 Convert from Logical (ED64) RRF-e B95A ¤ FCXPT R1,D2(L2,B2),M3 Convert from Packed (To Extended DFP) RSL-b EDAF PCCXR R1,R2 Compare (EH) RRE B369 ¤ cCXSTR R1,R2 Convert from Signed Packed (ED128) RRE B3FB ¤ TFCXTR R1,R2 Compare (ED) RRE B3EC ¤ c TFCXUTR R1,R2 Convert from Unsigned Packed (ED128) RRE B3FA ¤ TFCXZT R1,D2(L2,B2),M3 Convert from Zoned (to extended DFP) RSL-b EDAB ¤ ZFCY R1,D2(X2,B2) Compare (32) RXY-a E359 c LDCZDT R1,D2(L2,B2),M3 Convert to Zoned (from long DFP) RSL-b EDA8 ¤ ZFCZXT R1,D2(L2,B2),M3 Convert to Zoned (from extended DFP) RSL-b EDA9 ¤ ZFD R1,D2(X2,B2) Divide (3264) RX-a 5D ¤ DD R1,D2(X2,B2) Divide (LH) RX-a 6D ¤ DDB R1,D2(X2,B2) Divide (LB) RXE ED1D ¤ DDBR R1,R2 Divide (LB) RRE B31D ¤ DDR R1,R2 Divide (LH) RR 2D ¤ DDTR R1,R2,R3 Divide (LD) RRF-a B3D1 ¤ TFDDTRA R1,R2,R3,M4 Divide (LD) RRF-a B3D1 ¤ FDE R1,D2(X2,B2) Divide (SH) RX-a 7D ¤ DEB R1,D2(X2,B2) Divide (SB) RXE ED0D ¤ DEBR R1,R2 Divide (SB) RRE B30D ¤ DER R1,R2 Divide (SH) RR 3D ¤ DFLTCC R1,R2,R3 DEFLATE Conversion Call RRF-a B939 ¤ c GZDIDBR R1,R3,R2,M4 Divide to Integer (LB) RRF-b B35B ¤ cDIEBR R1,R3,R2,M4 Divide to Integer (SB) RRF-b B353 ¤ cDL R1,D2(X2,B2) Divide Logical (3264) RXY-a E397 ¤ N3DLG R1,D2(X2,B2) Divide Logical (64128) RXY-a E387 ¤ NDLGR R1,R2 Divide Logical (64128) RRE B987 ¤ NDLR R1,R2 Divide Logical (3264) RRE B997 ¤ N3DP D1(L1,B1),D2(L2,B2) Divide Decimal SS-b FD ¤ DR R1,R2 Divide (3264) RR 1D ¤ DSG R1,D2(X2,B2) Divide Single (64) RXY-a E30D ¤ NDSGF R1,D2(X2,B2) Divide Single (6432) RXY-a E31D ¤ NDSGFR R1,R2 Divide Single (6432) RRE B91D ¤ NDSGR R1,R2 Divide Single (64) RRE B90D ¤ NDXBR R1,R2 Divide (EB) RRE B34D ¤ DXR R1,R2 Divide (EH) RRE B22D ¤ DXTR R1,R2,R3 Divide (ED) RRF-a B3D9 ¤ TFDXTRA R1,R2,R3,M4 Divide (ED) RRF-a B3D9 ¤ FEAR R1,R2 Extract Access RRE B24F ECAG R1,R3,D2(B2) Extract CPU Attribute RSY-a EB4C ¤ GEECTG D1(B1),D2(B2),R3 Extract CPU Time SSF C81 ¤ ETED D1(L,B1),D2(B2) Edit SS-a DE ¤ cEDMK D1(L,B1),D2(B2) Edit and Mark SS-a DF ¤ cEEDTR R1,R2 Extract Biased Exponent (64LD) RRE B3E5 ¤ TFEEXTR R1,R2 Extract Biased Exponent (64ED) RRE B3ED ¤ TFEFPC R1 Extract FPC RRE B38C ¤ EPAIR R1 Extract Primary ASN and Instance RRE B99A q RA


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EPAR R1 Extract Primary ASN RRE B226 qEPSW R1,R2 Extract PSW RRE B98D ¤ N3EREG R1,R2 Extract Stacked Registers (32) RRE B249 ¤ EREGG R1,R2 Extract Stacked Registers (64) RRE B90E ¤ NESAIR R1 Extract Secondary ASN and Instance RRE B99B q RAESAR R1 Extract Secondary ASN RRE B227 qESDTR R1,R2 Extract Significance (64LD) RRE B3E7 ¤ TFESEA R1,R2 Extract and Set Extended Authority RRE B99D p NESTA R1,R2 Extract Stacked State RRE B24A ¤ cESXTR R1,R2 Extract Significance (64ED) RRE B3EF ¤ TFETND R1 Extract Transaction Nesting Depth RRE B2EC ¤ TXEX R1,D2(X2,B2) Execute RX-a 44 ¤ EXRL R1,RI2 Execute Relative Long RIL-b C60 ¤ XXFIDBR R1,M3,R2 Load FP Integer (LB) RRF-e B35F ¤ FIDBRA R1,M3,R2,M4 Load FP Integer (LB) RRF-e B35F ¤ FFIDR R1,R2 Load FP Integer (LH) RRE B37F ¤ FIDTR R1,M3,R2,M4 Load FP Integer (LD) RRF-e B3D7 ¤ TFFIEBR R1,M3,R2 Load FP Integer (SB) RRF-e B357 ¤ FIEBRA R1,M3,R2,M4 Load FP Integer (SB) RRF-e B357 ¤ FFIER R1,R2 Load FP Integer (SH) RRE B377 ¤ FIXBR R1,M3,R2 Load FP Integer (EB) RRF-e B347 ¤ FIXBRA R1,M3,R2,M4 Load FP Integer (EB) RRF-e B347 ¤ FFIXR R1,R2 Load FP Integer (EH) RRE B367 ¤ FIXTR R1,M3,R2,M4 Load FP Integer (ED) RRF-e B3DF ¤ TFFLOGR R1,R2 Find Leftmost One RRE B983 c EIHDR R1,R2 Halve (LH) RR 24 ¤ HER R1,R2 Halve (SH) RR 34 ¤ HSCH Halt Subchannel S B231 p cIAC R1 Insert Address Space Control RRE B224 q cIC R1,D2(X2,B2) Insert Character RX-a 43 ICM R1,M3,D2(B2) Insert Characters under Mask (low) RS-b BF cICMH R1,M3,D2(B2) Insert Characters under Mask (high) RSY-b EB80 c NICMY R1,M3,D2(B2) Insert Characters under Mask (low) RSY-b EB81 c LDICY R1,D2(X2,B2) Insert Character RXY-a E373 LDIDTE R1,R3,R2 Invalidate DAT Table Entry RRF-b B98E p u DEIEDTR R1,R3,R2 Insert Biased Exponent (LD64&LD) RRF-b B3F6 ¤ TFIEXTR R1,R3,R2 Insert Biased Exponent (ED64&ED) RRF-b B3FE ¤ TFIIHF R1,I2 Insert Immediate (high) RIL-a C08 EIIIHH R1,I2 Insert Immediate (high high) RI-a A50 NIIHL R1,I2 Insert Immediate (high low) RI-a A51 NIILF R1,I2 Insert Immediate (low) RIL-a C09 EIIILH R1,I2 Insert Immediate (low high) RI-a A52 NIILL R1,I2 Insert Immediate (low low) RI-a A53 NIPK Insert PSW Key S B20B qIPM R1 Insert Program Mask RRE B222IPTE R1,R2 Invalidate Page Table Entry RRF-a B221 pIRBM R1,R2 Insert Reference Bits Multiple RRE B2AC p IMISKE R1,R2 Insert Storage Key Extended RRE B229 pIVSK R1,R2 Insert Virtual Storage Key RRE B223 qKDB R1,D2(X2,B2) Compare and Signal (LB) RXE ED18 ¤ cKDBR R1,R2 Compare and Signal (LB) RRE B318 ¤ cKDSA R1,R2 Compute Digital Signature Authentication RRE B93A ¤ c M9KDTR R1,R2 Compare and Signal (LD) RRE B3E0 ¤ c TFKEB R1,D2(X2,B2) Compare and Signal (SB) RXE ED08 ¤ cKEBR R1,R2 Compare and Signal (SB) RRE B308 ¤ cKIMD R1,R2 Compute Intermediate Message Digest RRE B93E ¤ c MSKLMD R1,R2 Compute Last Message Digest RRE B93F ¤ c MSKM R1,R2 Cipher Message RRE B92E ¤ c MSKMA R1,R3,R2 Cipher Message with Authentication RRF-b B929 ¤ c M8KMAC R1,R2 Compute Message Authentication Code RRE B91E ¤ c MS


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13

KMC R1,R2 Cipher Message with Chaining RRE B92F ¤ c MSKMCTR R1,R3,R2 Cipher Message with Counter RRF-b B92D ¤ c M4KMF R1,R2 Cipher Message with Cipher Feedback RRE B92A ¤ c M4KMO R1,R2 Cipher Message with Output Feedback RRE B92B ¤ c M4KXBR R1,R2 Compare and Signal (EB) RRE B348 ¤ cKXTR R1,R2 Compare and Signal (ED) RRE B3E8 ¤ cTFL R1,D2(X2,B2) Load (32) RX-a 58 LA R1,D2(X2,B2) Load Address RX-a 41 LAA R1,R3,D2(B2) Load and Add (32) RSY-a EBF8 ¤ c IALAAG R1,R3,D2(B2) Load and Add (64) RSY-a EBE8 ¤ c IALAAL R1,R3,D2(B2) Load and Add Logical (32) RSY-a EBFA ¤ c IALAALG R1,R3,D2(B2) Load and Add Logical (64) RSY-a EBEA ¤ c IALAE R1,D2(X2,B2) Load Address Extended RX-a 51 ¤ LAEY R1,D2(X2,B2) Load Address Extended RXY-a E375 ¤ GELAM R1,R3,D2(B2) Load Access Multiple RS-a 9A ¤ LAMY R1,R3,D2(B2) Load Access Multiple RSY-a EB9A ¤ LDLAN R1,R3,D2(B2) Load and AND (32) RSY-a EBF4 ¤ c IALANG R1,R3,D2(B2) Load and AND (64) RSY-a EBE4 ¤ c IALAO R1,R3,D2(B2) Load and OR (32) RSY-a EBF6 ¤ c IALAOG R1,R3,D2(B2) Load and OR (64) RSY-a EBE6 ¤ c IALARL R1,RI2 Load Address Relative Long RIL-b C00 N3LASP D1(B1),D2(B2) Load Address Space Parameters SSE E500 p cLAT R1,D2(X2,B2) Load and Trap (32) RXY-a E39F LTLAX R1,R3,D2(B2) Load and Exclusive OR (32) RSY-a EBF7 ¤ c IALAXG R1,R3,D2(B2) Load and Exclusive OR (64) RSY-a EBE7 ¤ c IALAY R1,D2(X2,B2) Load Address RXY-a E371 LDLB R1,D2(X2,B2) Load Byte (328) RXY-a E376 LDLBH R1,D2(X2,B2) Load Byte High (328) RXY-a E3C0 HWLBR R1,R2 Load Byte (328) RRE B926 EILCBB R1,D2(X2,B2),M3 Load Count to Block Boundary RXE E727 ¤ c VFLCDBR R1,R2 Load Complement (LB) RRE B313 ¤ cLCDFR R1,R2 Load Complement (L) RRE B373 ¤ FSLCDR R1,R2 Load Complement (LH) RR 23 ¤ cLCEBR R1,R2 Load Complement (SB) RRE B303 ¤ cLCER R1,R2 Load Complement (SH) RR 33 ¤ cLCGFR R1,R2 Load Complement (6432) RRE B913 c NLCGR R1,R2 Load Complement (64) RRE B903 c NLCR R1,R2 Load Complement (32) RR 13 cLCTL R1,R3,D2(B2) Load Control (32) RS-a B7 pLCTLG R1,R3,D2(B2) Load Control (64) RSY-a EB2F p NLCXBR R1,R2 Load Complement (EB) RRE B343 ¤ cLCXR R1,R2 Load Complement (EH) RRE B363 ¤ cLD R1,D2(X2,B2) Load (L) RX-a 68 ¤ LDE R1,D2(X2,B2) Load Lengthened (LHSH) RXE ED24 ¤ LDEB R1,D2(X2,B2) Load Lengthened (LBSB) RXE ED04 ¤ LDEBR R1,R2 Load Lengthened (LBSB) RRE B304 ¤ LDER R1,R2 Load Lengthened (LHSH) RRE B324 ¤ LDETR R1,R2,M4 Load Lengthened (LDSD) RRF-d B3D4 ¤ TFLDGR R1,R2 Load FPR from GR (L64) RRE B3C1 ¤ FGLDR R1,R2 Load (L) RR 28 ¤ LDXBR R1,R2 Load Rounded (LBEB) RRE B345 ¤ LDXBRA R1,M3,R2,M4 Load Rounded (LBEB) RRF-e B345 ¤ FLDXR R1,R2 Load Rounded (LHEH) RR 25 ¤ LDXTR R1,M3,R2,M4 Load Rounded (LDED) RRF-e B3DD ¤ TFLDY R1,D2(X2,B2) Load (L) RXY-a ED65 ¤ LDLE R1,D2(X2,B2) Load (S) RX-a 78 ¤ LEDBR R1,R2 Load Rounded (SBLB) RRE B344 ¤ LEDBRA R1,M3,R2,M4 Load Rounded (SBLB) RRF-e B344 ¤ FLEDR R1,R2 Load Rounded (SHLH) RR 35 ¤ LEDTR R1,M3,R2,M4 Load Rounded (SDLD) RRF-e B3D5 ¤ TF


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LER R1,R2 Load (S) RR 38 ¤ LEXBR R1,R2 Load Rounded (SBEB) RRE B346 ¤ LEXBRA R1,M3,R2,M4 Load Rounded (SBEB) RRF-e B346 ¤ FLEXR R1,R2 Load Rounded (SHEH) RRE B366 ¤ LEY R1,D2(X2,B2) Load (S) RXY-a ED64 ¤ LDLFAS D2(B2) Load FPC and Signal S B2BD ¤ XFLFH R1,D2(X2,B2) Load High (32) RXY-a E3CA HWLFHAT R1,D2(X2,B2) Load and Trap (32H32) RXY-a E3C8 LTLFPC D2(B2) Load FPC S B29D ¤ LG R1,D2(X2,B2) Load (64) RXY-a E304 NLGAT R1,D2(X2,B2) Load and Trap (64) RXY-a E385 LTLGB R1,D2(X2,B2) Load Byte (648) RXY-a E377 LDLGBR R1,R2 Load Byte (648) RRE B906 EILGDR R1,R2 Load GR from FPR (64L) RRE B3CD ¤ FGLGF R1,D2(X2,B2) Load (6432) RXY-a E314 NLGFI R1,I2 Load Immediate (6432) RIL-a C01 EILGFR R1,R2 Load (6432) RRE B914 NLGFRL R1,RI2 Load Relative Long (6432) RIL-b C4C GELGG R1,D2(X2,B2) Load guarded (64) RXY-a E34C ¤ GFLGH R1,D2(X2,B2) Load Halfword (6416) RXY-a E315 NLGHI R1,I2 Load Halfword Immediate (6416) RI-a A79 NLGHR R1,R2 Load Halfword (6416) RRE B907 EILGHRL R1,RI2 Load Halfword Relative Long (6416) RIL-b C44 GELGR R1,R2 Load (64) RRE B904 NLGRL R1,RI2 Load Relative Long (64) RIL-b C48 GELGSC R1,D2(X2,B2) Load guarded storage controls RXY-a E34D ¤ GFLH R1,D2(X2,B2) Load Halfword (3216) RX-a 48 LHH R1,D2(X2,B2) Load Halfword High (3216) RXY-a E3C4 HWLHI R1,I2 Load Halfword Immediate (3216) RI-a A78 LHR R1,R2 Load Halfword (3216) RRE B927 EILHRL R1,RI2 Load Halfword Relative Long (3216) RIL-b C45 GELHY R1,D2(X2,B2) Load Halfword (3216) RXY-a E378 LDLLC R1,D2(X2,B2) Load Logical Character (328) RXY-a E394 EILLCH R1,D2(X2,B2) Load Logical Character High (328) RXY-a E3C2 HWLLCR R1,R2 Load Logical Character (328) RRE B994 EILLGC R1,D2(X2,B2) Load Logical Character (648) RXY-a E390 NLLGCR R1,R2 Load Logical Character (648) RRE B984 EILLGF R1,D2(X2,B2) Load Logical (6432) RXY-a E316 NLLGFAT R1,D2(X2,B2) Load and Trap (6432) RXY-a E39D LTLLGFR R1,R2 Load Logical (6432) RRE B916 NLLGFRL R1,RI2 Load Logical Relative Long (6432) RIL-b C4E GELLGFSG R1,D2(X2,B2) Load logical and shift guarded (6432) RXY-a E348 ¤ GFLLGH R1,D2(X2,B2) Load Logical Halfword (6416) RXY-a E391 NLLGHR R1,R2 Load Logical Halfword (6416) RRE B985 EILLGHRL R1,RI2 Load Logical Halfword Relative Long

(6416)RIL-b C46 GE

LLGT R1,D2(X2,B2) Load Logical Thirty One Bits (6431) RXY-a E317 NLLGTAT R1,D2(X2,B2) Load Logical Thirty One Bits and Trap

(6431)RXY-a E39C LT

LLGTR R1,R2 Load Logical Thirty One Bits (6431) RRE B917 NLLH R1,D2(X2,B2) Load Logical Halfword (3216) RXY-a E395 EILLHH R1,D2(X2,B2) Load Logical Halfword High (3216) RXY-a E3C6 HWLLHR R1,R2 Load Logical Halfword (3216) RRE B995 EILLHRL R1,RI2 Load Logical Halfword Relative Long

(3216)RIL-b C42 GE

LLIHF R1,I2 Load Logical Immediate (high) RIL-a C0E EILLIHH R1,I2 Load Logical Immediate (high high) RI-a A5C NLLIHL R1,I2 Load Logical Immediate (high low) RI-a A5D NLLILF R1,I2 Load Logical Immediate (low) RIL-a C0F EILLILH R1,I2 Load Logical Immediate (low high) RI-a A5E NLLILL R1,I2 Load Logical Immediate (low low) RI-a A5F N


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15

LLZRGF R1,D2(X2,B2) Load Logical and Zero Rightmost Byte (32) RXY-a E33A LZLM R1,R3,D2(B2) Load Multiple (32) RS-a 98 LMD R1,R3,D2(B2),D4(B4) Load Multiple Disjoint (6432&32) SS-e EF ¤ NLMG R1,R3,D2(B2) Load Multiple (64) RSY-a EB04 NLMH R1,R3,D2(B2) Load Multiple High RSY-a EB96 NLMY R1,R3,D2(B2) Load Multiple (32) RSY-a EB98 LDLNDBR R1,R2 Load Negative (LB) RRE B311 ¤ cLNDFR R1,R2 Load Negative (L) RRE B371 ¤ FSLNDR R1,R2 Load Negative (LH) RR 21 ¤ cLNEBR R1,R2 Load Negative (SB) RRE B301 ¤ cLNER R1,R2 Load Negative (SH) RR 31 ¤ cLNGFR R1,R2 Load Negative (6432) RRE B911 c NLNGR R1,R2 Load Negative (64) RRE B901 c NLNR R1,R2 Load Negative (32) RR 11 cLNXBR R1,R2 Load Negative (EB) RRE B341 ¤ cLNXR R1,R2 Load Negative (EH) RRE B361 ¤ cLOC R1,D2(B2),M3 Load on Condition (32) RSY-b EBF2 L1LOCFH R1,D2(B2),M3 Load High on Condition (32) RSY-b EBE0 L2LOCFHR R1,R2,M3 Load High on Condition (32) RRF-c B9E0 L2LOCG R1,D2(B2),M3 Load on Condition (64) RSY-b EBE2 L1LOCGHI R1,I2,M3 Load Halfword Immediate on Condition

(6416)RIE-g EC46 L2

LOCGR R1,R2,M3 Load on Condition (64) RRF-c B9E2 L1LOCHHI R1,I2,M3 Load Halfword High Immediate on Condi-

tion (3216)RIE-g EC4E L2

LOCHI R1,I2,M3 Load Halfword Immediate on Condition (3216)

RIE-g EC42 L2

LOCR R1,R2,M3 Load on Condition (32) RRF-c B9F2 L1LPD R3,D1(B1),D2(B2) Load Pair Disjoint (32) SSF C84 c IALPDBR R1,R2 Load Positive (LB) RRE B310 ¤ cLPDFR R1,R2 Load Positive (L) RRE B370 ¤ FSLPDG R3,D1(B1),D2(B2) Load Pair Disjoint (64) SSF C85 c IALPDR R1,R2 Load Positive (LH) RR 20 ¤ cLPEBR R1,R2 Load Positive (SB) RRE B300 ¤ cLPER R1,R2 Load Positive (SH) RR 30 ¤ cLPGFR R1,R2 Load Positive (6432) RRE B910 c NLPGR R1,R2 Load Positive (64) RRE B900 c NLPQ R1,D2(X2,B2) Load Pair from Quadword (64&64128) RXY-a E38F ¤ NLPR R1,R2 Load Positive (32) RR 10 cLPSW D2(B2) Load PSW SI 82 p nLPSWE D2(B2) Load PSW Extended S B2B2 p n NLPTEA R1,R3,R2,M4 Load Page-Table-Entry Address RRF-b B9AA p c D2LPXBR R1,R2 Load Positive (EB) RRE B340 ¤ cLPXR R1,R2 Load Positive (EH) RRE B360 ¤ cLR R1,R2 Load (32) RR 18 LRA R1,D2(X2,B2) Load Real Address (32) RX-a B1 p cLRAG R1,D2(X2,B2) Load Real Address (64) RXY-a E303 p c NLRAY R1,D2(X2,B2) Load Real Address (32) RXY-a E313 p c LDLRDR R1,R2 Load Rounded (LHEH) RR 25 ¤ LRER R1,R2 Load Rounded (SHLH) RR 35 ¤ LRL R1,RI2 Load Relative Long (32) RIL-b C4D GELRV R1,D2(X2,B2) Load Reversed (32) RXY-a E31E N3LRVG R1,D2(X2,B2) Load Reversed (64) RXY-a E30F NLRVGR R1,R2 Load Reversed (64) RRE B90F NLRVH R1,D2(X2,B2) Load Reversed (16) RXY-a E31F N3LRVR R1,R2 Load Reversed (32) RRE B91F N3LT R1,D2(X2,B2) Load and Test (32) RXY-a E312 c EILTDBR R1,R2 Load and Test (LB) RRE B312 ¤ cLTDR R1,R2 Load and Test (LH) RR 22 ¤ cLTDTR R1,R2 Load and Test (LD) RRE B3D6 ¤ c TFLTEBR R1,R2 Load and Test (SB) RRE B302 ¤ c


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LTER R1,R2 Load and Test (SH) RR 32 ¤ cLTG R1,D2(X2,B2) Load and Test (64) RXY-a E302 c EILTGF R1,D2(X2,B2) Load And Test (6432) RXY-a E332 c GELTGFR R1,R2 Load and Test (6432) RRE B912 c NLTGR R1,R2 Load and Test (64) RRE B902 c NLTR R1,R2 Load and Test (32) RR 12 cLTXBR R1,R2 Load and Test (EB) RRE B342 ¤ cLTXR R1,R2 Load and Test (EH) RRE B362 ¤ cLTXTR R1,R2 Load and Test (ED) RRE B3DE ¤ c TFLURA R1,R2 Load Using Real Address (32) RRE B24B pLURAG R1,R2 Load Using Real Address (64) RRE B905 p NLXD R1,D2(X2,B2) Load Lengthened (EHLH) RXE ED25 ¤ LXDB R1,D2(X2,B2) Load Lengthened (EBLB) RXE ED05 ¤ LXDBR R1,R2 Load Lengthened (EBLB) RRE B305 ¤ LXDR R1,R2 Load Lengthened (EHLH) RRE B325 ¤ LXDTR R1,R2,M4 Load Lengthened (EDLD) RRF-d B3DC ¤ TFLXE R1,D2(X2,B2) Load Lengthened (EHSH) RXE ED26 ¤ LXEB R1,D2(X2,B2) Load Lengthened (EBSB) RXE ED06 ¤ LXEBR R1,R2 Load Lengthened (EBSB) RRE B306 ¤ LXER R1,R2 Load Lengthened (EHSH) RRE B326 ¤ LXR R1,R2 Load (E) RRE B365 ¤ LY R1,D2(X2,B2) Load (32) RXY-a E358 LDLZDR R1 Load Zero (L) RRE B375 ¤ LZER R1 Load Zero (S) RRE B374 ¤ LZRF R1,D2(X2,B2) Load and Zero Rightmost Byte (32) RXY-a E33B LZLZRG R1,D2(X2,B2) Load and Zero Rightmost Byte (64) RXY-a E32A LZLZXR R1 Load Zero (E) RRE B376 ¤ M R1,D2(X2,B2) Multiply (6432) RX-a 5C MAD R1,R3,D2(X2,B2) Multiply and Add (LH) RXF ED3E ¤ HMMADB R1,R3,D2(X2,B2) Multiply and Add (LB) RXF ED1E ¤ MADBR R1,R3,R2 Multiply and Add (LB) RRD B31E ¤ MADR R1,R3,R2 Multiply and Add (LH) RRD B33E ¤ HMMAE R1,R3,D2(X2,B2) Multiply and Add (SH) RXF ED2E ¤ HMMAEB R1,R3,D2(X2,B2) Multiply and Add (SB) RXF ED0E ¤ MAEBR R1,R3,R2 Multiply and Add (SB) RRD B30E ¤ MAER R1,R3,R2 Multiply and Add (SH) RRD B32E ¤ HMMAY R1,R3,D2(X2,B2) Multiply and Add Unnormalized (EHLH) RXF ED3A ¤ UEMAYH R1,R3,D2(X2,B2) Multiply and Add Unnormalized (EHHLH) RXF ED3C ¤ UEMAYHR R1,R3,R2 Multiply and Add Unnormalized (EHHLH) RRD B33C ¤ UEMAYL R1,R3,D2(X2,B2) Multiply and Add Unnormalized (EHLLH) RXF ED38 ¤ UEMAYLR R1,R3,R2 Multiply and Add Unnormalized (EHLLH) RRD B338 ¤ UEMAYR R1,R3,R2 Multiply and Add Unnormalized (EHLH) RRD B33A ¤ UEMC D1(B1),I2 Monitor Call SI AF ¤ MD R1,D2(X2,B2) Multiply (LH) RX-a 6C ¤ MDB R1,D2(X2,B2) Multiply (LB) RXE ED1C ¤ MDBR R1,R2 Multiply (LB) RRE B31C ¤ MDE R1,D2(X2,B2) Multiply (LHSH) RX-a 7C ¤ MDEB R1,D2(X2,B2) Multiply (LBSB) RXE ED0C ¤ MDEBR R1,R2 Multiply (LBSB) RRE B30C ¤ MDER R1,R2 Multiply (LHSH) RR 3C ¤ MDR R1,R2 Multiply (LH) RR 2C ¤ MDTR R1,R2,R3 Multiply (LD) RRF-a B3D0 ¤ TFMDTRA R1,R2,R3,M4 Multiply (LD) RRF-a B3D0 ¤ FME R1,D2(X2,B2) Multiply (LHSH) RX-a 7C ¤ MEE R1,D2(X2,B2) Multiply (SH) RXE ED37 ¤ MEEB R1,D2(X2,B2) Multiply (SB) RXE ED17 ¤ MEEBR R1,R2 Multiply (SB) RRE B317 ¤ MEER R1,R2 Multiply (SH) RRE B337 ¤ MER R1,R2 Multiply (LHSH) RR 3C ¤ MFY R1,D2(X2,B2) Multiply (6432) RXY-a E35C GE


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Notes

17

MG R1,D2(X2,B2) Multiply (12864) RXY-a E384 MI2MGH R1,D2(X2,B2) Multiply Halfword(6416) RXY-a E33C MI2MGHI R1,I2 Multiply Halfword Immediate (6416) RI-a A7D NMGRK R1,R2,R3 Multiply (12864) RRF-a B9EC MI2MH R1,D2(X2,B2) Multiply Halfword (3216) RX-a 4C MHI R1,I2 Multiply Halfword Immediate (3216) RI-a A7C MHY R1,D2(X2,B2) Multiply Halfword (6416) RXY-a E37C GEML R1,D2(X2,B2) Multiply Logical (6432) RXY-a E396 N3MLG R1,D2(X2,B2) Multiply Logical (12864) RXY-a E386 NMLGR R1,R2 Multiply Logical (12864) RRE B986 NMLR R1,R2 Multiply Logical (6432) RRE B996 N3MP D1(L1,B1),D2(L2,B2) Multiply Decimal SS-b FC ¤ MR R1,R2 Multiply (6432) RR 1C MS R1,D2(X2,B2) Multiply Single (32) RX-a 71 MSC R1,D2(X2,B2) Multiply Single (32) RXY-a E353 c MI2MSCH D2(B2) Modify Subchannel S B232 p cMSD R1,R3,D2(X2,B2) Multiply and Subtract (LH) RXF ED3F ¤ HMMSDB R1,R3,D2(X2,B2) Multiply and Subtract (LB) RXF ED1F ¤ MSDBR R1,R3,R2 Multiply and Subtract (LB) RRD B31F ¤ MSDR R1,R3,R2 Multiply and Subtract (LH) RRD B33F ¤ HMMSE R1,R3,D2(X2,B2) Multiply and Subtract (SH) RXF ED2F ¤ HMMSEB R1,R3,D2(X2,B2) Multiply and Subtract (SB) RXF ED0F ¤ MSEBR R1,R3,R2 Multiply and Subtract (SB) RRD B30F ¤ MSER R1,R3,R2 Multiply and Subtract (SH) RRD B32F ¤ HMMSFI R1,I2 Multiply Single Immediate (32) RIL-a C21 GEMSG R1,D2(X2,B2) Multiply Single (64) RXY-a E30C NMSGC R1,D2(X2,B2) Multiply Single (64) RXY-a E383 c MI2MSGF R1,D2(X2,B2) Multiply Single (6432) RXY-a E31C NMSGFI R1,I2 Multiply Single Immediate (6432) RIL-a C20 GEMSGFR R1,R2 Multiply Single (6432) RRE B91C NMSGR R1,R2 Multiply Single (64) RRE B90C NMSGRKC R1,R2,R3 Multiply Single (64) RRF-a B9ED c MI2MSR R1,R2 Multiply Single (32) RRE B252 MSRKC R1,R2,R3 Multiply Single (32) RRF-a B9FD c MI2MSTA R1 Modify Stacked State RRE B247 ¤ MSY R1,D2(X2,B2) Multiply Single (32) RXY-a E351 LDMVC D1(L,B1),D2(B2) Move (character) SS-a D2 ¤ MVCDK D1(B1),D2(B2) Move with Destination Key SSE E50F qMVCIN D1(L,B1),D2(B2) Move Inverse SS-a E8 ¤ MVCK D1(R1,B1),D2(B2),R3 Move with Key SS-d D9 q cMVCL R1,R2 Move Long RR 0E i ¤ cMVCLE R1,R3,D2(B2) Move Long Extended RS-a A8 ¤ cMVCLU R1,R3,D2(B2) Move Long Unicode RSY-a EB8E ¤ c E2MVCOS D1(B1),D2(B2),R3 Move with Optional Specifications SSF C80 q c MOMVCP D1(R1,B1),D2(B2),R3 Move to Primary SS-d DA q cMVCRL D1(B1),D2(B2) Move Right to Left SSE E50A ¤ MI3MVCS D1(R1,B1),D2(B2),R3 Move to Secondary SS-d DB q cMVCSK D1(B1),D2(B2) Move with Source Key SSE E50E qMVGHI D1(B1),I2 Move (6416) SIL E548 GEMVHHI D1(B1),I2 Move (1616) SIL E544 GEMVHI D1(B1),I2 Move (3216) SIL E54C GEMVI D1(B1),I2 Move Immediate SI 92 MVIY D1(B1),I2 Move Immediate SIY EB52 LDMVN D1(L,B1),D2(B2) Move Numerics SS-a D1 ¤MVO D1(L1,B1),D2(L2,B2) Move with Offset SS-b F1 ¤MVPG R1,R2 Move Page RRE B254 q cMVST R1,R2 Move String RRE B255 ¤ cMVZ D1(L,B1),D2(B2) Move Zones SS-a D3 ¤MXBR R1,R2 Multiply (EB) RRE B34C ¤MXD R1,D2(X2,B2) Multiply (EHLH) RX-a 67 ¤


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MXDB R1,D2(X2,B2) Multiply (EBLB) RXE ED07 ¤MXDBR R1,R2 Multiply (EBLB) RRE B307 ¤MXDR R1,R2 Multiply (EHLH) RR 27 ¤MXR R1,R2 Multiply (EH) RR 26 ¤MXTR R1,R2,R3 Multiply (ED) RRF-a B3D8 ¤ TFMXTRA R1,R2,R3,M4 Multiply (ED) RRF-a B3D8 ¤ FMY R1,R3,D2(X2,B2) Multiply Unnormalized (EHLH) RXF ED3B ¤ UEMYH R1,R3,D2(X2,B2) Multiply Unnormalized (EHHLH) RXF ED3D ¤ UEMYHR R1,R3,R2 Multiply Unnormalized (EHHLH) RRD B33D ¤ UEMYL R1,R3,D2(X2,B2) Multiply Unnormalized (EHLLH) RXF ED39 ¤ UEMYLR R1,R3,R2 Multiply Unnormalized (EHLLH) RRD B339 ¤ UEMYR R1,R3,R2 Multiply Unnormalized (EHLH) RRD B33B ¤ UEN R1,D2(X2,B2) AND (32) RX-a 54 cNC D1(L,B1),D2(B2) AND (character) SS-a D4 ¤ cNCGRK R1,R2,R3 AND with Complement (64) RRF-a B9E5 c MI3NCRK R1,R2,R3 AND with Complement (32) RRF-a B9F5 c MI3NG R1,D2(X2,B2) AND (64) RXY-a E380 c NNGR R1,R2 AND (64) RRE B980 c NNGRK R1,R2,R3 AND (64) RRF-a B9E4 c DONI D1(B1),I2 AND Immediate SI 94 cNIAI I1,I2 Next Instruction Access Intent IE B2FA EHNIHF R1,I2 AND Immediate (high) RIL-a C0A c EINIHH R1,I2 AND Immediate (high high) RI-a A54 c NNIHL R1,I2 AND Immediate (high low) RI-a A55 c NNILF R1,I2 AND Immediate (low) RIL-a C0B c EINILH R1,I2 AND Immediate (low high) RI-a A56 c NNILL R1,I2 AND Immediate (low low) RI-a A57 c NNIY D1(B1),I2 AND Immediate SIY EB54 c LDNNGRK R1,R2,R3 NAND (64) RRF-a B964 c MI3NNRK R1,R2,R3 NAND (32) RRF-a B974 c MI3NOGRK R1,R2,R3 NOR (64) RRF-a B966 c MI3NORK R1,R2,R3 NOR (32) RRF-a B976 c MI3NR R1,R2 AND (32) RR 14 cNRK R1,R2,R3 AND (32) RRF-a B9F4 c DONTSTG R1,D2(X2,B2) Nontransactional Store (64) RXY-a E325 ¤ TXNXGRK R1,R2,R3 NOT Exclusive OR (64) RRF-a B967 c MI3NXRK R1,R2,R3 NOT Exclusive OR (32) RRF-a B977 c MI3NY R1,D2(X2,B2) AND (32) RXY-a E354 c LDO R1,D2(X2,B2) OR (32) RX-a 56 cOC D1(L,B1),D2(B2) OR (character) SS-a D6 ¤ cOCGRK R1,R2,R3 OR with Complement (64) RRF-a B965 c MI3OCRK R1,R2,R3 OR with Complement (32) RRF-a B975 c MI3OG R1,D2(X2,B2) OR (64) RXY-a E381 c NOGR R1,R2 OR (64) RRE B981 c NOGRK R1,R2,R3 OR (64) RRF-a B9E6 c DOOI D1(B1),I2 OR Immediate SI 96 cOIHF R1,I2 OR Immediate (high) RIL-a C0C c EIOIHH R1,I2 OR Immediate (high high) RI-a A58 c NOIHL R1,I2 OR Immediate (high low) RI-a A59 c NOILF R1,I2 OR Immediate (low) RIL-a C0D c EIOILH R1,I2 OR Immediate (low high) RI-a A5A c NOILL R1,I2 OR Immediate (low low) RI-a A5B c NOIY D1(B1),I2 OR Immediate SIY EB56 c LDOR R1,R2 OR (32) RR 16 cORK R1,R2,R3 OR (32) RRF-a B9F6 c DOOY R1,D2(X2,B2) OR (32) RXY-a E356 c LDPACK D1(L1,B1),D2(L2,B2) Pack SS-b F2 ¤ PALB Purge ALB RRE B248 pPC D2(B2) Program Call S B218 qPCC Perform Cryptographic Computation RRE B92C ¤ c M4


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19

PCKMO Perform Crypto. Key Mgmt. Operations RRE B928 M3PFD M1,D2(X2,B2) Prefetch Data RXY-b E336 ¤ GEPFDRL M1,RI2 Prefetch Data Relative Long RIL-c C62 ¤ GEPFMF R1,R2 Perform Frame Management Function RRE B9AF p ED1PFPO Perform Floating-Point Operation E 010A ¤ PFPGIN R1,R2 Page In RRE B22E p c ESPGOUT R1,R2 Page Out RRE B22F p c ESPKA D1(B1),D2(L2,B2) Pack ASCII SS-f E9 ¤ E2PKU D1(B1),D2(L2,B2) Pack Unicode SS-f E1 ¤ E2PLO R1,D2(B2),R3,D4(B4) Perform Locked Operation SS-e EE ¤ cPOPCNT R1,R2[,M3] Population Count RRF-c B9E1 c PKPPA R1,R2,M3 Perform Processor Assist RRF-c B2E8 PAPR Program Return E 0101 q nPRNO R1,R2 Perform Random Number Operation RRE B93C M5PT R1,R2 Program Transfer RRE B228 qPTF R1 Perform Topology Function RRE B9A2 c p CTPTFF Perform Timing-Facility Function E 0104 q cPTI R1,R2 Program Transfer with Instance RRE B99E q RAPTLB Purge TLB S B20D pQADTR R1,R3,R2,M4 Quantize (LD) RRF-b B3F5 ¤ TFQAXTR R1,R3,R2,M4 Quantize (ED) RRF-b B3FD ¤ TFRCHP Reset Channel Path S B23B p cRISBG R1,R2,I3,I4[,I5] Rotate then Insert Selected Bits (64) RIE-f EC55 c GERISBGN R1,R2,I3,I4[,I5] Rotate then Insert Selected Bits (64) RIE-f EC59 MI1RISBHG R1,I2,I3,I4[,I5] Rotate then Insert Selected Bits High (32) RIE-f EC5D HWRISBLG R1,I2,I3,I4[,I5] Rotate then Insert Selected Bits Low (32) RIE-f EC51 HWRLL R1,R3,D2(B2) Rotate Left Single Logical (32) RSY-a EB1D N3RLLG R1,R3,D2(B2) Rotate Left Single Logical (64) RSY-a EB1C NRNSBG R1,R2,I3,I4[,I5] Rotate then AND Selected Bits (64) RIE-f EC54 c GEROSBG R1,R2,I3,I4[,I5] Rotate then OR Selected Bits (64) RIE-f EC56 c GERP D2(B2) Resume Program S B277 q nRRBE R1,R2 Reset Reference Bit Extended RRE B22A p cRRBM R1,R2 Reset Reference Bits Multiple RRE B9AE p RBRRDTR R1,R3,R2,M4 Reround (LD) RRF-b B3F7 ¤ TFRRXTR R1,R3,R2,M4 Reround (ED) RRF-b B3FF ¤ TFRSCH Resume Subchannel S B238 p cRXSBG R1,R2,I3,I4[,I5] Rotate then Exclusive OR Selected Bits

(64)RIE-f EC57 c GE

S R1,D2(X2,B2) Subtract (32) RX-a 5B cSAC D2(B2) Set Address Space Control S B219 qSACF D2(B2) Set Address Space Control Fast S B279 qSAL Set Address Limit S B237 pSAM24 Set Addressing Mode (24) E 010C ¤ N3SAM31 Set Addressing Mode (31) E 010D ¤ N3SAM64 Set Addressing Mode (64) E 010E ¤ NSAR R1,R2 Set Access RRE B24E ¤ SCHM Set Channel Monitor S B23C pSCK D2(B2) Set Clock S B204 p cSCKC D2(B2) Set Clock Comparator S B206 pSCKPF Set Clock Programmable Field E 0107 pSD R1,D2(X2,B2) Subtract Normalized (LH) RX-a 6B ¤ cSDB R1,D2(X2,B2) Subtract (LB) RXE ED1B ¤ cSDBR R1,R2 Subtract (LB) RRE B31B ¤ cSDR R1,R2 Subtract Normalized (LH) RR 2B ¤ cSDTR R1,R2,R3 Subtract (LD) RRF-a B3D3 ¤ c TFSDTRA R1,R2,R3,M4 Subtract (LD) RRF-a B3D3 ¤ c FSE R1,D2(X2,B2) Subtract Normalized (SH) RX-a 7B ¤ cSEB R1,D2(X2,B2) Subtract (SB) RXE ED0B ¤ cSEBR R1,R2 Subtract (SB) RRE B30B ¤ cSELFHR R1,R2,R3,M4 Select High (32) RRF-a B9C0 MI3SELGR R1,R2,R3,M4 Select (64) RRF-a B9E3 MI3SELR R1,R2,R3,M4 Select (32) RRF-a B9F0 MI3


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SER R1,R2 Subtract Normalized (SH) RR 3B ¤ cSFASR R1 Set FPC and Signal RRE B385 ¤ XFSFPC R1 Set FPC RRE B384 ¤ SG R1,D2(X2,B2) Subtract (64) RXY-a E309 c NSGF R1,D2(X2,B2) Subtract (6432) RXY-a E319 c NSGFR R1,R2 Subtract (6432) RRE B919 c NSGH R1,D2(X2,B2) Subtract Halfword (6416) RXY-a E339 c MI2SGR R1,R2 Subtract (64) RRE B909 c NSGRK R1,R2,R3 Subtract (64) RRF-a B9E9 c DOSH R1,D2(X2,B2) Subtract Halfword (3216) RX-a 4B cSHHHR R1,R2,R3 Subtract High (32) RRF-a B9C9 c HWSHHLR R1,R2,R3 Subtract High (32) RRF-a B9D9 c HWSHY R1,D2(X2,B2) Subtract Halfword (3216) RXY-a E37B c LDSIE D2(B2) Start Interpretive Execution S B214 i pSIGP R1,R3,D2(B2) Signal Processor RS-a AE p cSL R1,D2(X2,B2) Subtract Logical (32) RX-a 5F cSLA R1,D2(B2) Shift Left Single (32) RS-a 8B cSLAG R1,R3,D2(B2) Shift Left Single (64) RSY-a EB0B c NSLAK R1,R3,D2(B2) Shift Left Single (32) RSY-a EBDD c DOSLB R1,D2(X2,B2) Subtract Logical with Borrow (32) RXY-a E399 c N3SLBG R1,D2(X2,B2) Subtract Logical with Borrow (64) RXY-a E389 c NSLBGR R1,R2 Subtract Logical with Borrow (64) RRE B989 c NSLBR R1,R2 Subtract Logical with Borrow (32) RRE B999 c N3SLDA R1,D2(B2) Shift Left Double (64) RS-a 8F cSLDL R1,D2(B2) Shift Left Double Logical (64) RS-a 8D SLDT R1,R3,D2(X2,B2) Shift Significand Left (LD) RXF ED40 ¤ TFSLFI R1,I2 Subtract Logical Immediate (32) RIL-a C25 c EISLG R1,D2(X2,B2) Subtract Logical (64) RXY-a E30B c NSLGF R1,D2(X2,B2) Subtract Logical (6432) RXY-a E31B c NSLGFI R1,I2 Subtract Logical Immediate (6432) RIL-a C24 c EISLGFR R1,R2 Subtract Logical (6432) RRE B91B c NSLGR R1,R2 Subtract Logical (64) RRE B90B c NSLGRK R1,R2,R3 Subtract Logical (64) RRF-a B9EB c DOSLHHHR R1,R2,R3 Subtract Logical High (32) RRF-a B9CB c HWSLHHLR R1,R2,R3 Subtract Logical High (32) RRF-a B9DB c HWSLL R1,D2(B2) Shift Left Single Logical (32) RS-a 89 SLLG R1,R3,D2(B2) Shift Left Single Logical (64) RSY-a EB0D NSLLK R1,R3,D2(B2) Shift Left Single Logical (32) RSY-a EBDF DOSLR R1,R2 Subtract Logical (32) RR 1F cSLRK R1,R2,R3 Subtract Logical (32) RRF-a B9FB c DOSLXT R1,R3,D2(X2,B2) Shift Significand Left (ED) RXF ED48 ¤ TFSLY R1,D2(X2,B2) Subtract Logical (32) RXY-a E35F c LDSP D1(L1,B1),D2(L2,B2) Subtract Decimal SS-b FB ¤ cSPKA D2(B2) Set PSW Key from Address S B20A qSPM R1 Set Program Mask RR 04 nSPT D2(B2) Set CPU Timer S B208 pSPX D2(B2) Set Prefix S B210 pSQD R1,D2(X2,B2) Square Root (LH) RXE ED35 ¤ SQDB R1,D2(X2,B2) Square Root (LB) RXE ED15 ¤ SQDBR R1,R2 Square Root (LB) RRE B315 ¤ SQDR R1,R2 Square Root (LH) RRE B244 ¤ SQE R1,D2(X2,B2) Square Root (SH) RXE ED34 ¤ SQEB R1,D2(X2,B2) Square Root (SB) RXE ED14 ¤ SQEBR R1,R2 Square Root (SB) RRE B314 ¤ SQER R1,R2 Square Root (SH) RRE B245 ¤ SQXBR R1,R2 Square Root (EB) RRE B316 ¤ SQXR R1,R2 Square Root (EH) RRE B336 ¤ SR R1,R2 Subtract (32) RR 1B cSRA R1,D2(B2) Shift Right Single (32) RS-a 8A cSRAG R1,R3,D2(B2) Shift Right Single (64) RSY-a EB0A c N


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SRAK R1,R3,D2(B2) Shift Right Single (32) RSY-a EBDC c DOSRDA R1,D2(B2) Shift Right Double (64) RS-a 8E cSRDL R1,D2(B2) Shift Right Double Logical (64) RS-a 8C SRDT R1,R3,D2(X2,B2) Shift Significand Right (LD) RXF ED41 ¤ TFSRK R1,R2,R3 Subtract (32) RRF-a B9F9 c DOSRL R1,D2(B2) Shift Right Single Logical (32) RS-a 88 SRLG R1,R3,D2(B2) Shift Right Single Logical (64) RSY-a EB0C NSRLK R1,R3,D2(B2) Shift Right Single Logical (32) RSY-a EBDE DOSRNM D2(B2) Set BFP Rounding Mode (2 bit) S B299 ¤ SRNMB D2(B2) Set BFP Rounding Mode (3 bit) S B2B8 ¤ FSRNMT D2(B2) Set DFP Rounding Mode S B2B9 ¤ TRSRP D1(L1,B1),D2(B2),I3 Shift and Round Decimal SS-c F0 ¤ cSRST R1,R2 Search String RRE B25E ¤ cSRSTU R1,R2 Search String Unicode RRE B9BE ¤ c E3SRXT R1,R3,D2(X2,B2) Shift Significand Right (ED) RXF ED49 ¤ TFSSAIR R1 Set Secondary ASN with Instance RRE B99F ¤ RASSAR R1 Set Secondary ASN RRE B225 ¤ SSCH D2(B2) Start Subchannel S B233 p cSSKE R1,R2[,M3] Set Storage Key Extended RRF-d B22B p cSSM D2(B2) Set System Mask SI 80 pST R1,D2(X2,B2) Store (32) RX-a 50 STAM R1,R3,D2(B2) Store Access Multiple RS-a 9B STAMY R1,R3,D2(B2) Store Access Multiple RSY-a EB9B LDSTAP D2(B2) Store CPU Address S B212 pSTC R1,D2(X2,B2) Store Character RX-a 42 STCH R1,D2(X2,B2) Store Character High (8) RXY-a E3C3 HWSTCK D2(B2) Store Clock S B205 ¤ cSTCKC D2(B2) Store Clock Comparator S B207 pSTCKE D2(B2) Store Clock Extended S B278 ¤ cSTCKF D2(B2) Store Clock Fast S B27C ¤ c SCSTCM R1,M3,D2(B2) Store Characters under Mask (low) RS-b BE STCMH R1,M3,D2(B2) Store Characters under Mask (high) RSY-b EB2C ¤ NSTCMY R1,M3,D2(B2) Store Characters under Mask (low) RSY-b EB2D LDSTCPS D2(B2) Store Channel Path Status S B23A pSTCRW D2(B2) Store Channel Report Word S B239 p cSTCTG R1,R3,D2(B2) Store Control (64) RSY-a EB25 p NSTCTL R1,R3,D2(B2) Store Control (32) RS-a B6 pSTCY R1,D2(X2,B2) Store Character RXY-a E372 LDSTD R1,D2(X2,B2) Store (L) RX-a 60 ¤ STDY R1,D2(X2,B2) Store (L) RXY-a ED67 ¤ LDSTE R1,D2(X2,B2) Store (S) RX-a 70 ¤ STEY R1,D2(X2,B2) Store (S) RXY-a ED66 ¤ LDSTFH R1,D2(X2,B2) Store High (32) RXY-a E3CB HWSTFL D2(B2) Store Facility List S B2B1 p N3STFLE D2(B2) Store Facility List Extended S B2B0 ¤ c FLSTFPC D2(B2) Store FPC S B29C ¤ STG R1,D2(X2,B2) Store (64) RXY-a E324 NSTGRL R1,RI2 Store Relative Long (64) RIL-b C4B GESTGSC R1,D2(X2,B2) Store guarded storage controls RXY-a E349 ¤ GFSTH R1,D2(X2,B2) Store Halfword (16) RX-a 40 STHH R1,D2(X2,B2) Store Halfword High (16) RXY-a E3C7 HWSTHRL R1,RI2 Store Halfword Relative Long (16) RIL-b C47 GESTHY R1,D2(X2,B2) Store Halfword (16) RXY-a E370 LDSTIDP D2(B2) Store CPU ID S B202 pSTM R1,R3,D2(B2) Store Multiple (32) RS-a 90 STMG R1,R3,D2(B2) Store Multiple (64) RSY-a EB24 NSTMH R1,R3,D2(B2) Store Multiple High (32) RSY-a EB26 NSTMY R1,R3,D2(B2) Store Multiple (32) RSY-a EB90 LDSTNSM D1(B1),I2 Store Then And System Mask SI AC pSTOC R1,D2(B2),M3 Store on Condition (32) RSY-b EBF3 L1


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STOCFH R1,D2(B2),M3 Store High on Condition (32) RSY-b EBE1 L2STOCG R1,D2(B2),M3 Store on Condition (64) RSY-b EBE3 L1STOSM D1(B1),I2 Store Then Or System Mask SI AD pSTPQ R1,D2(X2,B2) Store Pair to Quadword (64,64128) RXY-a E38E ¤ NSTPT D2(B2) Store CPU Timer S B209 pSTPX D2(B2) Store Prefix S B211 pSTRAG D1(B1),D2(B2) Store Real Address (64) SSE E502 p NSTRL R1,RI2 Store Relative Long (32) RIL-b C4F GESTRV R1,D2(X2,B2) Store Reversed (32) RXY-a E33E N3STRVG R1,D2(X2,B2) Store Reversed (64) RXY-a E32F NSTRVH R1,D2(X2,B2) Store Reversed (16) RXY-a E33F N3STSCH D2(B2) Store Subchannel S B234 p cSTSI D2(B2) Store System Information S B27D p cSTURA R1,R2 Store Using Real Address (32) RRE B246 pSTURG R1,R2 Store Using Real Address (64) RRE B925 p NSTY R1,D2(X2,B2) Store (32) RXY-a E350 LDSU R1,D2(X2,B2) Subtract Unnormalized (SH) RX-a 7F ¤ cSUR R1,R2 Subtract Unnormalized (SH) RR 3F ¤ cSVC I Supervisor Call I 0A ¤ SW R1,D2(X2,B2) Subtract Unnormalized (LH) RX-a 6F ¤ cSWR R1,R2 Subtract Unnormalized (LH) RR 2F ¤ cSXBR R1,D2 Subtract (EB) RRE B34B ¤ cSXR R1,D2 Subtract Normalized (EH) RR 37 ¤ cSXTR R1,R2,R3 Subtract (ED) RRF-a B3DB ¤ c TFSXTRA R1,R2,R3,M4 Subtract (ED) RRF-a B3DB ¤ c FSY R1,D2(X2,B2) Subtract (32) RXY-a E35B c LDTABORT D2(B2) Transaction Abort S B2FC ¤ TXTAM Test Addressing Mode E 010B ¤ c N3TAR R1,R2 Test Access RRE B24C ¤ cTB R1,R2 Test Block RRE B22C i p cTBDR R1,M3,R2 Convert HFP to BFP (LBLH) RRF-e B351 ¤ cTBEDR R1,M3,R2 Convert HFP to BFP (SBLH) RRF-e B350 ¤ cTBEGIN D1(B1),I2 Transaction Begin (nonconstrained) SIL E560 ¤ c TXTBEGINC D1(B1),I2 Transaction Begin (constrained) SIL E561 ¤ c CXTCDB R1,D2(X2,B2) Test Data Class (LB) RXE ED11 ¤ cTCEB R1,D2(X2,B2) Test Data Class (SB) RXE ED10 ¤ cTCXB R1,D2(X2,B2) Test Data Class (EB) RXE ED12 ¤ cTDCDT R1,D2(X2,B2) Test Data Class (LD) RXE ED54 ¤ TFTDCET R1,D2(X2,B2) Test Data Class (SD) RXE ED50 ¤ TFTDCXT R1,D2(X2,B2) Test Data Class (ED) RXE ED58 ¤ TFTDGDT R1,D2(X2,B2) Test Data Group (LD) RXE ED55 ¤ TFTDGET R1,D2(X2,B2) Test Data Group (SD) RXE ED51 ¤ TFTDGXT R1,D2(X2,B2) Test Data Group (ED) RXE ED59 ¤ TFTEND Transaction End S B2F8 ¤ c TXTHDER R1,R2 Convert BFP to HFP (LHSB) RRE B358 ¤ cTHDR R1,R2 Convert BFP to HFP (LHLB) RRE B359 ¤ cTM D1(B1),I2 Test under Mask SI 91 cTMH R1,I2 Test under Mask High RI-a A70 cTMHH R1,I2 Test under Mask (high high) RI-a A72 c NTMHL R1,I2 Test under Mask (high low) RI-a A73 c NTML R1,I2 Test under Mask Low RI-a A71 cTMLH R1,I2 Test under Mask (low high) RI-a A70 c NTMLL R1,I2 Test under Mask (low low) RI-a A71 c NTMY D1(B1),I2 Test under Mask SIY EB51 c LDTP D1(L1,B1) Test Decimal RSL EBC0 ¤ c E2TPEI R1,R2 Test Pending External Interruption RRE B9A1 p c TETPI D2(B2) Test Pending Interruption S B236 p cTPROT D1(B1),D2(B2) Test Protection SSE E501 p cTR D1(L,B1),D2(B2) Translate SS-a DC ¤ TRACE R1,R3,D2(B2) Trace (32) RS-a 99 p


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TRACG R1,R3,D2(B2) Trace (64) RSY-a EB0F p NTRAP2 Trap E 01FF ¤ TRAP4 D2(B2) Trap S B2FF ¤ TRE R1,R2 Translate Extended RRE B2A5 ¤ cTROO R1,R2[,M3] Translate One to One RRF-c B993 ¤ c E2TROT R1,R2[,M3] Translate One to Two RRF-c B992 ¤ c E2TRT D1(L,B1),D2(B2) Translate and Test SS-a DD ¤ cTRTE R1,R2[,M3] Translate and Test Extended RRF-c B9BF ¤ PETRTO R1,R2[,M3] Translate Two to One RRF-c B991 ¤ c E2TRTR D1(L,B1),D2(B2) Translate and Test Reverse SS-a D0 ¤ c E3TRTRE R1,R2[,M3] Translate and Test Reverse Extended RRF B9BD ¤ PETRTT R1,R2[,M3] Translate Two to Two RRF-c B990 ¤ c E2TS D2(B2) Test and Set SI 93 ¤ cTSCH D2(B2) Test Subchannel S B235 p cUNPK D1(L1,B1),D2(L2,B2) Unpack SS-b F3 ¤ UNPKA D1(L1,B1),D2(B2) Unpack ASCII SS-a EA ¤ c E2UNPKU D1(L1,B1),D2(B2) Unpack Unicode SS-a E2 ¤ c E2UPT Update Tree E 0102 i ¤ cVA V1,V2,V3,M4 Vector Add VRR-c E7F3 ¤ VFVAC V1,V2,V3,V4,M5 Vector Add With Carry VRR-d E7BB ¤ VFVACC V1,V2,V3,M4 Vector Add Compute Carry VRR-c E7F1 ¤ VFVACCC V1,V2,V3,V4,M5 Vector Add With Carry Compute Carry VRR-d E7B9 ¤ VFVAP V1,V2,V3,I4,M5 Vector Add Decimal VRI-f E671 ¤ c* VDVAVG V1,V2,V3,M4 Vector Average VRR-c E7F2 ¤ VFVAVGL V1,V2,V3,M4 Vector Average Logical VRR-c E7F0 ¤ VFVBPERM V1,V2,V3 Vector Bit Permute VRR-c E785 ¤ V1VCDG V1,V2,M3,M4,M5 Vector FP Convert from Fixed 64-bit VRR-a E7C3 ¤ VFVCDLG V1,V2,M3,M4,M5 Vector FP Convert from Logical 64-bit VRR-a E7C1 ¤ VFVCEQ V1,V2,V3,M4,M5 Vector Compare Equal VRR-b E7F8 ¤ c* VFVCFPL V1,V2,M3,M4,M5 Vector FP Convert from Logical VRR-a E7C1 ¤ V2VCFPS V1,V2,M3,M4,M5 Vector FP Convert from Fixed VRR-a E7C3 ¤ V2VCGD V1,V2,M3,M4,M5 Vector FP Convert to Fixed 64-bit VRR-a E7C2 ¤ VFVCH V1,V2,V3,M4,M5 Vector Compare High VRR-b E7FB ¤ c* VFVCHL V1,V2,V3,M4,M5 Vector Compare High Logical VRR-b E7F9 ¤ c* VFVCKSM V1,V2,V3 Vector Checksum VRR-c E766 ¤ VFVCLFP V1,V2,M3,M4,M5 Vector FP Convert to Logical VRR-a E7C0 ¤ V2VCLGD V1,V2,M3,M4,M5 Vector FP Convert to Logical 64-bit VRR-a E7C0 ¤ VFVCLZ V1,V2,M3 Vector Count Leading Zeros VRR-a E753 ¤ VFVCP V1,V2,M3 Vector Compare Decimal VRR-h E677 ¤ c VDVCSFP V1,V2,M3,M4,M5 Vector FP Convert to Fixed VRR-a E7C2 ¤ V2VCTZ V1,V2,M3 Vector Count Trailing Zeros VRR-a E752 ¤ VFVCVB R1,V2,M3 Vector Convert to Binary VRR-i E650 ¤ c* VDVCVBG R1,V2,M3 Vector Convert to Binary VRR-i E652 ¤ c* VDVCVD V1,R2,I3,M4 Vector Convert to Decimal VRI-i E658 ¤ c* VDVCVDG V1,R2,I3,M4 Vector Convert to Decimal VRI-i E65A ¤ c* VDVDP V1,V2,V3,I4,M5 Vector Divide Decimal VRI-f E67A ¤ c* VDVEC V1,V2,M3 Vector Element Compare VRR-a E7DB ¤ c VFVECL V1,V2,M3 Vector Element Compare Logical VRR-a E7D9 ¤ c VFVERIM V1,V2,V3,I4,M5 Vector Element Rotate and Insert Under

MaskVRI-d E772 ¤ VF

VERLL V1,V3,D2(B2),M4 Vector Element Rotate Left Logical VRS-a E733 ¤ VFVERLLV V1,V2,V3,M4 Vector Element Rotate Left Logical VRR-c E773 ¤ VFVESL V1,V3,D2(B2),M4 Vector Element Shift Left VRS-a E730 ¤ VFVESLV V1,V2,V3,M4 Vector Element Shift Left VRR-c E770 ¤ VFVESRA V1,V3,D2(B2),M4 Vector Element Shift Right Arithmetic VRS-a E73A ¤ VFVESRAV V1,V2,V3,M4 Vector Element Shift Right Arithmetic VRR-c E77A ¤ VFVESRL V1,V3,D2(B2),M4 Vector Element Shift Right Logical VRS-a E738 ¤ VFVESRLV V1,V2,V3,M4 Vector Element Shift Right Logical VRR-c E778 ¤ VFVFA V1,V2,V3,M4,M5 Vector FP Add VRR-c E7E3 ¤ VFVFAE V1,V2,V3,M4[,M5] Vector Find Any Element Equal VRR-b E782 ¤ c* VF


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VFCE V1,V2,V3,M4,M5,M6 Vector FP Compare Equal VRR-c E7E8 ¤ c* VFVFCH V1,V2,V3,M4,M5,M6 Vector FP Compare High VRR-c E7EB ¤ c* VFVFCHE V1,V2,V3,M4,M5,M6 Vector FP Compare High or Equal VRR-c E7EA ¤ c* VFVFD V1,V2,V3,M4,M5 Vector FP Divide VRR-c E7E5 ¤ VFVFEE V1,V2,V3,M4[,M5] Vector Find Element Equal VRR-b E780 ¤ c* VFVFENE V1,V2,V3,M4[,M5] Vector Find Element Not Equal VRR-b E781 ¤ c* VFVFI V1,V2,M3,M4,M5 Vector Load FP Integer VRR-a E7C7 ¤ VFVFLL V1,V2,M3,M4 Vector FP Load Lengthened VRR-a E7C4 ¤ VFVFLR V1,V2,M3,M4,M5 Vector FP Load Rounded VRR-a E7C5 ¤ VFVFM V1,V2,V3,M4,M5 Vector FP Multiply VRR-c E7E7 ¤ VFVFMA V1,V2,V3,V4,M5,M6 Vector FP Multiply and Add VRR-e E78F ¤ VFVFMAX V1,V2,V3,M4,M5,M6 Vector FP Maximum VRR-c E7EF ¤ V1VFMIN V1,V2,V3,M4,M5,M6 Vector FP Minimum VRR-c E7EE ¤ V1VFMS V1,V2,V3,V4,M5,M6 Vector FP Multiply and Subtract VRR-e E78E ¤ VFVFNMA V1,V2,V3,V4,M5,M6 Vector FP Negative Multiply and Add VRR-e E79F ¤ V1VFNMS V1,V2,V3,V4,M5,M6 Vector FP Negative Multiply and Subtract VRR-e E79E ¤ V1VFPSO V1,V2,M3,M4,M5 Vector FP Perform Sign Operation VRR-a E7CC ¤ VFVFS V1,V2,V3,M4,M5 Vector FP Subtract VRR-c E7E2 ¤ VFVFSQ V1,V2,M3,M4 Vector FP Square Root VRR-a E7CE ¤ VFVFTCI V1,V2,I3,M4,M5 Vector FP Test Data Class Immediate VRI-e E74A ¤ VFVGBM V1,I2 Vector Generate Byte Mask VRI-a E744 ¤ VFVGEF V1,D2(V2,B2),M3 Vector Gather Element (32) VRV E713 ¤ VFVGEG V1,D2(V2,B2),M3 Vector Gather Element (64) VRV E712 ¤ VFVGFM V1,V2,V3,M4 Vector Galois Field Multiply Sum VRR-c E7B4 ¤ VFVGFMA V1,V2,V3,V4,M5 Vector Galois Field Multiply Sum and Accu-

mulate VRR-d E7BC ¤ VF

VGM V1,I2,I3,V4 Vector Generate Mask VRI-b E746 ¤ VFVISTR V1,V2,M3[,M5] Vector Isolate String VRR-a E75C ¤ c* VFVL V1,D2(X2,B2) Vector Load VRX E706 ¤ VFVLBB V1,D2(X2,B2),M3 Vector Load to Block Boundary VRX E707 ¤ VFVLBR V1,D2(X2,B2),M3 Vector Load Byte Reversed Elements VRX E606 ¤ V2VLBRREP

V1,D2(X2,B2),M3 Vector Load Byte Reversed Element and Replicate

VRX E605 ¤ V2

VLC V1,V2,M3 Vector Load Complement VRR-a E7DE ¤ VFVLEB V1,D2(X2,B2),M3 Vector Load Element (8) VRX E700 ¤ VFVLEF V1,D2(X2,B2),M3 Vector Load Element (32) VRX E703 ¤ VFVLEG V1,D2(X2,B2),M3 Vector Load Element (64) VRX E702 ¤ VFVLEH V1,D2(X2,B2),M3 Vector Load Element (16) VRX E701 ¤ VFVLEIB V1,I2,M3 Vector Load Element Immediate (8) VRI-a E740 ¤ VFVLEIF V1,I2,M3 Vector Load Element Immediate (32) VRI-a E743 ¤ VFVLEIG V1,I2,M3 Vector Load Element Immediate (64) VRI-a E742 ¤ VFVLEIH V1,I2,M3 Vector Load Element Immediate (16) VRI-a E741 ¤ VFVLER V1,D2(X2,B2),M3 Vector Load Elements Reversed VRX E607 ¤ V2VLGV R1,V3,D2(B2),M4 Vector Load GR from VR Element VRS-c E721 ¤ VFVLIP V1,I2,I3 Vector Load Immediate Decimal VRI-h E649 ¤ VDVLL V1,R3,D2(B2) Vector Load With Length VRS-b E737 ¤ VFVLLEBRF V1,D2(X2,B2),M3 Vector Load Byte Reversed Element (32) VRX E603 ¤ V2VLLEBRG

V1,D2(X2,B2),M3 Vector Load Byte Reversed Element (64) VRX E602 ¤ V2

VLLEBRH

V1,D2(X2,B2),M3 Vector Load Byte Reversed Element (16) VRX E601 ¤ V2

VLLEBRZ V1,D2(X2,B2),M3 Vector Load Byte Reversed Element and Zero

VRX E604 ¤ V2

VLLEZ V1,D2(X2,B2),M3 Vector Load Logical Element and Zero VRX E704 ¤ VFVLM V1,V3,D2(B2) Vector Load Multiple VRS-a E736 ¤ VFVLP V1,V2,M3 Vector Load Positive VRR-a E7DF ¤ VFVLR V1,V2 Vector Load VRR-a E756 ¤ VFVLREP V1,D2(X2,B2),M3 Vector Load and Replicate VRX E705 ¤ VFVLRL V1,D2(B2),I3 Vector Load Rightmost with Length VSI E635 ¤ VDVLRLR V1,R3,D2(B2) Vector Load Rightmost with Length VRS-d E637 ¤ VDVLVG V1,R3,D2(B2),M4 Vector Load VR Element from GR VRS-b E722 ¤ VF


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Op-code

Class&

Notes

25

VLVGP V1,R2,R3 Vector Load VR from GRs Disjoint VRR-f E762 ¤ VFVMAE V1,V2,V3,V4,M5 Vector Multiply and Add Even VRR-d E7AE ¤ VFVMAH V1,V2,V3,V4,M5 Vector Multiply and Add High VRR-d E7AB ¤ VFVMAL V1,V2,V3,V4,M5 Vector Multiply and Add Low VRR-d E7AA ¤ VFVMALE V1,V2,V3,V4,M5 Vector Multiply and Add Logical Even VRR-d E7AC ¤ VFVMALH V1,V2,V3,V4,M5 Vector Multiply and Add Logical High VRR-d E7A9 ¤ VFVMALO V1,V2,V3,V4,M5 Vector Multiply and Add Logical Odd VRR-d E7AD ¤ VFVMAO V1,V2,V3,V4,M5 Vector Multiply and Add Odd VRR-d E7AF ¤ VFVME V1,V2,V3,M4 Vector Multiply Even VRR-c E7A6 ¤ VFVMH V1,V2,V3,M4 Vector Multiply High VRR-c E7A3 ¤ VFVML V1,V2,V3,M4 Vector Multiply Low VRR-c E7A2 ¤ VFVMLE V1,V2,V3,M4 Vector Multiply Logical Even VRR-c E7A4 ¤ VFVMLH V1,V2,V3,M4 Vector Multiply Logical High VRR-c E7A1 ¤ VFVMLO V1,V2,V3,M4 Vector Multiply Logical Odd VRR-c E7A5 ¤ VFVMN V1,V2,V3,M4 Vector Minimum VRR-c E7FE ¤ VFVMNL V1,V2,V3,M4 Vector Minimum Logical VRR-c E7FC ¤ VFVMO V1,V2,V3,M4 Vector Multiply Odd VRR-c E7A7 ¤ VFVMP V1,V2,V3,I4,M5 Vector Multiply Decimal VRI-f E678 ¤ c* VDVMRH V1,V2,V3,M4 Vector Merge High VRR-c E761 ¤ VFVMRL V1,V2,V3,M4 Vector Merge Low VRR-c E760 ¤ VFVMSL V1,V2,V3,V4,M5,M6 Vector Multiply Sum Logical VRR-d E6B8 ¤ V1VMSP V1,V2,V3,I4,M5 Vector Multiply and Shift Decimal VRI-f E679 ¤ c* VDVMX V1,V2,V3,M4 Vector Maximum VRR-c E7FF ¤ VFVMXL V1,V2,V3,M4 Vector Maximum Logical VRR-c E7FD ¤ VFVN V1,V2,V3 Vector AND VRR-c E768 ¤ VFVNC V1,V2,V3 Vector AND with Complement VRR-c E769 ¤ VFVNN V1,V2,V3 Vector NAND VRR-c E76E ¤ V1VNO V1,V2,V3 Vector NOR VRR-c E76B ¤ VFVNX V1,V2,V3 Vector Not Exclusive OR VRR-c E76C ¤ V1VO V1,V2,V3 Vector OR VRR-c E76A ¤ VFVOC V1,V2,V3 Vector OR with Complement VRR-c E76F ¤ V1VPDI V1,V2,V3,M4 Vector Permute Doubleword Immediate VRR-c E784 ¤ VFVPERM V1,V2,V3,V4 Vector Permute VRR-e E78C ¤ VFVPK V1,V2,V3,M4 Vector Pack VRR-c E794 ¤ VFVPKLS V1,V2,V3,M4,M5 Vector Pack Logical Saturate VRR-b E795 ¤ c* VFVPKS V1,V2,V3,M4,M5 Vector Pack Saturate VRR-b E797 ¤ c* VFVPKZ V1,D2(B2),I3 Vector Pack Zoned VSI E634 ¤ VDVPOPCT V1,V2,M3 Vector Population Count VRR-a E750 ¤ VFVPSOP V1,V2,I3,I4,M5 Vector Perform Sign Operation Decimal VRI-g E65B ¤ c* VDVREP V1,V3,I2,M4 Vector Replicate VRI-c E74D ¤ VFVREPI V1,I2,M3 Vector Replicate Immediate VRI-a E745 ¤ VFVRP V1,V2,V3,I4,M5 Vector Remainder Decimal VRI-f E67B ¤ c* VDVS V1,V2,V3,M4 Vector Subtract VRR-c E7F7 ¤ VFVSBCBI V1,V2,V3,V4,M5 Vector Subtract With Borrow Compute

Borrow IndicationVRR-d E7BD ¤ VF

VSBI V1,V2,V3,V4,M5 Vector Subtract With Borrow Indication VRR-d E7BF ¤ VFVSCBI V1,V2,V3,M4 Vector Subtract Compute Borrow Indication VRR-c E7F5 ¤ VFVSCEF V1,D2(V2,B2),M3 Vector Scatter Element (32) VRV E71B ¤ VFVSCEG V1,D2(V2,B2),M3 Vector Scatter Element (64) VRV E71A ¤ VFVSDP V1,V2,V3,I4,M5 Vector Shift and Divide Decimal VRI-f E67E ¤ c* VDVSEG V1,V2,M3 Vector Sign Extend to Doubleword VRR-a E75F ¤ VFVSEL V1,V2,V3,V4 Vector Select VRR-e E78D ¤ VFVSL V1,V2,V3 Vector Shift Left VRR-c E774 ¤ VFVSLB V1,V2,V3 Vector Shift Left By Byte VRR-c E775 ¤ VFVSLD V1,V2,V3,I4 Vector Shift Left Double by Bit VRI-d E786 ¤ V2VSLDB V1,V2,V3,I4 Vector Shift Left Double By Byte VRI-d E777 ¤ VFVSP V1,V2,V3,I4,M5 Vector Subtract Decimal VRI-f E673 ¤ c* VDVSRA V1,V2,V3 Vector Shift Right Arithmetic VRR-c E77E ¤ VFVSRAB V1,V2,V3 Vector Shift Right Arithmetic By Byte VRR-c E77F ¤ VFVSRD V1,V2,V3,I4 Vector Shift Right Double by Bit VRI-d E787 ¤ V2


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Op-code

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Notes


Floating-Point Operand Lengths and Types:

VSRL V1,V2,V3 Vector Shift Right Logical VRR-c E77C ¤ VFVSRLB V1,V2,V3 Vector Shift Right Logical By Byte VRR-c E77D ¤ VFVSRP V1,V2,I3,I4,M5 Vector Shift and Round Decimal VRI-g E659 ¤ c* VDVST V1,D2(X2,B2) Vector Store VRX E70E ¤ VFVSTBR V1,D2(X2,B2),M3 Vector Store Byte Reversed Elements VRX E60E ¤ V2VSTEB V1,D2(X2,B2),M3 Vector Store Element (8) VRX E708 ¤ VFVSTEBRF

V1,D2(X2,B2),M3 Vector Store Byte Reversed Element (32) VRX E60B ¤ V2

VSTEBRG

V1,D2(X2,B2),M3 Vector Store Byte Reversed Element (64) VRX E60A ¤ V2

VSTEBRH

V1,D2(X2,B2),M3 Vector Store Byte Reversed Element (16) VRX E609 ¤ V2

VSTEF V1,D2(X2,B2),M3 Vector Store Element (32) VRX E70B ¤ VFVSTEG V1,D2(X2,B2),M3 Vector Store Element (64) VRX E70A ¤ VFVSTEH V1,D2(X2,B2),M3 Vector Store Element (16) VRX E709 ¤ VFVSTER V1,D2(X2,B2),M3 Vector Store Elements Reversed VRX E60F ¤ V2VSTL V1,R3,D2(B2) Vector Store With Length VRS-b E73F ¤ VFVSTM V1,V3,D2(B2) Vector Store Multiple VRS-a E73E ¤ VFVSTRC V1,V2,V3,V4,M5[,M6] Vector String Range Compare VRR-d E78A ¤ c* VFVSTRL V1,D2(B2),I3 Vector Store Rightmost with Length VSI E63D ¤ VDVSTRLR V1,R3,D2(B2) Vector Store Rightmost with Length VRS-d E63F ¤ VDVSTRS V1,V2,V3,V4,M5[,M6] Vector String Search VRR-d E78B ¤ c V2VSUM V1,V2,V3,M4 Vector Sum Across Word VRR-c E764 ¤ VFVSUMG V1,V2,V3,M4 Vector Sum Across Doubleword VRR-c E765 ¤ VFVSUMQ V1,V2,V3,M4 Vector Sum Across Quadword VRR-c E767 ¤ VFVTM V1,V2 Vector Test Under Mask VRR-a E7D8 ¤ VFVTP V1 Vector Test Decimal VRR-g E65F ¤ c* VDVUPH V1,V2,M3 Vector Unpack High VRR-a E7D7 ¤ VFVUPKZ V1,D2(B2),I3 Vector Unpack Zoned VSI E63C ¤ VDVUPL V1,V2,M3 Vector Unpack Low VRR-a E7D6 ¤ VFVUPLH V1,V2,M3 Vector Unpack Logical High VRR-a E7D5 ¤ VFVUPLL V1,V2,M3 Vector Unpack Logical Low VRR-a E7D4 ¤ VFVX V1,V2,V3 Vector Exclusive OR VRR-c E76D ¤ VFWFC V1,V2,M3,M4 Vector FP Compare Scalar VRR-a E7CB ¤ VFWFK V1,V2,M3,M4 Vector FP Compare and Signal Scalar VRR-a E7CA ¤ VFX R1,D2(X2,B2) Exclusive OR (32) RX-a 57 cXC D1(L,B1),D2(B2) Exclusive OR (character) SS-a D7 ¤ cXG R1,D2(X2,B2) Exclusive OR (64) RXY-a E382 c NXGR R1,R2 Exclusive OR (64) RRE B982 c NXGRK R1,R2,R3 Exclusive OR (64) RRF-a B9E7 c DOXI D1(B1),I2 Exclusive OR Immediate SI 97 cXIHF R1,I2 Exclusive OR Immediate (high) RIL-a C06 c EIXILF R1,I2 Exclusive OR Immediate (low) RIL-a C07 c EIXIY D1(B1),I2 Exclusive OR Immediate SIY EB57 c LDXR R1,R2 Exclusive OR (32) RR 17 cXRK R1,R2,R3 Exclusive OR (32) RRF-a B9F7 c DOXSCH Cancel Subchannel S B276 p cXY R1,D2(X2,B2) Exclusive Or (32) RXY-a E357 c LDZAP D1(L1,B1),D2(L2,B2) Zero and Add SS-b F8 ¤ c


For-mat

Op-code

Class&

Notes

E Extended (binary, decimal or hex)EB Extended binaryED Extended decimalEH Extended hexEHL Extended hex (low-order part)EHH Extended hex (high-order part)L Long (binary, decimal or hex)

LB Long binaryLD Long decimalLH Long hexS Short (binary, decimal or hex)SB Short binarySD Short decimalSH Short hex

27

Notes:

& Combination of fields¤ One or more restrictions apply in the

transactional-execution modec Condition code setc* Condition code may be set based on

control in the instructioni Interruptible instructionn New condition code loadedp Privileged instruction; restricted in the

transactional-execution modeq Semiprivileged instruction; restricted in

the transactional-execution modeu Condition code is unpredictableCS Compare-and-swap-and-store facilityCT Configuration topology facilityCX Constrained-transactional-execution

facilityD2 DAT-enhancement facility 2DE DAT-enhancement facilityDO Distinct-operands facilityE2 Extended-translation facility 2E3 Extended-translation facility 3ED1 Enhanced-DAT facility 1ED2 Enhanced-DAT facility 2EH Execution-hint facilityEI Extended-immediate facilityES Expanded-storage facilityET Extract-CPU-time facilityF Floating-point-extension facilityFG FPR-GPR-transfer facilityFL Store-facility-list-extended facilityFS Floating-point-support-sign-handling

facilityGE General-instructions-extension facilityGF Guarded-storage facilityGZ DEFLATE-conversion facilityHM HFP multiply-and-add/subtract facilityHW High-word facilityIA Interlocked-access facility

IM Insert-reference-bits-multiple facilityL1 Load/store-on-condition facility 1L2 Load/store-on-condition facility 2LD Long-displacement facilityLT Load-and-trap facilityLZ Load-and-zero-rightmost-byte facilityM3 Message-security assist extension 3M4 Message-security assist extension 4M5 Message-security assist extension 5M8 Message-security assist extension 8M9 Message-security assist extension 9MI1 Miscellaneous-instructions facility 1MI2 Miscellaneous-instructions facility 2MI3 Miscellaneous-instructions facility 3MO Move-with-optional-specifications

facilityMS Message-security assistN New in z/ArchitectureN3 New in z/Architecture and added to

ESA/390PA Processor-assist facilityPC DFP-packed-conversion facilityPE Parsing-enhancement facilityPF PFPO facilityPK Population-count facilityRA ASN-and-LX-reuse facilityRB Reset-reference-bits multiple facilitySC Store-clock-fast facilityTE Test-pending-external-interruption

facilityTF Decimal-floating-point facilityTR Decimal-floating-point-rounding facilityTS TOD-clock-steering facilityTX Transactional-execution facilityUE HFP unnormalized-extension facilityVD Vector-packed-decimal facility VF Vector facility for z/ArchitectureV1 Vector-enhancements facility 1V2 Vector-enhancements facility 2XF IEEE-exception-support facility


Machine Instructions by Operation Code

OpCode Mnemonic0101 PR0102 UPT0104 PTFF0107 SCKPF010A PFPO010B TAM010C SAM24010D SAM31010E SAM6401FF TRAP204 SPM05 BALR06 BCTR07 BCR0A SVC0B BSM0C BASSM0D BASR0E MVCL0F CLCL10 LPR11 LNR12 LTR13 LCR14 NR15 CLR16 OR17 XR18 LR19 CR1A AR1B SR1C MR1D DR1E ALR1F SLR20 LPDR21 LNDR22 LTDR23 LCDR24 HDR25 LDXR25 LRDR26 MXR27 MXDR28 LDR29 CDR2A ADR2B SDR2C MDR2D DDR2E AWR2F SWR30 LPER31 LNER32 LTER33 LCER34 HER35 LEDR35 LRER36 AXR37 SXR38 LER39 CER3A AER3B SER3C MDER3C MER3D DER3E AUR3F SUR40 STH

41 LA42 STC43 IC44 EX45 BAL46 BCT47 BC48 LH49 CH4A AH4B SH4C MH4D BAS4E CVD4F CVB50 ST51 LAE54 N55 CL56 O57 X58 L59 C5A A5B S5C M5D D5E AL5F SL60 STD67 MXD68 LD69 CD6A AD6B SD6C MD6D DD6E AW6F SW70 STE71 MS78 LE79 CE7A AE7B SE7C MDE7C ME7D DE7E AU7F SU80 SSM82 LPSW83 Diagnose84 BRXH85 BRXLE86 BXH87 BXLE88 SRL89 SLL8A SRA8B SLA8C SRDL8D SLDL8E SRDA8F SLDA90 STM91 TM92 MVI93 TS94 NI95 CLI96 OI

OpCode Mnemonic97 XI98 LM99 TRACE9A LAM9B STAMA50 IIHHA51 IIHLA52 IILHA53 IILLA54 NIHHA55 NIHLA56 NILHA57 NILLA58 OIHHA59 OIHLA5A OILHA5B OILLA5C LLIHHA5D LLIHLA5E LLILHA5F LLILLA70 TMHA70 TMLHA71 TMLA71 TMLLA72 TMHHA73 TMHLA74 BRCA75 BRASA76 BRCTA77 BRCTGA78 LHIA79 LGHIA7A AHIA7B AGHIA7C MHIA7D MGHIA7E CHIA7F CGHIA8 MVCLEA9 CLCLEAC STNSMAD STOSMAE SIGPAF MCB1 LRAB202 STIDPB204 SCKB205 STCKB206 SCKCB207 STCKCB208 SPTB209 STPTB20A SPKAB20B IPKB20D PTLBB210 SPXB211 STPXB212 STAPB214 SIEB218 PCB219 SACB21A CFCB221 IPTEB222 IPMB223 IVSKB224 IACB225 SSARB226 EPARB227 ESARB228 PTB229 ISKE

OpCode Mnemonic

29

B22A RRBEB22B SSKEB22C TBB22D DXRB22E PGINB22F PGOUTB230 CSCHB231 HSCHB232 MSCHB233 SSCHB234 STSCHB235 TSCHB236 TPIB237 SALB238 RSCHB239 STCRWB23A STCPSB23B RCHPB23C SCHMB240 BAKRB241 CKSMB244 SQDRB245 SQERB246 STURAB247 MSTAB248 PALBB249 EREGB24A ESTAB24B LURAB24C TARB24D CPYAB24E SARB24F EARB250 CSPB252 MSRB254 MVPGB255 MVSTB257 CUSEB258 BSGB25A BSAB25D CLSTB25E SRSTB263 CMPSCB276 XSCHB277 RPB278 STCKEB279 SACFB27C STCKFB27D STSIB299 SRNMB29C STFPCB29D LFPCB2A5 TREB2A6 CU21B2A6 CUUTFB2A7 CU12B2A7 CUTFUB2B0 STFLEB2B1 STFLB2B2 LPSWEB2B8 SRNMBB2B9 SRNMTB2BD LFASB2E8 PPAB2EC ETNDB2F8 TENDB2FA NIAIB2FC TABORTB2FF TRAP4B300 LPEBRB301 LNEBRB302 LTEBRB303 LCEBRB304 LDEBRB305 LXDBRB306 LXEBR

OpCode MnemonicB307 MXDBRB308 KEBRB309 CEBRB30A AEBRB30B SEBRB30C MDEBRB30D DEBRB30E MAEBRB30F MSEBRB310 LPDBRB311 LNDBRB312 LTDBRB313 LCDBRB314 SQEBRB315 SQDBRB316 SQXBRB317 MEEBRB318 KDBRB319 CDBRB31A ADBRB31B SDBRB31C MDBRB31D DDBRB31E MADBRB31F MSDBRB324 LDERB325 LXDRB326 LXERB32E MAERB32F MSERB336 SQXRB337 MEERB338 MAYLRB339 MYLRB33A MAYRB33B MYRB33C MAYHRB33D MYHRB33E MADRB33F MSDRB340 LPXBRB341 LNXBRB342 LTXBRB343 LCXBRB344 LEDBRB344 LEDBRAB345 LDXBRB345 LDXBRAB346 LEXBRB346 LEXBRAB347 FIXBRB347 FIXBRAB348 KXBRB349 CXBRB34A AXBRB34B SXBRB34C MXBRB34D DXBRB350 TBEDRB351 TBDRB353 DIEBRB357 FIEBRB357 FIEBRAB358 THDERB359 THDRB35B DIDBRB35F FIDBRB35F FIDBRAB360 LPXRB361 LNXRB362 LTXRB363 LCXRB365 LXRB366 LEXRB367 FIXRB369 CXR

OpCode MnemonicB370 LPDFRB371 LNDFRB372 CPSDRB373 LCDFRB374 LZERB375 LZDRB376 LZXRB377 FIERB37F FIDRB384 SFPCB385 SFASRB38C EFPCB390 CELFBRB391 CDLFBRB392 CXLFBRB394 CEFBRB394 CEFBRAB395 CDFBRB395 CDFBRAB396 CXFBRB396 CXFBRAB398 CFEBRB398 CFEBRAB399 CFDBRB399 CFDBRAB39A CFXBRB39A CFXBRAB39C CLFEBRB39D CLFDBRB39E CLFXBRB3A0 CELGBRB3A1 CDLGBRB3A2 CXLGBRB3A4 CEGBRB3A4 CEGBRAB3A5 CDGBRB3A5 CDGBRAB3A6 CXGBRB3A6 CXGBRAB3A8 CGEBRB3A8 CGEBRAB3A9 CGDBRB3A9 CGDBRAB3AA CGXBRB3AA CGXBRAB3AC CLGEBRB3AD CLGDBRB3AE CLGXBRB3B4 CEFRB3B5 CDFRB3B6 CXFRB3B8 CFERB3B9 CFDRB3BA CFXRB3C1 LDGRB3C4 CEGRB3C5 CDGRB3C6 CXGRB3C8 CGERB3C9 CGDRB3CA CGXRB3CD LGDRB3D0 MDTRB3D0 MDTRAB3D1 DDTRB3D1 DDTRAB3D2 ADTRB3D2 ADTRAB3D3 SDTRB3D3 SDTRAB3D4 LDETRB3D5 LEDTRB3D6 LTDTRB3D7 FIDTRB3D8 MXTRB3D8 MXTRA

OpCode Mnemonic


B3D9 DXTRB3D9 DXTRAB3DA AXTRB3DA AXTRAB3DB SXTRB3DB SXTRAB3DC LXDTRB3DD LDXTRB3DE LTXTRB3DF FIXTRB3E0 KDTRB3E1 CGDTRB3E1 CGDTRAB3E2 CUDTRB3E3 CSDTRB3E4 CDTRB3E5 EEDTRB3E7 ESDTRB3E8 KXTRB3E9 CGXTRB3E9 CGXTRAB3EA CUXTRB3EB CSXTRB3EC CXTRB3ED EEXTRB3EF ESXTRB3F1 CDGTRB3F1 CDGTRAB3F2 CDUTRB3F3 CDSTRB3F4 CEDTRB3F5 QADTRB3F6 IEDTRB3F7 RRDTRB3F9 CXGTRB3F9 CXGTRAB3FA CXUTRB3FB CXSTRB3FC CEXTRB3FD QAXTRB3FE IEXTRB3FF RRXTRB6 STCTLB7 LCTLB900 LPGRB901 LNGRB902 LTGRB903 LCGRB904 LGRB905 LURAGB906 LGBRB907 LGHRB908 AGRB909 SGRB90A ALGRB90B SLGRB90C MSGRB90D DSGRB90E EREGGB90F LRVGRB910 LPGFRB911 LNGFRB912 LTGFRB913 LCGFRB914 LGFRB916 LLGFRB917 LLGTRB918 AGFRB919 SGFRB91A ALGFRB91B SLGFRB91C MSGFRB91D DSGFRB91E KMACB91F LRVRB920 CGR

OpCode MnemonicB921 CLGRB925 STURGB926 LBRB927 LHRB928 PCKMOB929 KMAB92A KMFB92B KMOB92C PCCB92D KMCTRB92E KMB92F KMCB930 CGFRB931 CLGFRB939 DFLTCCB93A KDSAB93C PRNOB93E KIMDB93F KLMDB941 CFDTRB942 CLGDTRB943 CLFDTRB946 BCTGRB949 CFXTRB94A CLGXTRB94B CLFXTRB951 CDFTRB952 CDLGTRB953 CDLFTRB959 CXFTRB95A CXLGTRB95B CXLFTRB960 CGRTB961 CLGRTB964 NNGRKB965 OCGRKB966 NOGRKB967 NXGRKB972 CRTB973 CLRTB974 NNRKB975 OCRKB976 NORKB977 NXRKB980 NGRB981 OGRB982 XGRB983 FLOGRB984 LLGCRB985 LLGHRB986 MLGRB987 DLGRB988 ALCGRB989 SLBGRB98A CSPGB98D EPSWB98E IDTEB98F CRDTEB990 TRTTB991 TRTOB992 TROTB993 TROOB994 LLCRB995 LLHRB996 MLRB997 DLRB998 ALCRB999 SLBRB99A EPAIRB99B ESAIRB99D ESEAB99E PTIB99F SSAIRB9A1 TPEIB9A2 PTFB9AA LPTEA

OpCode MnemonicB9AC IRBMB9AE RRBMB9AF PFMFB9B0 CU14B9B1 CU24B9B2 CU41B9B3 CU42B9BD TRTREB9BE SRSTUB9BF TRTEB9C0 SELFHRB9C8 AHHHRB9C9 SHHHRB9CA ALHHHRB9CB SLHHHRB9CD CHHRB9CF CLHHRB9D8 AHHLRB9D9 SHHLRB9DA ALHHLRB9DB SLHHLRB9DD CHLRB9DF CLHLRB9E0 LOCFHRB9E1 POPCNTB9E2 LOCGRB9E3 SELGRB9E4 NGRKB9E5 NCGRKB9E6 OGRKB9E7 XGRKB9E8 AGRKB9E9 SGRKB9EA ALGRKB9EB SLGRKB9EC MGRKB9ED MSGRKCB9F0 SELRB9F2 LOCRB9F4 NRKB9F5 NCRKB9F6 ORKB9F7 XRKB9F8 ARKB9F9 SRKB9FA ALRKB9FB SLRKB9FD MSRKCBA CSBB CDSBD CLMBE STCMBF ICMC00 LARLC01 LGFIC04 BRCLC05 BRASLC06 XIHFC07 XILFC08 IIHFC09 IILFC0A NIHFC0B NILFC0C OIHFC0D OILFC0E LLIHFC0F LLILFC20 MSGFIC21 MSFIC24 SLGFIC25 SLFIC28 AGFIC29 AFIC2A ALGFIC2B ALFIC2C CGFI

OpCode Mnemonic

31

C2D CFIC2E CLGFIC2F CLFIC42 LLHRLC44 LGHRLC45 LHRLC46 LLGHRLC47 STHRLC48 LGRLC4B STGRLC4C LGFRLC4D LRLC4E LLGFRLC4F STRLC5 BPRPC60 EXRLC62 PFDRLC64 CGHRLC65 CHRLC66 CLGHRLC67 CLHRLC68 CGRLC6A CLGRLC6C CGFRLC6D CRLC6E CLGFRLC6F CLRLC7 BPPC80 MVCOSC81 ECTGC82 CSSTC84 LPDC85 LPDGCC6 BRCTHCC8 AIHCCA ALSIHCCB ALSIHNCCD CIHCCF CLIHD0 TRTRD1 MVND2 MVCD3 MVZD4 NCD5 CLCD6 OCD7 XCD9 MVCKDA MVCPDB MVCSDC TRDD TRTDE EDDF EDMKE1 PKUE2 UNPKUE302 LTGE303 LRAGE304 LGE306 CVBYE308 AGE309 SGE30A ALGE30B SLGE30C MSGE30D DSGE30E CVBGE30F LRVGE312 LTE313 LRAYE314 LGFE315 LGHE316 LLGFE317 LLGTE318 AGFE319 SGF

OpCode MnemonicE31A ALGFE31B SLGFE31C MSGFE31D DSGFE31E LRVE31F LRVHE320 CGE321 CLGE324 STGE325 NTSTGE326 CVDYE32A LZRGE32E CVDGE32F STRVGE330 CGFE331 CLGFE332 LTGFE334 CGHE336 PFDE338 AGHE339 SGHE33A LLZRGFE33B LZRFE33C MGHE33E STRVE33F STRVHE346 BCTGE347 BICE348 LLGFSGE349 STGSCE34C LGGE34D LGSCE350 STYE351 MSYE353 MSCE354 NYE355 CLYE356 OYE357 XYE358 LYE359 CYE35A AYE35B SYE35C MFYE35E ALYE35F SLYE370 STHYE371 LAYE372 STCYE373 ICYE375 LAEYE376 LBE377 LGBE378 LHYE379 CHYE37A AHYE37B SHYE37C MHYE380 NGE381 OGE382 XGE383 MSGCE384 MGE385 LGATE386 MLGE387 DLGE388 ALCGE389 SLBGE38E STPQE38F LPQE390 LLGCE391 LLGHE394 LLCE395 LLHE396 MLE397 DL

OpCode MnemonicE398 ALCE399 SLBE39C LLGTATE39D LLGFATE39F LATE3C0 LBHE3C2 LLCHE3C3 STCHE3C4 LHHE3C6 LLHHE3C7 STHHE3C8 LFHATE3CA LFHE3CB STFHE3CD CHFE3CF CLHFE500 LASPE501 TPROTE502 STRAGE50A MVCRLE50E MVCSKE50F MVCDKE544 MVHHIE548 MVGHIE54C MVHIE554 CHHSIE555 CLHHSIE558 CGHSIE559 CLGHSIE55C CHSIE55D CLFHSIE560 TBEGINE561 TBEGINCE601 VLEBRHE602 VLEBRGE603 VLEBRFE604 VLLEBRZE605 VLBRREPE606 VLBRE607 VLERE609 VSTEBRHE60A VSTEBRGE60B VSTEBRFE60E VSTBRE60F VSTERE634 VPKZE635 VLRLE637 VLRLRE63C VUPKZE63D VSTRLE63F VSTRLRE649 VLIPE650 VCVBE652 VCVBGE658 VCVDE659 VSRPE65A VCVDGE65B VPSOPE65F VTPE671 VAPE673 VSPE677 VCPE678 VMPE679 VMSPE67A VDPE67B VRPE67E VSDPE700 VLEBE701 VLEHE702 VLEGE703 VLEFE704 VLLEZE705 VLREPE706 VLE707 VLBBE708 VSTEB

OpCode Mnemonic


E709 VSTEHE70A VSTEGE70B VSTEFE70E VSTE712 VGEGE713 VGEFE71A VSCEGE71B VSCEFE721 VLGVE722 VLVGE727 LCBBE730 VESLE733 VERLLE736 VLME737 VLLE738 VESRLE73A VESRAE73E VSTME73F VSTLE740 VLEIBE741 VLEIHE742 VLEIGE743 VLEIFE744 VGBME745 VREPIE746 VGME74A VFTCIE74D VREPE750 VPOPCTE752 VCTZE753 VCLZE756 VLRE75C VISTRE75F VSEGE760 VMRLE761 VMRHE762 VLVGPE764 VSUME765 VSUMGE766 VCKSME767 VSUMQE768 VNE769 VNCE76A VOE76B VNOE76C VNXE76D VXE76E VNNE76F VOCE770 VESLVE772 VERIME773 VERLLVE774 VSLE775 VSLBE777 VSLDBE778 VESRLVE77A VESRAVE77C VSRLE77D VSRLBE77E VSRAE77F VSRABE780 VFEEE781 VFENEE782 VFAEE784 VPDIE786 VSLDE787 VSRDE785 VBPERME78A VSTRCE78B VSTRSE78C VPERME78D VSELE78E VFMSE78F VFMAE794 VPKE795 VPKLS

OpCode MnemonicE797 VPKSE79E VFNMSE79F VFNMAE7A1 VMLHE7A2 VMLE7A3 VMHE7A4 VMLEE7A5 VMLOE7A6 VMEE7A7 VMOE7A9 VMALHE7AA VMALE7AB VMAHE7AC VMALEE7AD VMALOE7AE VMAEE7AF VMAOE7B4 VGFME7B8 VMSLE7B9 VACCCE7BB VACE7BC VGFMAE7BD VSBCBIE7BF VSBIE7C0 VCLGDE7C0 VCLFPE7C1 VCDLGE7C1 VCFPLE7C2 VCGDE7C2 VCSFPE7C3 VCDGE7C3 VCFPSE7C4 VFLLE7C5 VFLRE7C7 VFIE7CA WFKE7CB WFCE7CC VFPSOE7CE VFSQE7D4 VUPLLE7D5 VUPLHE7D6 VUPLE7D7 VUPHE7D8 VTME7D9 VECLE7DB VECE7DE VLCE7DF VLPE7E2 VFSE7E3 VFAE7E5 VFDE7E7 VFME7E8 VFCEE7EA VFCHEE7EB VFCHE7EE VFMINE7EF VFMAXE7F0 VAVGLE7F1 VACCE7F2 VAVGE7F3 VAE7F5 VSCBIE7F7 VSE7F8 VCEQE7F9 VCHLE7FB VCHE7FC VMNLE7FD VMXLE7FE VMNE7FF VMXE8 MVCINE9 PKAEA UNPKAEB04 LMGEB0A SRAGEB0B SLAG

OpCode MnemonicEB0C SRLGEB0D SLLGEB0F TRACGEB14 CSYEB1C RLLGEB1D RLLEB20 CLMHEB21 CLMYEB23 CLTEB24 STMGEB25 STCTGEB26 STMHEB2B CLGTEB2C STCMHEB2D STCMYEB2F LCTLGEB30 CSGEB31 CDSYEB3E CDSGEB44 BXHGEB45 BXLEGEB4C ECAGEB51 TMYEB52 MVIYEB54 NIYEB55 CLIYEB56 OIYEB57 XIYEB6A ASIEB6E ALSIEB7A AGSIEB7E ALGSIEB80 ICMHEB81 ICMYEB8E MVCLUEB8F CLCLUEB90 STMYEB96 LMHEB98 LMYEB9A LAMYEB9B STAMYEBC0 TPEBDC SRAKEBDD SLAKEBDE SRLKEBDF SLLKEBE0 LOCFHEBE1 STOCFHEBE2 LOCGEBE3 STOCGEBE4 LANGEBE6 LAOGEBE7 LAXGEBE8 LAAGEBEA LAALGEBF2 LOCEBF3 STOCEBF4 LANEBF6 LAOEBF7 LAXEBF8 LAAEBFA LAALEC42 LOCHIEC44 BRXHGEC45 BRXLGEC46 LOCGHIEC4E LOCHHIEC51 RISBLGEC54 RNSBGEC55 RISBGEC56 ROSBGEC57 RXSBGEC59 RISBGNEC5D RISBHGEC64 CGRJEC65 CLGRJ

OpCode Mnemonic

33

EC70 CGITEC71 CLGITEC72 CITEC73 CLFITEC76 CRJEC77 CLRJEC7C CGIJEC7D CLGIJEC7E CIJEC7F CLIJECD8 AHIKECD9 AGHIKECDA ALHSIKECDB ALGHSIKECE4 CGRBECE5 CLGRBECF6 CRBECF7 CLRBECFC CGIBECFD CLGIBECFE CIBECFF CLIBED04 LDEBED05 LXDBED06 LXEBED07 MXDBED08 KEBED09 CEBED0A AEBED0B SEBED0C MDEBED0D DEBED0E MAEBED0F MSEBED10 TCEBED11 TCDBED12 TCXBED14 SQEBED15 SQDBED17 MEEBED18 KDBED19 CDBED1A ADBED1B SDBED1C MDBED1D DDBED1E MADBED1F MSDBED24 LDEED25 LXDED26 LXEED2E MAEED2F MSEED34 SQEED35 SQDED37 MEEED38 MAYLED39 MYLED3A MAYED3B MYED3C MAYHED3D MYHED3E MADED3F MSDED40 SLDTED41 SRDTED48 SLXTED49 SRXTED50 TDCETED51 TDGETED54 TDCDTED55 TDGDTED58 TDCXTED59 TDGXTED64 LEYED65 LDY

OpCode MnemonicED66 STEYED67 STDYEDA8 CZDTEDA9 CZXTEDAA CDZTEDAB CXZTEDAC CPDTEDAD CPXTEDAE CDPTEDAF CXPTEE PLOEF LMDF0 SRPF1 MVOF2 PACKF3 UNPKF8 ZAPF9 CPFA APFB SPFC MPFD DP

OpCode Mnemonic


Condition Codes Condition Code 0 1 2 3Mask Bit Value 8 4 2 1General InstructionsAdd Zero < Zero > Zero OverflowAdd Halfword Zero < Zero > Zero OverflowAdd Halfword Immediate Zero < Zero > Zero OverflowAdd High Zero < Zero > Zero OverflowAdd Immediate Zero < Zero > Zero OverflowAdd Immediate High Zero < Zero > Zero OverflowAdd Logical Zero, no carry Not zero, no

carryZero, carry Not zero, carry

Add Logical High Zero, no carry Not zero, no carry

Zero, carry Not zero, carry

Add Logical Immediate Zero, no carry Not zero, no carry


Add Logical with Carry Zero, no carry Not zero, no carry


Add Logical with Signed Imme-diate

Zero, no carry Not zero, no carry


Add Logical with Signed Imme-diate High

Zero, no carry Not zero, no carry


AND Zero Not zero — —AND Immediate ANDed bits

zeroANDed bits not zero

— —

AND with Complement Zero Not zero — —Checksum Checksum

complete— — CPU-deter-

mined com-pletion

Cipher Message Normal com-pletion

Verification mismatch

— Partial com-pletion

Cipher Message with Authenti-cation

Normal com-pletion


Partial com-pletion (LAAD or LPC zero)

Partial com-pletion (time out)

Cipher Message with Chaining Normal com-pletion



Cipher Message with Cipher Feedback

Normal com-pletion



Cipher Message with Counter Normal com-pletion



Cipher Message with Output Feedback

Normal com-pletion



Compare Equal First op low First op high —Compare and Form Codeword Equal First op low

and ctl = 0, or first op high and ctl = 1

First op high and ctl = 0, or first op low and ctl = 1

—

Compare and Swap Equal Not equal — —Compare and Swap and Store Equal Not equal — —Compare Double and Swap Equal Not equal — —Compare Halfword Equal First op low First op high —Compare Halfword Immediate Equal First op low First op high —Compare Halfword Relative

LongEqual First op low First op high —

Compare High Equal First op low First op high —Compare Immediate Equal First op low First op high —Compare Immediate High Equal First op low First op high —Compare Logical Equal First op low First op high —Compare Logical Characters

under MaskEqual, or Mask is zero

First op low First op high —

Compare Logical High Equal First op low First op high —Compare Logical Immediate Equal First op low First op high —Compare Logical Immediate

HighEqual First op low First op high —

Compare Logical Long Equal First op low First op high —Compare Logical Long

ExtendedEqual First op low First op high CPU-deter-

mined com-pletion

Compare Logical Long Uni-code

Equal First op low First op high CPU-deter-mined com-pletion

Compare Logical Relative Long

Equal First op low First op high —

Compare Logical String Equal First op low First op high CPU-deter-mined com-pletion

35

Compare Relative Long Equal First op low First op high —Compare until Substring Equal Equal sub-

stringLast bytes equal

Last bytes unequal

CPU-deter-mined com-pletion

Compression Call Second op end

First op end, not second op end

— CPU-deter-mined com-pletion

Compute Intermediate Mes-sage Digest

Normal com-pletion

— — Partial com-pletion

Compute Last Message Digest Normal com-pletion


Compute Message Authentica-tion Code

Normal com-pletion



Convert UTF-16 to UTF-32 Data pro-cessed

First op full Invalid low surrogate



First op full Invalid low surrogate



First op full Invalid UTF-32 character











Exclusive OR Zero Not zero — —Exclusive OR Immediate XORed bits

zeroXORed bits not zero

— —

Find Leftmost One No one bit found

— One bit found —

Insert Characters under Mask All zero, or mask is zero

Leftmost bit = 1

Not zero, but with leftmost bit = 0

—

Load and Test Zero < Zero > Zero —Load Complement Zero < Zero > Zero OverflowLoad Negative Zero < Zero — —Load Positive Zero — > Zero OverflowMove Long Operand

lengths equalFirst op shorter

First op longer Overlap

Move Long Extended Operand lengths equal

First op shorter

First op longer CPU-deter-mined com-pletion

Move Long Unicode Operand lengths equal

First op shorter

First op longer CPU-deter-mined com-pletion

Move String — Second op moved


Multiply Single (MSC, MSGC, MSGRKC, MRRKC)

Zero, no over-flow

< Zero, no overflow

> Zero, no overflow

Overflow

NAND Zero Not zero — —NOR Zero Not zero — —NOT Exclusive OR Zero Not zero — —OR Zero Not zero — —OR Immediate ORed bits

zeroORed bits not zero

— —

OR with Complement Zero Not zero — —Perform Cryptographic Compu-

tationNormal com-pletion



Perform Locked Operation (test bit zero)

Equal First op not equal

First op equal, third op not equal

—

Perform Locked Operation (test bit one)

Code valid — — Code invalid

Perform Random Number Operation

Normal com-pletion


Population Count Zero Not zero — —

Condition Code 0 1 2 3Mask Bit Value 8 4 2 1


Rotate Then AND Selected Bits

Selected bits zero

Selected bits not zero

— —

Rotate Then Exclusive OR Selected Bits

Selected bits zero


— —

Rotate Then Insert Selected Bits

Zero < zero > zero —

Rotate Then OR Selected Bits Selected bits zero


— —

Search String, Search String Unicode

— Character found

Character not found


Set Program Mask4 See Note See Note See Note See NoteShift Left (Double / Single) Zero < Zero > Zero OverflowShift Right (Double / Single) Zero < Zero > Zero —Store Clock (STCK, STCKE or

STCKF)Set state Not-set state Error state Stopped state

or not opera-tional

Store Facility List Extended Complete list stored

— — Incomplete list stored

Subtract Zero < Zero > Zero OverflowSubtract Halfword Zero < Zero > Zero OverflowSubtract High Zero < Zero > Zero OverflowSubtract Logical — Not zero, bor-

rowZero, no bor-row

Not zero, no borrow

Subtract Logical High — Not zero, bor-row

Zero, no bor-row

Not zero, no borrow

Subtract Logical Immediate — Not zero, bor-row

Zero, no bor-row

Not zero, no borrow

Subtract Logical with Borrow Zero, borrow Not zero, bor-row

Zero, no bor-row

Not zero, no borrow

Test Addressing Mode 24-bit mode 31-bit mode — 64-bit modeTest and Set Leftmost bit

zeroLeftmost bit one

— —

Test under Mask (TM) All zeros, or mask is zero

Mixed 0's and 1's

— All ones

Test under Mask (TMH, TMHH, TMHL, TML, TMLH, TMLL)

All zeros or mask is zero

Mixed 0's and 1's and left-most bit zero

Mixed 0's and 1's and left-most bit one

All ones

Test under Mask High, Low All zeros or mask is zero

Mixed 0's and 1's and left-most bit zero

Mixed 0's and 1's and left-most bit one

All ones

Transaction Begin Successful — — —Transaction End In TX mode — Not in TX

mode—

Translate and Test, Translate and Test Reverse

All zeros Not zero, scan incomplete

Not zero, scan complete

—

Translate and Test Extended, Translate and Test Reverse Extended

All selected function codes zero

Nonzero func-tion code selected


Translate Extended Data pro-cessed

First op byte equal test byte


Translate One to One, One to Two, Two to One, Two to Two

Character not found

Character found

— CPU deter-mined com-pletion

Unpack ASCII Sign plus Sign minus — Sign invalidUnpack Unicode Sign plus Sign minus — Sign invalidUpdate Tree Compare

equal at cur-rent node on path

Path com-plete, no nodes com-pared equal

— Path not com-plete and compared reg-ister negative

Decimal InstructionsAdd Decimal Zero < Zero > Zero OverflowCompare Decimal Equal First op low First op high —Edit Zero < Zero > Zero —Edit and Mark Zero < Zero > Zero —Shift and Round Decimal Zero < Zero > Zero OverflowSubtract Decimal Zero < Zero > Zero OverflowTest Decimal Digits and sign

validSign invalid Digit invalid Sign and digit

invalidZero and Add Zero < Zero > Zero Overflow


37

Floating-PointInstructionsAdd Zero < Zero > Zero NaNAdd Normalized Zero < Zero > Zero —Add Unnormalized Zero < Zero > Zero —Compare (BFP) Equal First op low First op high UnorderedCompare (HFP) Equal First op low First op high —Compare and Signal Equal First op low First op high UnorderedCompare Biased Exponent Equal First op low First op high UnorderedConvert BFP to HFP Zero < Zero > Zero Special caseConvert HFP to BFP Zero < Zero > Zero Special caseConvert to Fixed Zero < Zero > Zero Special caseConvert to Logical Zero < Zero > Zero Special caseConvert to Packed Zero < Zero > Zero Special caseConvert to Zoned Zero < Zero > Zero Special caseDivide to Integer Remainder

complete, quotient nor-mal

Remainder complete, quotient over-flow or NaN

Remainder incomplete, quotient nor-mal

Remainder incomplete, quotient over-flow or NaN

Load and Test (BFP) Zero < Zero > Zero NaNLoad and Test (HFP) Zero < Zero > Zero —Load Complement (BFP) Zero < Zero > Zero NaNLoad Complement (HFP) Zero < Zero > Zero —Load Negative (BFP) Zero < Zero — NaNLoad Negative (HFP) Zero < Zero — —Load Positive (BFP) Zero — > Zero NaNLoad Positive (HFP) Zero — > Zero —Perform Floating-Point Opera-

tion (T=0)Normal result Nontrap

exceptionTrap exception —

Perform Floating-Point Opera-tion (T=1)

Function valid — — Function invalid

Subtract Zero < Zero > Zero NaNSubtract Normalized Zero < Zero > Zero —Subtract Unnormalized Zero < Zero > Zero —Test Data Class Zero (no

match)One (match) — —

Test Data Group Zero (no match)

One (match) — —

Vector-Facility InstructionsLoad Count to Block Boundary = 16 — — < 16Vector Add Decimal5 No overflow — — OverflowVector Compare Decimal Equal First op low First op high —Vector Compare Equal5 All elements

equalSome ele-ments equal

— No element equal

Vector Compare High Logical5 All elements high

Some ele-ments high

— No element high

Vector Compare High5 All elements high

Some ele-ments high

— No element high

Vector Convert to Binary5 No overflow — — Overflow

Vector Convert to Decimal5 No overflow — — Overflow

Vector Divide Decimal5 No overflow — — OverflowVector Element Compare Equal Low High —Vector Element Compare Logi-cal

Equal Low High —

Vector Find Any Element Equal5

None equal, zero found

Equal ele-ment found, no zeros if ZS=1

Equal ele-ment found and zero found

No equal ele-ments, no zeros

Vector Find Element Equal5 Zero found Equal ele-ment found, no zeros

Equal ele-ment found, and zero

Not equal, no zeros

Vector Find Element Not Equal5

Zero found Not equal ele-ment found, less than

Not equal found, greater than

Equal, no zero

Vector FP Compare And Signal Scalar

Elements equal

First element low

First element high

Elements unordered

Vector FP Compare Equal5 All elements equal

Mix of equal and unequal (or unor-dered) ele-ments

— All elements not equal (or unordered)



Vector FP Compare High Or Equal5

All elements Mix of and < — All elements < (or unordered)

Vector FP Compare High5 All elements > Mix of > and — All elements (or unordered)

Vector FP Compare Scalar Elements equal

First element low

First element high

Elements unordered

Vector FP Test Data Class Immediate

Match Selected bit 1 for some (but not all) ele-ments

— No match

Vector Isolate String5 Zero element found

— — All elements nonzero

Vector Multiply and Shift Deci-mal5

No overflow — — Overflow

Vector Multiply Decimal5 No overflow — — Overflow

Vector Pack Logical Saturate5 No saturation Some satu-rated

All saturated

Vector Pack Saturate5 No saturation Some satu-rated

All saturated

Vector Perform Sign Operation Decimal5


Vector Remainder Decimal5 No overflow — — OverflowVector Shift and Divide Deci-mal5


Vector Shift and Round Deci-mal5


Vector String Range Compare5 Zero found At least one in ranges, no zero

At least one in ranges, zero found

No ranges match, no zeros

Vector String Search No match and either ZS is 0 or no zero byte detected

No match and ZS is 1 and a zero byte detected

full match partial match

Vector Subtract Decimal5 No overflow — — Overflow

Vector Test Decimal5 Digits and sign valid

Sign invalid Digit invalid Sign and digit invalid

Vector Test Under Mask All zeros or mask zero

Mixed — All ones

Control InstructionsCompare and Replace DAT

Table EntryEqual Not equal — —

Compare and Swap and Purge Equal Not equal — —Diagnose1 See note See note See note See noteExtract Stacked State Branch state

entryProgram call state entry

— —

Insert Address Space Control Primary-space mode

Secondary-space mode

Access regis-ter mode

Home-space mode

Load Address Space Parame-ters

Parameters loaded

Primary not available

Secondary not authorized or not available

Space-switch event

Load Page-Table-Entry Address

Address returned; STE.P=0

Address returned; STE.P=1

Invalid bit on in RTE or STE.

Exception condition exists.

Load PSW3 See note See note See note See note

Load PSW Extended3 See note See note See note See note

Load Real Address2 Translation available

Segment table entry invalid

Page table entry invalid

See note

Move Page Data moved First op invalid, both valid in ES, locked, or ES error

Second op invalid

—

Move to Primary Length 256 — — Length > 256Move to Secondary Length 256 — — Length > 256Move with Key Length 256 — — Length > 256Move with Optional Specifica-

tionsLength 4096 — — Length > 4096

Page In Operation completed

ES data error — ES block not available

Page Out Operation completed

ES data error — ES block not available


39

Perform Timing Facility Func-tion

Function per-formed

— — Function not available

Perform Topology Function Initiated — Rejected —Program Return See note See note See note See noteReset Reference Bit Extended Ref = 0, Chg =

0Ref = 0, Chg = 1

Ref = 1, Chg = 0

Ref = 1, Chg = 1

Resume Program3 See note See note See note See noteSet Clock Set Secure — Not opera-

tionalSignal Processor Accepted Status stored Busy Not opera-

tionalStore System Information Info provided — — Info not avail-

ableTest Access ALET = 0 ALET uses

DUALDALET uses PSALD

ALET = 1 or causes ART exception

Test Pending External Interrup-tion

None pending One or more pending

— —

Test Block Usable Unusable — —Test Protection Fetch and

store allowedFetch allowed; no store allowed

No fetch or store allowed

Translation not available

Input/OutputInstructionsCancel Subchannel Function

started— — Not opera-

tionalClear Subchannel Function

started— — Not opera-

tionalHalt Subchannel Function

startedNon-interme-diate status pending

Busy Not opera-tional

Modify Subchannel Function exe-cuted

Status pend-ing


Reset Channel Path Function started

— Busy Not opera-tional

Resume Subchannel Function started

Status pend-ing

Not applicable Not opera-tional

Start Subchannel Function started

Status pend-ing


Store Channel Report Word CRW stored Zeros stored — —Store Subchannel SCHIB stored — — Not opera-

tionalTest Pending Interruption Interruption

not pendingInterruption code stored

— —

Test Subchannel IRB stored; status pending

IRB stored; not status pending

— Not opera-tional

Specialized-Function-AssistInstructionsCompute Digital Signature

Authenticationverify: signa-ture verified; sign: normal completion

verify: public key not on curve; sign: KVP mis-match; sign & verify: reserved area

verify: signa-ture incorrect or invalid; sign: random number not invertible if deterministic

partial com-pletion

DEFLATE Conversion Call Normal com-pletion

op1 length insufficient

op2 length insufficient or invalid input


Notes:1 For Diagnose, the resulting condition code is model-dependent.2 For Load Real Address, condition code 3 is set if address-space-control element not available,

region-table entry outside table or invalid, segment-table entry outside table, or, for LRA in 24- or 31-bit mode when bits 0-32 of entry address not all zeros, segment- or page-table entry invalid.

3 For Load PSW, Load PSW Extended, and Resume Program, the condition code is loaded from the condition-code field of the second operand.

4 For Set Program Mask, the condition code is loaded from bit positions 2 and 3 of the first oper-and.

5 For various vector-facility instructions, the condition code is optionally set based on the CS control in the M5 field of the instruction.



Assembler Instructions Function Mnemonic Meaning

Option control *PROCESS Specify assembler optionsACONTROL Dynamically modify options

Data definition CCW Define channel command wordCCW0 Define format-0 channel command wordCCW1 Define format-1 channel command wordDC Define constantDS Define storage

Program ALIAS Rename external symbolsectioning AMODE Specify addressing modeand linking CATTR Define class/part name and attributes

COM Identify common control sectionCSECT Identify control sectionCXD Cumulative length of external dummy sectionDSECT Identify dummy sectionDXD Define external dummy sectionENTRY Identify entry-point symbolEXTRN Identify external symbolLOCTR Specify multiple location countersRMODE Specify residence modeRSECT Identify read-only control sectionSTART Start assemblyWXTRN Identify weak external symbolXATTR Declare external symbol attributes

Base register DROP Drop base address registerassignment USING Use base address and register

Control of AEJECT Start new page in macro definitionlisting ASPACE Space lines in macro definition

CEJECT Conditional start new pageEJECT Start new pagePRINT Control listing contentsSPACE Space listingTITLE Identify assembly output

Program control ADATA Provide data for SYSADATA fileCNOP Conditional no operationCOPY Copy predefined source codingEND End assemblyEQU Equate symbolEXITCTL Program control data for I/O exitsICTL Input format controlISEQ Input sequence checkingLTORG Begin literal poolOPSYN Equate operation codeORG Set location counterPOP Restore ACONTROL, PRINT, or USING statusPUNCH Punch a recordPUSH Save current ACONTROL, PRINT, or USING statusREPRO Reproduce following record

Conditional ACTR Conditional assembly branch counterassembly AGO Unconditional branch

AIF Conditional branchAINSERT Create input recordANOP Assembly no operationAREAD Assign input record to SETC symbolGBLA Define global SETA symbolGBLB Define global SETB symbolGBLC Define global SETC symbolLCLA Define local SETA symbolLCLB Define local SETB symbolLCLC Define local SETC symbolMHELP Trace macro flowMNOTE Generate messageSETA Set arithmetic variable symbolSETAF Set arithmetic variable symbol from external functionSETB Set binary variable symbolSETC Set character variable symbolSETCF Set character variable symbol from external function

41

CNOP Alignment

Extended-Mnemonic Instructions for Branch on Condition and Branch Indirect on Condition

Extended-Mnemonic Instructions for Relative-Branch Instructions

Macro definition MACRO Macro definition header MEND Macro definition trailerMEXIT Macro expansion exit

Source: SC26-4940.

Quadword

Doubleword Doubleword

Fullword Fullword Fullword Fullword

Halfword Halfword Halfword Halfword Halfword Halfword Halfword Halfword

Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte

0,40,80,16

2,42,82,16

0,44,84,16

2,46,86,16

0,40,88,16

2,42,810,16

0,44,812,16

2,46,814,16

For byte offset and boundary values greater than 16, see IBM High Level Assembler for z/OS, z/VM & z/VSE Language Reference (SC26-4940).

UseExtended Mnemonic for:

Meaning M1 Value*BC BCR BICControl B BR BI Unconditional branch 15

NOP NOPR — No operation 0

After BH BHR BIH Branch on A High 2Compare BL BLR BIL Branch on A Low 4Instructions BE BER BIE Branch on A Equal B 8(A:B) BNH BNHR BINH Branch on A Not High 13

BNL BNLR BINL Branch on A Not Low 11BNE BNER BINE Branch on A Not Equal B 7

After BP BPR BIP Branch on Plus 2Arithmetic BM BMR BIM Branch on Minus 4Instructions BZ BZR BIZ Branch on Zero 8

BO BOR BIO Branch on Overflow 1BNP BNPR BINP Branch on Not Plus 13BNM BNMR BINM Branch on Not Minus 11BNZ BNZR BINZ Branch on Not Zero 7BNO BNOR BINO Branch on No Overflow 14

After Test BO BOR BIO Branch if Ones 1under Mask BM BMR BIM Branch if Mixed 4Instruction BZ BZR BIZ Branch if Zeros 8

BNO BNOR BINO Branch if Not Ones 14BNM BNMR BINM Branch if Not Mixed 11BNZ BNZR BINZ Branch if Not Zeros 7

Source: SC26-4940.— Not applicable for BIC* Extended mnemonic replaces the M1 field; second operand, not shown, is D2(X2,B2) for RX and

RXY formats and R2 for RR format.

UseExtendedMnemonic Meaning

MachineInstr.

General BRU or J Unconditional Branch Relative BRC 15,I2Branch Rel. BRUL or JLU Unconditional Branch Relative BRCL 15,I2on Condition JNOP* No Operation BRC 0,I2

After BRH or JH* Branch Relative on A High BRC 2,I2Compare BRL or JL* Branch Relative on A Low BRC 4,I2Instructions BRE or JE* Branch Relative on A Equal B BRC 8,I2

BRNH or JNH* Branch Relative on A Not High BRC 13,I2BRNL or JNL* Branch Relative on A Not Low BRC 11,I2BRNE or JNE* Branch Relative on A Not Equal B BRC 7,I2

After BRP or JP* Branch Relative on Plus BRC 2,I2Arithmetic BRM or JM* Branch Relative on Minus BRC 4,I2

Function Mnemonic Meaning


Extended-Mnemonic Suffixes for Compare-and-Branch, andCompare-and-Trap Instructions

Extended-Mnemonic Suffixes for Load/Store-on-ConditionInstructions

Extended-Mnemonic Suffixes for Rotate-Then-Insert / AND / OR /Exclusive OR-Selected-Bits Instructions

Instructions BRZ or JZ* Branch Relative on Zero BRC 8,I2BRO or JO* Branch Relative on Overflow BRC 1,I2BRNP or JNP* Branch Relative on Not Plus BRC 13,I2BRNM or JNM* Branch Relative on Not Minus BRC 11,I2BRNZ or JNZ* Branch Relative on Not Zero BRC 7,I2BRNO or JNO* Branch Relative on No Overflow BRC 14,I2

After Test BRO or JO* Branch Relative if Ones BRC 1,I2under Mask BRM or JM* Branch Relative if Mixed BRC 4,I2Instruction BRZ or JZ* Branch Relative if Zeros BRC 8,I2

BRNO or JNO* Branch Relative if Not Ones BRC 14,I2BRNM or JNM* Branch Relative if Not Mixed BRC 11,I2BRNZ or JNZ* Branch Relative if Not Zeros BRC 7,I2

Other Branch JAS Branch Relative and Save BRAS R1,I2Relative JASL Branch Relative and Save Long BRASL R1,I2Instructions JCT Branch Relative on Count (32) BRCT R1,I2

JCTG Branch Relative on Count (64) BRCTG R1,I2JXH Branch Relative on Index High (32) BRXH R1,R3,I2JXHG Branch Relative on Index High (64) BRXHG R1,R3,I2JXLE Br. Rel. on Index Low or Equal (32) BRXLE R1,R3,I2JXLEG Br. Rel. on Index Low or Equal (64) BRXLG R1,R3,I2

Source: SC26-4940.* To obtain BRCL instead of BRC, add L at the end of the B mnemonic or insert L after the J of the J mnemonic. For example, change BRNZ or JNZ to BRNZL or JLNZ.

Suffix Meaning M3 Value Suffix Meaning M3 ValueH High 2 NH Not High 12L Low 4 NL Not Low 10E Equal 8 NE Not Equal 6Explanation:

These suffixes may be appended to the following mnemonics: CGIB, CGIJ, CGIT, CGRB, CGRJ, CGRT, CIB, CIJ, CIT, CLFIT, CLGIB, CLGIJ, CLGIT, CLGRB, CLGRJ, CLGRT, CLGT, CLIB, CLIJ, CLRB, CLRJ, CLRT, CLT, CRB, CRJ, CRT. When the suffix is coded, the M3 oper-and must be omitted.

Suffix Meaning M3 Value Suffix Meaning M3 ValueO * One / Overflow 1 NO * Not one / Not overflow 14H High 2 NH Not High 13P * Plus 2 NP * Not Plus 13L Low 4 NL Not Low 11M * Minus / Mixed 4 NM * Not Minus / Mixed 11E Equal 8 NE Not Equal 7Z * Zero 8 NZ * Not Zero 7Explanation:

These suffixes may be appended to the following mnemonics: LOC, LOCG, LOCGHI, LOCGR, LOCHHI, LOCHI, LOCR, LOCFH, LOCFHR, STOC, STOCFH, STOCG. Suffixes marked with an asterisk (*) may not be available on earlier versions of the High Level Assembler.

Extended-Mnemonic Syntax

Basic-MnemonicEquivalent Meaning

LHHR R1,R2 RISBHGZ R1,R2,0,31 LOAD (HIGH HIGH)LHLR R1,R2 RISBHGZ R1,R2,0,31,32 LOAD (HIGH LOW)LLCHHR R1,R2 RISBHGZ R1,R2,24,31 LOAD LOG. CH. (HIGH HIGH)LLCHLR R1,R2 RISBHGZ R1,R2,24,31,32 LOAD LOG. CH. (HIGH LOW)LLCLHR R1,R2 RISBLGZ R1,R2,24,31,32 LOAD LOG. CH. (LOW HIGH)LLHFR R1,R2 RISBLGZ R1,R2,0,31,32 LOAD (LOW HIGH)LLHHHR R1,R2 RISBHGZ R1,R2,16,31 LOAD LOG. HW. (HIGH HIGH)LLHHLR R1,R2 RISBHGZ R1,R2,16,31,32 LOAD LOG. HW. (HIGH LOW)

UseExtendedMnemonic Meaning

MachineInstr.

43

Extended-Mnemonics for Vector-Facility Instructions

See z/Architecture Principles of Operation (SA22-7832) Chapters 21-24

Summary of Constants

LLHLHR R1,R2 RISBLGZ R1,R2,16,31,32 LOAD LOG. HW. (LOW HIGH)NHHR R1,R2 RNSBG R1,R2,0,31 AND HIGH (HIGH HIGH)NHLR R1,R2 RNSBG R1,R2,0,31,32 AND HIGH (HIGH LOW)NLHR R1,R2 RNSBG R1,R2,32,63,32 AND HIGH (LOW HIGH)OHHR R1,R2 ROSBG R1,R2,0,31 OR HIGH (HIGH HIGH)OHLR R1,R2 ROSBG R1,R2,0,31,32 OR HIGH (HIGH LOW)OLHR R1,R2 ROSBG R1,R2,32,63,32 OR HIGH (LOW HIGH)RISBGNZ R1,R2,I3,I4,I5 RISBGN R1,R2,I3,I4+128,I5 Set zero-remaining-bits control to 1.RISBGZ R1,R2,I3,I4,I5 RISBG R1,R2,I3,I4+128,I5 Set zero-remaining-bits control to 1.RISBHGZ R1,R2,I3,I4,I5 RISBHG R1,R2,I3,I4+128,I5 Set zero-remaining-bits control to 1.RISBLGZ R1,R2,I3,I4,I5 RISBLG R1,R2,I3,I4+128,I5 Set zero-remaining-bits control to 1.RNSBGT R1,R2,I3,I4,I5 RNSBG R1,R2,I3+128,I4,I5 Set test-results control to 1.ROSBGT R1,R2,I3,I4,I5 ROSBG R1,R2,I3+128,I4,I5 Set test-results control to 1.RXSBGT R1,R2,I3,I4,I5 RXSBG R1,R2,I3+128,I4,I5 Set test-results control to 1.XHHR R1,R2 RXSBG R1,R2,0,31 EXCL. OR HIGH (HIGH HIGH)XHLR R1,R2 RXSBG R1,R2,0,31,32 EXCL. OR HIGH (HIGH LOW)XLHR R1,R2 RXSBG R1,R2,32,63,32 EXCL. OR HIGH (LOW HIGH)Source: SA22-7832

Type

Implied Length, Bytes

Default Align-ment Format

Trunca-tion/Padding

A 4 Word Value of address or expression LeftAD 8 Doubleword Value of address or expression LeftB - Byte Binary digits LeftC - Byte Characters RightCA - Byte Characters (ASCII) RightCE - Byte Characters (EBCDIC) RightCU Even Byte Characters, translated to Unicode RightD 8 Doubleword Long hex floating point RightDB 8 Doubleword Long binary floating point RightDD 8 Doubleword Long decimal floating point RightDH 8 Doubleword Long hex floating point RightE 4 Word Short hex floating point RightEB 4 Word Short binary floating point RightED 4 Word Short decimal floating point RightEH 4 Word Short hex floating point RightF 4 Word Fixed-point binary LeftFD 8 Doubleword Fixed-point binary LeftG Even Byte Graphic (double-byte) characters RightH 2 Halfword Fixed-point binary LeftJ 4 Word Symbol naming a DXD, DSECT, or class LeftJD 8 Doubleword Symbol naming a DXD, DSECT, or class LeftL 16 Doubleword Extended hex floating point RightLB 16 Doubleword Extended binary floating point RightLD 16 Doubleword Extended decimal floating point RightLH 16 Doubleword Extended hex floating point RightLQ 16 Quadword Extended hex floating point RightP - Byte Packed decimal LeftQ 4 Word Symbol naming a DXD, DSECT, or part LeftQD 8 Doubleword Symbol naming a DXD, DSECT, or part LeftQY 3 Halfword Symbol naming a DXD, DSECT, or part in long-

displacement form–

R 4 Word PSECT address value LeftRD 8 Doubleword PSECT address value LeftS 2 Halfword Address in base-displacement form –SY 3 Halfword Address in base-and-long-displacement form –V 4 Word Externally defined address value –VD 8 Doubleword Externally defined address value –X - Byte Hexadecimal digits Left

Extended-Mnemonic Syntax

Basic-MnemonicEquivalent Meaning


Assigned Storage Locations

Y 2 Halfword Value of address or expression LeftZ - Byte Zoned decimal Left Source: SC26-4940.

HexAddr

DecAddr

AddrType Function

0-7 0-7 A IPL PSW†

8-F 8-15 A CCW-type IPL: IPL CCW1†

10-17 16-23 A CCW-type IPL: IPL CCW2†

10-13 16-19 A LD-IPL: Machine-loader execution-space size†

14-17 20-23 A LD-IPL: System-IPL parameter-list pointer†

80-83 128-131 R External-interruption parameter84-85 132-133 R CPU address associated with external interruption, or zeros86-87 134-135 R External-interruption code (see table on page 46)88-8B 136-139 R SVC-interruption identification: 0-12 zeros, 13-14 ILC, 15 zero,

16-31 code8C-8F 140-143 R Program-interruption identification: 0-12 zeros, 13-14 ILC, 15

zero, 16-31 code (see table on page 46)90-93 144-147 R Data-exception code or vector-exception code: 0-23 zeros, 24-

31 code (for DXC, see table on page 47; for VXC, see table on page 48)

94-95 148-149 R Monitor-class number: 0-7 zeros, 8-15 number96-97 150-151 R PER code, ATMID, AI (see table on page 50)98-9F 152-159 R PER addressA0 160 R Exception access identification: 0-3 zeros, 4-7 access-register

numberA1 161 R PER access identification: 0-3 zeros, 4-7 access-register num-

berA2 162 R Operand access identification (if page-translation exception rec-

ognized by MOVE PAGE): 0-3 R1, 4-7 R2

A3 163 A/R Store-status/machine-check architectural-mode identification: 0-6 zeros, 7 one

A8-AF 168-175 R Translation-exception identification (see table on page 48)B0-B7 176-183 R Monitor codeB8-BB 184-187 R Subsystem-identification word: 0-12 zeros, 13-14 SSID,15 one,

16-31 subchannel numberBC-BF 188-191 R I/O-interruption parameterC0-C3 192-195 R I/O-interruption-identification word: 0-1 zeros, 2-4 I/O-interrup-

tion subclass, 5-31 zerosC8-CB 200-203 R STFL facility list (see “Facility Indications” on page 51)E8-EF 232-239 R Machine-check-interruption code (see diagram on page 50)F4-F7 244-247 R External-damage code (see diagram on page 50)F8-FF 248-255 R Failing-storage address100-107 256-263 R Enhanced-Monitor Counter-Array Origin108-10B 264-267 R Enhanced-Monitor Counter-Array Size10C-10F 268-271 R Enhanced-Monitor Exception Count110-117 272-279 R Breaking-event address120-12F 288-303 R Restart old PSW130-13F 304-319 R External old PSW140-14F 320-335 R Supervisor-call old PSW150-15F 336-351 R Program old PSW160-16F 352-367 R Machine-check old PSW170-17F 368-383 R Input/output old PSW1A0-1AF 416-431 R Restart new PSW1B0-1BF 432-447 R External new PSW1C0-1CF 448-463 R Supervisor-call new PSW1D0-1DF 464-479 R Program new PSW1E0-1EF 480-495 R Machine-check new PSW1F0-1FF 496-511 R Input/output new PSW11B0-11B7 4528-4535 R Machine-check-extended-save-area address11C0-11FF 4544-4607 R Available for programming1200-127F 4608-4735 A/R Store-status/machine-check floating-point-register save area

Type

Implied Length, Bytes

Default Align-ment Format

Trunca-tion/Padding

45

External-Interruption CodesAt real-storage locations 134-135 (86-87 hex)

Program-Interruption Codes At real-storage locations 142-143 (8E-8F hex)

1280-12FF 4736-4863 A/R Store-status/machine-check general-register save area1300-130F 4864-4879 A/R Store-status PSW save area or machine-check fixed-logout

area‡

1318-131B 4888-4891 A Store-status prefix save area131C-131F 4892-4895 A/R Store-status/machine-check floating-point-control-register save

area1324-1327 4900-4903 A/R Store-status/machine-check TOD-programmable-register save

area1328-132F 4904-4911 A/R Store-status/machine-check CPU-timer save area1331-1337 4913-4919 A/R Store-status/machine-check clock-comparator bits 0-55 save

area (zeros at 4912)1340-137F 4928-4991 A/R Store-status/machine-check access-register save area1380-13FF 4992-5119 A/R Store-status/machine-check control-register save area1800-18FF 6144-6399 R Program-interruption TDB (see diagram on page 73)A Absolute address.R Real address.A/R A if store status; R if machine check.† When the configuration-z/Architecture-architectural-mode (CZAM) facility is installed.‡ Contents may vary among models; see System Library manuals.

Code(Hex) Condition

0040 Interrupt key1004 Clock comparator1005 CPU timer1007 Warning-track interruption1200 Malfunction alert1201 Emergency signal1202 External call1406 Timing alert1407 Measurement alert2401 Service signal

Code(Hex) Condition ILC Set

Instr. Ending

0001 Operation exception 1 2 3 S0002 Privileged-operation exception 2 3 S0003 Execute exception 2 3 S0004 Protection exception 1 2 3 S T0005 Addressing exception 1 2 3 S T0006 Specification exception 0 1 2 3 C S0007 Data exception 1 2 3 C S T0008 Fixed-point-overflow exception 1 2 3 C0009 Fixed-point-divide exception 1 2 3 C S000A Decimal-overflow exception 2 3 C000B Decimal-divide exception 2 3 S000C HFP-exponent-overflow exception 1 2 3 C000D HFP-exponent-underflow exception 1 2 3 C000E HFP-significance exception 1 2 C000F HFP-floating-point-divide exception 1 2 S0010 Segment-translation exception 1 2 3 N0011 Page-translation exception 1 2 3 N0012 Translation-specification exception 1 2 3 S0013 Special-operation exception 1 2 3 S0015 Operand exception 2 S0016 Trace-table exception 1 2 N0018 Transaction constraint 1 2 3 S

HexAddr

DecAddr

AddrType Function


Data-Exception Code (DXC)At real-storage location 147 (93 hex) and in byte 2 of floating-point-control register

001B Vector-processing 3 S001C Space-switch event 0 1 2 C001D HFP-square-root exception 2 S001F PC-translation-specification exception 2 S0020 AFX-translation exception 1 2 N0021 ASX-translation exception 1 2 N0022 LX-translation exception 2 N0023 EX-translation exception 2 N0024 Primary-authority exception 2 N0025 Secondary-authority exception 1 2 N0026 LFX-translation exception 2 N0027 LSX-translation exception 2 N0028 ALET-specification exception 1 2 3 S0029 ALEN-translation exception 1 2 3 N002A ALE-sequence exception 1 2 3 N002B ASTE-validity exception 1 2 3 N002C ASTE-sequence exception 1 2 3 N002D Extended-authority exception 1 2 3 N002E LSTE sequence 2 N002F ASTE instance 1 2 3 N0030 Stack-full exception 2 N0031 Stack-empty exception 1 2 N0032 Stack-specification exception 1 2 N0033 Stack-type exception 1 2 N0034 Stack-operation exception 1 2 N0038 ASCE-type exception 1 2 3 N0039 Region-first-translation exception 1 2 3 N003A Region-second-translation exception 1 2 3 N003B Region-third-translation exception 1 2 3 N0040 Monitor event 2 C0080 PER basic event (code may be combined with another code) 0 1 2 3 C0080 PER nullification event 0 N0119 Crypto-operation exception 2 N0200 Transactional-execution-aborted event 1 2 3 CC CompletedILC Instruction-length codeN NullifiedS SuppressedT Terminated

Code(Hex) Data Exception00 General operand01 AFP register02 BFP instruction03 DFP instruction04 Quantum exception07 Simulated quantum exception08 IEEE inexact and truncated0B IXS inexact0C IEEE inexact and incremented10 IEEE underflow, exact13 IXS underflow, exact18 IEEE underflow, inexact and truncated1B IXS underflow, inexact1C IEEE underflow, inexact and incremented20 IEEE overflow, exact23 IXS overflow, exact28 IEEE overflow, inexact and truncated2B IXS overflow, inexact2C IEEE overflow, inexact and incremented40 IEEE division by zero43 IXS division by zero80 IEEE invalid operation

Code(Hex) Condition ILC Set

Instr. Ending

47

Vector-Exception Code (VXC)At real-storage location 147 (93 hex) and in byte 2 of floating-point-control register

PER Code, ATMID, and AIAt real-storage locations 150-151

Translation-Exception IdentificationAt real-storage locations 168-175 (A8-AF hex)

83 IXS invalid operationFE Vector instructionFF Compare-and-trap or load-and-trap instruction

VIX VXCVector Interrupt Code (VIC)

Value Meaning

0 4 7 0001 IEEE invalid operation0010 IEEE division by zero

Vector Index (VIX) 0011 IEEE overflowIndex to the leftmost element that recognized the exception

0100 IEEE underflow0101 IEEE inexact

PER Code ATMID AI

0 8 14 15

Program-Event-Recording (PER Code) Addressing and-Translation-Mode ID (ATMID)Bit Meaning Bit Meaning0 Successful-branching event 8 PSW bit 311 Instruction-fetching event 9 ATMID-validity bit2 Storage-alteration event 10 PSW bit 323 Storage-key-alteration event 11 PSW bit 54 Store-using-real-address event 12-13 PSW bits 16-175 Zero-address-detection event PER ASCE Identification (AI)6 Transaction-end event 14-15 0 - primary; 1 - AR-specified;

2 - secondary; 3 - home7 Instruction-fetch-nullification event

Interrup-tion Code(Hex) Exception or Event Format of Information Stored*

0004 Protection If 61 zero: rest unpredictable,If 61 one: suppression, 0-51 address; 52-53 access-exception fetch/store indication; bits 56, 60, and 61 form a 3-bit protection code, 62-63 ASCE identifica-tion, rest unpredictable, location 160 valid; if DAT was off, rest unpredictable

0010 Segment translation 0-51 address; 52-53 access-exception fetch/store indication; 54-61 unpredictable, 62-63 ASCE identi-fication

0011 Page translation 0-51 address; 52-53 access-exception fetch/store indication; 54-60 unpredictable, if 61, zero, not MOVE PAGE; if 61 one, MOVE PAGE (see location 162); 62-63 ASCE identification

001C Space switch From primary-space mode: 32 old primary-space-switch-event control, 33-47 zeros, 48-63 old PASNFrom home-space mode: 32 home-space-switch-event control, 33-63 zeros

0020 AFX translation 32-47 zeros, 48-63 address-space number

0021 ASX translation 32-47 zeros, 48-63 address-space number

0022 LX translation 32-43 zeros, 44-63 program-call number

0023 EX translation 32-43 zeros, 44-63 program-call number

0024 Primary authority 32-47 zeros, 48-63 address-space number

Code(Hex) Data Exception


0025 Secondary authority 32-47 zeros, 48-63 address-space number

00260027

LFX translationLSX translation

When bit 44 is 0: 32-43 zeros, 44-63 program-call number. When bit 44 is 1, 32-63 program-call num-ber

0038 ASCE type 0-51 address; 52-53 access-exception fetch/store indication; 54-61 unpredictable, 62-63 ASCE identi-fication

0039 Region-first translation 0-51 address; 52-53 access-exception fetch/store indication; 54-61 unpredictable, 62-63 ASCE identi-fication

003A Region-second translation 0-51 address; 52-53 access-exception fetch/store indication; 54-61 unpredictable, 62-63 ASCE identi-fication

003B Region-third translation 0-51 address; 52-53 access exception fetch/store indication; 54-61 unpredictable, 62-63 ASCE identi-fication

* Bits 0-31 (bytes 168-171) unchanged if not described.

Interrup-tion Code(Hex) Exception or Event Format of Information Stored*

49

Machine-Check Interruption CodeAt real-storage locations 232-239 (E8-EF hex)

External-Damage Code

At real-storage address 244-247 (F4-F7 hex)

SD

PD

SR

0CD

ED

0DG

WCP

SP

CK

0 0 B 0SE

SC

KE

DS

WP

MS

PM

IA

FA

VR

EC

FP

GR

CR

RI

ST

0 4 8 14 16 24 26 31

IE

AR

DA 0 G

S 0 0 0 0 0 PR

FC

AP 0 C

TCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

32 36 40 42 46 48 56 63

Bit Meaning0 (SD) System damage1 (PD) Instruction-processing damage2 (SR) System recovery4 (CD) Timing-facility damage5 (ED) External damage7 (DG) Degradation8 (W) Warning9 (CP) Channel report pending10 (SP) Service-processor damage11 (CK) Channel-subsystem damage14 (B) Backed up16 (SE) Storage error uncorrected17 (SC) Storage error corrected18 (KE) Storage-key error uncorrected19 (DS) Storage degradation20 (WP) PSW-MWP validity21 (MS) PSW mask and key validity22 (PM) PSW program-mask and condition-code validity23 (IA) PSW-instruction-address validity24 (FA) Failing-storage-address validity25 (VR) Vector-register validity26 (EC) External-damage-code validity27 (FP) Floating-point-register validity28 (GR) General-register validity29 (CR) Control-register validity30 (RI) Reserved for IBM use31 (ST) Storage logical validity32 (IE) Indirect storage error33 (AR) Access-register validity34 (DA) Delayed-access exception36 (GS) Guarded-storage-registers validity42 (PR) TOD-programmable-register validity43 (FC) Floating-point-control-register validity44 (AP) Ancillary report46 (CT) CPU-timer validity47 (CC) Clock-comparator validity

0 0 0 0 0 0 0 0XN

XF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 8 9 10 16 24 31

Bit Meaning8 (XN) Expanded storage not operational9 (XF) Expanded-storage control failure


Facility IndicationsThe first 32 facility indications are stored at real-storage locations 200-203 (C8-CB hex) by STFL; the specified number of doublewords of facility indications are stored at second-operand location by STFLE.

Bit Meaning when Bit is One

0 The instructions marked “N3” in the instruction-summary figures in Chapters 7 and 10 are installed.

1 The z/Architecture architectural mode is installed. 2 The z/Architecture architectural mode is active. When bits 2 and 168 are both zero, the

ESA/390 architectural mode is active; when bit 2 is zero and bit 168 is one, the ESA/390 compatibility mode is active.

3 The DAT-enhancement facility is installed in the z/Architecture architectural mode. The DAT-enhancement facility includes the INVALIDATE DAT TABLE ENTRY (IDTE) and COMPARE AND SWAP AND PURGE (CSPG) instructions.

4 INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation-and-clearing operation by selectively clearing TLB segment-table entries when a segment-table entry or entries are invalidated. IDTE also performs the clearing-by-ASCE operation. Unless bit 4 is one, IDTE simply purges all TLBs. Bit 3 is one if bit 4 is one.

5 INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation-and-clearing operation by selectively clearing TLB region-table entries when a region-table entry or entries are invalidated. Bits 3 and 4 are ones if bit 5 is one.

6 The ASN-and-LX reuse facility is installed in the z/Architecture architectural mode.7 The store-facility-list-extended facility is installed. 8 The enhanced-DAT facility 1 is installed in the z/Architecture architectural mode.9 The sense-running-status facility is installed in the z/Architecture architectural mode.

10 The conditional-SSKE facility is installed in the z/Architecture architectural mode.11 The configuration-topology facility is installed in the z/Architecture architectural mode.13 The IPTE-range facility is installed in the z/Architecture architectural mode.14 The nonquiescing key-setting facility is installed in the z/Architecture architectural mode.16 The extended-translation facility 2 is installed. 17 The message-security assist is installed. 18 The long-displacement facility is installed in the z/Architecture architectural mode. 19 The long-displacement facility has high performance. Bit 18 is one if bit 19 is one. 20 The HFP-multiply-add/subtract facility is installed. 21 The extended-immediate facility is installed in the z/Architecture architectural mode.22 The extended-translation facility 3 is installed in the z/Architecture architectural mode.23 The HFP-unnormalized-extension facility is installed in the z/Architecture architectural

mode.24 The ETF2-enhancement facility is installed.25 The store-clock-fast facility is installed in the z/Architecture architectural mode.26 The parsing-enhancement facility is installed in the z/Architecture architectural mode.27 The move-with-optional-specifications facility is installed in the z/Architecture architectural

mode.28 The TOD-clock-steering facility is installed in the z/Architecture architectural mode.30 The ETF3-enhancement facility is installed in the z/Architecture architectural mode.31 The extract-CPU-time facility is installed in the z/Architecture architectural mode.32 The compare-and-swap-and-store facility is installed in the z/Architecture architectural

mode.33 The compare-and-swap-and-store facility 2 is installed in the z/Architecture architectural

mode.34 The general-instructions-extension facility is installed in the z/Architecture architectural

mode.35 The execute-extensions facility is installed in the z/Architecture architectural mode.36 The enhanced-monitor facility is installed in the z/Architecture architectural mode.37 The floating-point extension facility is installed in the z/Architecture architectural mode. 39 Assigned to IBM internal use.40 The set-program-parameters facility is installed in the z/Architecture architectural mode. 41 The floating-point-support-enhancement facilities (FPR-GR-loading, FPS-sign-handling,

and DFP-rounding) are installed in the z/Architecture architectural mode.42 The DFP (decimal-floating-point) facility is installed in the z/Architecture architectural

mode.43 The DFP (decimal-floating-point) facility has high performance. Bit 42 is one if bit 43 is

one.44 The PFPO instruction is installed in the z/Architecture architectural mode.45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities,

the interlocked-access facility 1, and the load/store-on-condition facility 1 are installed in the z/Architecture architectural mode.

47 The CMPSC-enhancement facility is installed in the z/Architecture architectural mode.

51

48 The decimal-floating-point zoned-conversion facility is installed in the z/Architecture archi-tectural mode.

49 The execution-hint, load-and-trap, and processor-assist facilities and the miscellaneous-instruction-extensions facility 1, are installed in the z/Architecture architectural mode.

50 The constrained transactional-execution facility is installed in the z/Architecture architec-tural mode. This bit is meaningful only when bit 73 is one.

51 The local-TLB-clearing facility is installed in the z/Architecture architectural mode.52 The interlocked-access facility 2 is installed. 53 The load/store-on-condition facility 2 and load-and-zero-rightmost-byte facility are

installed in the z/Architecture architectural mode.57 The message-security-assist-extension 5 is installed in the z/Architecture architectural

mode. 58 The miscellaneous-instruction-extensions facility 2 is installed in the z/Architecture archi-

tectural mode.61 The miscellaneous-instruction-extensions facility 3 is installed in the z/Architecture archi-

tectural mode.66 The reset-reference-bits-multiple facility is installed in the z/Architecture architectural

mode.67 The CPU-measurement counter facility is installed in the z/Architecture architectural

mode. 68 The CPU-measurement sampling facility is installed in the z/Architecture architectural

mode. 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit

49 is one when bit 73 is one.74 The store-hypervisor-information facility is installed in the z/Architecture architectural

mode (see z/VM CP Programming Services [SC24-6179]).75 The access-exception-fetch/store-indication facility is installed in the z/Architecture archi-

tectural mode.76 The message-security-assist-extension 3 is installed in the z/Architecture architectural

mode. 77 The message-security-assist-extension 4 is installed in the z/Architecture architectural

mode. 78 The enhanced-DAT facility 2 is installed in the z/Architecture architectural mode.80 The decimal-floating-point packed-conversion facility is installed in the z/Architecture

architectural mode.81 The PPA-in-order facility is installed in the z/Architecture architectural mode.129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.130 The instruction-execution-protection facility is installed in the z/Architecture architectural

mode. 131 The side-effect-access facility and the enhanced-suppression-on-protection facility 2 are

installed in the z/Architecture architectural mode. 133 The guarded-storage facility is installed in the z/Architecture architectural mode. 134 The vector-packed-decimal facility is installed in the z/Architecture architectural mode. 135 The vector-enhancements facility 1 is installed in the z/Architecture architectural mode. 138 The configuration z/Architecture architectural mode facility is installed.139 The multiple-epoch facility is installed in the z/Architecture architectural mode. 142 The store-CPU-counter-multiple facility is installed.144 The test-pending-external-interruption facility is installed in the z/Architecture architectural

mode. 145 The insert-reference-bits-multiple facility is installed in the z/Architecture architectural

mode. 146 The message-security-assist-extension 8 is installed in the z/Architecture architectural

mode. 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. 149 The move-page-and-set-key facility is installed in the z/Architecture architectural mode. 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode. 152 The vector-packed-decimal-enhancement facility is installed in the z/Architecture architec-

tural mode. 155 The message-security-assist-extension 9 is installed in the z/Architecture architectural

mode. 168 The ESA/390-compatibility-mode facility is installed in the configuration.

Bit Meaning when Bit is One


Control Registers CR Bits Name of Field Associated with Init*

0 8 Transactional-execution control Transactional-execution 09 Program-interruption filtering override Transactional-execution 0

10 Clock-comparator sign control TOD clock 030 Warning-track-interruption enable-

mentVirtual machines 0

32 Trace TOD-clock control TOD clock 033 SSM-suppression control SSM instruction 034 TOD-clock-sync control TOD clock 035 Low-address-protection control Low-address protection 036 Extraction-authority control Instruction authorization 037 Secondary-space control Instruction authorization 038 Fetch-protection-override control Key-controlled protection 039 Storage-protection-override control Key-controlled protection 040 Enhanced-DAT-enablement control Dynamic address translation 043 Instruction-execution-protection-

enablement controlInstruction-execution protection 0

44 ASN-and-LX-reuse control Instruction authorization 045 AFP-register control Floating point 046 Vector enablement control Vector facility for z/Architecture 048 Malfunction-alert subclass mask External interruptions 049 Emergency-signal subclass mask External interruptions 050 External-call subclass mask External interruptions 052 Clock-comparator subclass mask External interruptions 053 CPU-timer subclass mask External interruptions 054 Service-signal subclass mask External interruptions 056 Unused (See note) 157 Interrupt-key subclass mask External interruptions 158 Unused (See note) 159 ETR subclass mask External interruptions 061 Crypto control Cryptography 0

1 0-63 Primary address-space-control ele-ment

Dynamic address translation 0

0-51 Primary region-table or segment-table origin or real-space token origin


54 Primary subspace-group control Subspace groups 055 Primary private-space control Dynamic address translation 056 Primary storage-alteration-event con-

trolProgram-event recording 0

57 Primary space-switch-event control Program interruptions 058 Primary real-space control Dynamic address translation 0

60-61 Primary designation-type control Dynamic address translation 062-63 Primary table length Dynamic address translation 0

2 0-8 Reserved for IBM use System Controls 033-57 Dispatchable-unit-control-table origin Access-register translation 0

59 Guarded-storage facility enablement Guarded-storage facility 061 Transaction diagnostic scope Transactional execution 0

62-63 Transaction diagnostic control Transactional execution 03 0-31 Secondary ASTE Instance Number Instruction authorization 0

32-47 PSW-key mask Instruction authorization 048-63 Secondary ASN Address spaces 0

4 0-31 Primary ASTE Instance Number Instruction authorization 032-47 Authorization index Instruction authorization 048-63 Primary ASN Address spaces 0

5 33-57 Primary-ASTE origin Access-register translation 06 32-39 I/O-interruption subclass mask I/O interruptions 0

53

7 0-63 Secondary address-space-control element


0-51 Secondary region-table or segment-table origin or real-space token origin


54 Secondary subspace-group control Subspace groups 055 Secondary private-space control Dynamic address translation 056 Secondary storage-alteration-event

controlProgram-event recording 0

58 Secondary real-space control Dynamic address translation 060-61 Secondary designation-type control Dynamic address translation 062-63 Secondary table length Dynamic address translation 0

8 16-31 Enhanced-monitor masks MONITOR CALL instruction 032-47 Extended authorization index Access-register translation 048-63 Monitor masks MONITOR CALL instruction 0

9 32 Successful-branching-event mask Program-event recording 033 Instruction-fetching-event mask Program-event recording 034 Storage-alteration-event mask Program-event recording 035 Storage-key-alteration-event mask Program-event recording 036 Store-using-real-address-event mask Program-event recording 037 Zero-address-detection-event mask Program-event recording 038 Transaction-end-event mask Program-event recording 039 Instruction-fetching-nullification-event

maskProgram-event recording 0

40 Branch-address control Program-event recording 041 Event-suppression control Program-event recording 042 Storage-alteration-space control Program-event recording 0

10 0-63 PER starting address Program-event recording 011 0-63 PER ending address Program-event recording 012 0 Branch-trace control Tracing 0

1 Mode-trace control Tracing 02-61 Trace-entry address Tracing 062 ASN-trace control Tracing 063 Explicit-trace control Tracing 0

13 0-63 Home address-space-control ele-ment


0-51 Home region-table or segment-table origin or real-space token origin


54 Home subspace-group control Subspace groups 055 Home private-space control Dynamic address translation 056 Home storage-alteration-event con-

trolProgram-event recording 0

57 Home space-switch-event control Program interruptions 058 Home real-space control Dynamic address translation 0

60-61 Home designation-type control Dynamic address translation 062-63 Home table length Dynamic address translation 0

14 32 Unused (See note) 133 Unused (See note) 135 Channel-report-pending

subclass maskI/O machine-check handling 0

36 Recovery subclass mask Machine-check handling 037 Degradation subclass mask Machine-check handling 038 External-damage subclass mask Machine-check handling 139 Warning subclass mask Machine-check handling 042 TOD-clock-control-override control TOD clock 044 ASN-translation control Instruction authorization 0

45-63 ASN-first-table origin ASN translation 015 0-60 Linkage-stack-entry address Linkage-stack operations 0

* Value after initial CPU reset.Note: This bit is not used but is initialized to one for consistency with the

System/370 definition.

CR Bits Name of Field Associated with Init*


Floating-Point-Control (FPC) Register Masks Flags

DXC (see page 47)or

VCX (see page 48)0 DRM 0 BRMI

Mi

IMz

IMo

IMu

IMx

IMq

0 0SFi

SFz

SFo

SFu

SFx

SFq

0 0

0 8 16 24 31

Bit Meaning0 (IMi) IEEE-invalid-operation mask1 (IMz) IEEE-division-by-zero mask2 (IMo) IEEE-overflow mask3 (IMu) IEEE-underflow mask4 (IMx) IEEE-inexact mask5 (IMq) Quantum-exception mask8 (SFi) IEEE-invalid-operation flag9 (SFz) IEEE-division-by-zero flag10 (SFo) IEEE-overflow flag11 (SFu) IEEE-underflow flag12 (SFx) IEEE-inexact flag13 (SFq) Quantum-exception flag16-23 (DXC) Data-exception code (see table on page 47)25-27 (DRM) DFP Rounding mode

000 Round to nearest with ties to even001 Round toward 0010 Round toward +011 Round toward -100 Round to nearest with ties away from 0101 Round to nearest with ties toward 0110 Round away from 0111 Round to prepare for shorter precision

29-31 (BRM) BFP Rounding mode000 Round to nearest001 Round toward 0010 Round toward +011 Round toward -111 Round to prepare for shorter precision

55

Program-Status Word (PSW)

z/Architecture PSW

Short-Format PSW

0 R 0 0 0 T I E PSW Key 0 M W P AS CC Program Mask

RI 0 0 0 0 0 0 E

A

0 5 8 12 16 18 20 24 25 31

BA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

32 63

Bits 0-31 of Instruction Address

64 95

Bits 32-63 of Instruction Address

96 127

Bit Meaning1 (R) Program-event-recording mask5 (T = 1) DAT mode6 (I) Input/output mask7 (E) External mask12 Zero indicates a 16-byte PSW13 (M) Machine-check mask14 (W = 1) Wait state15 (P = 1) Problem state16-17 xx Real mode (T = 0)

00 – Primary-space mode (T = 1)01 – Access-register mode (T = 1)10 – Secondary-space mode (T = 1)11 – Home-space mode (T = 1)

18-19 (CC) Condition code20 Fixed-point-overflow mask21 Decimal-overflow mask22 HFP-exponent-underflow mask23 HFP-significance mask24 Reserved for IBM use31/32 Extended/basic addressing mode

00 – 24-bit mode01 – 31-bit mode10 – Invalid11 – 64-bit mode

0 R 0 0 0 T I E PSW Key 1 M W P AS CC Program Mask

RI 0 0 0 0 0 0 E

A

0 5 8 12 16 18 20 24 25 31

A Instruction Address

32 63

Bit Meaning12 One indicates a short-format PSW


Dynamic Address Translation

Virtual-Address Format

Address-Space-Control Element (ASCE)

Region-Table or Segment-Table Designation (RTD or STD)

Real-Space Designation (RSD)

Table Values

11 11 11 11 8 12

RFX RSX RTX SX PX BX

0 11 22 33 44 52 63

RX

Field MeaningRX Region index (region = 2G bytes)RFX Region first indexRSX Region second indexRTX Region third indexSX Segment index (segment = 1M bytes)PX Page index (page = 4K bytes)BX Byte index

Region-Table or Segment-Table Origin G P S X R DT DL

0 52 54 58 60 63

Bit Meaning54 (G) Subspace-group control55 (P) Private-space control56 (S) Storage-alteration-event control57 (X) Space-switch-event control58 (R) Real-space control (R = 0)60-61 (DT) Designation-type control

11 Region-first-table10 Region-second-table01 Region-third-table00 Segment-table

62-63 (DL) Designation length (× 4K bytes)

Real-Space Token Origin GPSXR

0 52 54 58 63

Bit Meaning58 (R) Real-space control (R = 1)Note: Other bits are as in RTD or STD.

TableIncre-ment

Incr. Size

Incr. En-tries

Max. Size

Max. En-tries

Max Table Maps

Regions Bytes

Region First 1-4 4KB 512 16KB 2K 8G 16E =16×260

Region Second 1-4 4KB 512 16KB 2K 4M 8P = 8×250

Region Third 1-4 4KB 512 16KB 2K 2K 4T = 4×240

Segment 1-4 4KB 512 16KB 2K 1 2G = 2×230

Page 1 2KB 256 2KB 256 — 1M = 220

57

Region-Table Entry (RTE)

Region-First-Table Entry (RFTE)

Region-Second-Table Entry (RSTE)

Region-Third-Table Entry (RTTE, FC=0)

Region-Third-Table Entry (RTTE, FC-1)

Segment-Table Entry (STE, FC=0)

Segment-Table Entry (STE, FC=1)

Region-Second-Table Origin P TF I TT TL

0 52 54 56 58 60 63

Region-Third-Table Origin P TF I TT TL

0 52 54 56 58 60 63

Segment-Table Origin FCP TF I C

R TT TL

0 52 54 56 58 60 63

Region-Frame Absolute Address (RFAA) AV ACC F F

CPIEP

I CR TT

0 33 48 52 54 56 58 60 63

Bit Meaning47 (AV) Access-control (ACC) and fetch-protection (F) validity bit48-51 (ACC) Access-control bits52 (F) Fetch-protection bit53 (FC) Format control54 (P) DAT protection bit55 (IEP) Instruction-execution-protection bit (format-1 RTTE only)56-57 (TF) Table offset (for next-lower-level table)58 (I) Invalid bit (for set of regions in RFTE or RSTE, or for region in RTTE59 (CR) Common-region bit60-61 (TT) Table-type bits (for this table)

11=Region first table10=Region second table01=Region third table

62-63 (TL) Table length (for next-lower-level table) (× 4K bytes)

Page-Table Origin FCP I C TT

0 54 58 60 63

Segment-Frame Absolute Address AV ACC F F

CPIEP

I CS TT

0 44 48 52 54 58 60 63

Bit Meaning47 (AV) Access-control (ACC) and fetch-protection (F) validity bit48-51 (ACC) Access-control bits52 (F) Fetch-protection bit53 (FC) Format control54 (P) DAT-protection bit55 (IEP) Instruction-execution-protection bit (format-1 STE only)58 (I) Segment-invalid bit59 (CS) Common-segment bit60-61 (TT) Table-type bits (for this table): 00=Segment table


Page-Table Entry (PTE)

ASN Translation

Address-Space Number (ASN)

ASN-First-Table Entry

ASN-Second-Table Entry (ASTE)

Page-Frame Real Address 0 I PIEP

/ / / / / / / /

0 52 56 63

Bit Meaning53 (I) Page-invalid bit54 (P) DAT-protection bit55 (IEP) Instruction-execution-protection bit (format-1 STE only)

ASN-First-Table Index

ASN-Second-Table Index

0 10 15

I ASN-Second-Table Origin 0 0 0 0 0 0

0 1 26 31Bit Meaning0 (I) AFX-invalid bit

Byte(Hex)

0 I Authority-Table Origin B

0 1 31

4 Authorization Index Authority-Table Length CA

RA

0 16 28 31

8 Region or Segment-Table Origin or Real-Space Token Origin

0 31

C Region- or Segment-Table Origin (Continued) G P S X R DT DL

0 20 22 26 28 31

C Real-Space-Token Origin (Continued) G P S X R

0 20 22 26 31

10 Primary-Space Access-List Origin ALL

0 1 25 31

14 ASN-Second-Table-Entry Sequence Number

0 31

18 V Linkage-Table Origin LTL

0 1 25 31

Address-Space-Control Element (ASCE=RTD/STD/RSD) Part 1

RTD or STD Part 2 (R=0)

RSD Part 2 (R=1)

Linkage-Table Designation (LTD)

59

PC-Number Translation

Program-Call Number (20-Bit)

Program-Call Number (32-Bit, Bit 44=0)

Program-Call Number (32-Bit, Bit 44=1)

Linkage-Table Entry (LTE)

18 V Linkage-First-Table Origin LFTL

0 1 24 31

1C24

Available for Programming

0 31

28 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

0 31

2C ASTEIN

0 31

303C

0 31

Byte.Bit Meaning

0.0 (I) ASX-invalid bit

0.31 (B) Base-space bit

4.30 (CA) Controlled-ASN bit

4.31 (RA) Reusable-ASN bit

10.25-31 (ALL) Access-list length (× 128 bytes)

18.0 (V) Subsystem-linkage control

18.25-31 (LTL) Linkage-table length (× 128 bytes)

18.24-31 (LFTL) Linkage-first-table length (× 256 bytes)

Linkage Index Entry Index

32 44 56 63

0 LFX LSX Entry Index

32 44 51 56 63

LFX1 1 LFX2 LSX Entry Index

32 44 51 56 63

I Entry-Table Origin ETL

0 1 26 31Bit Meaning0 (I) LX-invalid bit26-31 (ETL) Entry-table length (× 128 bytes)

Linkage-First-Table Designation (LFTD)


Linkage-First-Table Entry (LFTE)

Linkage-Second-Table Entry (LSTE)

Entry-Table Entry (ETE)

I Linkage-Second-Table Origin

0 1 24 31Bit Meaning0 (I) LFX-invalid bit

I Entry-Table Origin ETL

0 1 26 31

LSTESN

32 63Bit Meaning0 (I) LSX-invalid bit26-31 (ETL) Entry-table length (× 128 bytes)

Byte(Hex)

If Bit 10.1 (G) Is Zero

0

0 31

4 A Bits 33-62 of Entry Instruction Address P

0 1 31

If Bit 10.1 (G) Is One

0 Bits 0-31 of Entry Instruction Address

0 31

4 Bits 32-62 of Entry Instruction Address P

0 31

8 Authorization Key Mask Address-Space Number

0 16 31

C Entry Key Mask

0 16 31

10 T G RI K M E C S EK Entry Ext. Authority Index

0 3 8 12 16 31

14 ASN-Second-Table-Entry Address

0 1 26 31

18 Bits 0-31 of Entry Parameter

0 31

1C Bits 32-63 of Entry Parameter

0 31

Byte.Bit Meaning

4.0 (A) Entry addressing mode

4.31 (P) Entry problem state

10.0 (T) PC-type bit (zero: basic; one: stacking)

10.1 (G) Entry extended addressing mode

61

Access-Register Translation

Access-List-Entry Token (ALET)

Dispatchable-Unit-Control Table (DUCT)

10.2 (RI) Reserved for IBM use

10.3 (K) PSW-key control (zero: unchanged; one: replace if stacking

10.4 (M) PSW-key-mask control (zero: Or; one: replace if stacking)

10.5 (E) EAX control (zero: unchanged; one: replace if stacking)

10.6 (C) Address-space-control control

10.7 (S) Secondary-ASN control

10.8-11 (EK) Entry key

0 0 0 0 0 0 0 P ALESN Access-List-Entry Number

0 7 8 16 31Bit Meaning7 (P) Primary-list bit (zero: use DUCT; one: use primary ASTE)8-15 (ALESN) Access-list-entry sequence number

Byte(Hex)

0 Base-ASTE Origin

0 1 31

4 SA Subspace-ASTE Origin

0 31

8

0 31

C Subspace-ASTE Sequence Number

0 31

10 Dispatchable-Unit Access-List Origin ALL

0 1 25 31

14 PSW-Key Mask PSW Key RA P

0 16 24 28 31

18

0 31

1C / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

0 31

In 24-Bit or 31-Bit Addressing Mode

20

0 31

24 Bits 33-63 of Return Address

0 1 31


Access-List Entry (ALE)

Linkage-Stack Entries

Entry Descriptor

In 64-Bit Addressing Mode


0 31


0 31

28

0 31

2C Trap-Control-Block Address E

0 29 31

303C

0 31

Byte.Bit Meaning

4.0 (SA) Subspace-active bit

10.25-31 (ALL) Access-list length (× 128 bytes)

14.28 (RA) Reduced-authority bit

14.31 (P) Problem-state bit

2C.31 (E) TRAP-enabled bit

/// Available for programming

I FO P ALESN Access-List-Entry Authorization Index

(ALEAX)

0 1 6 8 16 31

32 63

ASN-Second-Table-Entry Origin (ASTEO)

64 90 95

ASN-Second-Table-Entry Sequence Number (ASTESN)

96 127

Bit Meaning0 (I) ALEN-invalid bit6 (FO) Fetch-only bit7 (P) Private bit8-15 (ALESN) Access-list-entry sequence number

U Entry Type Section ID Remaining Free Space

0 1 8 16 31

Next-Entry Size

32 48 63

63

Header Entry (Entry Type 0001001)

Trailer Entry (Entry Type 0001010)

Branch State Entry (Entry Type 0001100) and Program-Call State Entry (Entry Type 0001101)

Bit Meaning0 (U) Unstack-suppression bit1-7 Entry type:

Header entry = 0001001 binaryTrailer entry = 0001010 binaryBranch state entry = 0001100 binaryProgram-call state entry = 0001101 binaryAvailable for program use = 1xxxxxx binary

Bits 0-31 of Backward Stack-Entry Address

0 31

Bits 32-60 of Backward Stack-Entry Address B

32 61 63

Entry Descriptor (First Half)

64 95

Entry Descriptor (Second Half)

96 127

Bit Meaning63 (B) Backward stack-entry validity bit

Bits 0-31 of Forward-Section-Header Address

0 31

Bits 32-60 of Forward-Section-Header Address F

32 61 63

Entry Descriptor (First Half)

64 95

Entry Descriptor (Second Half)

96 127

Bit Meaning63 (F) Forward-section validity bit

Byte(Hex)

078

Contents of General Registers 0-15

0 63

80 PSW-Key Mask Secondary ASN Ext Authority Index Primary ASN

0 16 32 48 63

88 Bits 0-63 of Program-Status Word

0 63


TrappingTrap Control Block

In a Branch State Entry Made in 24-Bit or 31-Bit Mode

90 A Bits 33-63 of Branch Address

0 32 33 63

In a Branch State Entry Made in 64-Bit Mode

90 Bits 0-62 of Branch Address 1

0 63

In a Program-Call State Entry Made on a Call to 24-Bit or 31-Bit Mode

90 Called-Space ID 0 Numeric part of PC Number

0 32 44 63

In a Program-Call State Entry Made on a Call to 64-Bit Mode

90 Called-Space ID 1 Numeric part of PC Number

0 32 44 63

98 Modifiable Area

0 63

A0 All Zeros

0 63

A8 Bits 64-127 of Program-Status Word

0 63

B0 SASTEIN PASTEIN

0 63

B8D8

0 63

E0

118Contents of Access Registers 0-15

0 63

120 Entry Descriptor

0 63

Byte.Bit Meaning90.32 (A) Addressing mode (in branch state entry)

Byte(Hex)

0 P R

0 13 31

4

8

0 31

65

Trap Save Area

C Trap-Save-Area Address

0 1 29 31

10

0 31

14 Trap-Program Address

0 1 31

18 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

1C / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

0 31

203C

0 31

Byte.Bit Meaning0.13 (P) PSW control (zero: PSW.31 must be zero, ESA/390 PSW stored; one: z/Architecture

PSW stored)0.14 (R) General-register control (zero: bits 32-63 stored; one: bits 0-63 stored)/// Available for programming

Byte(Hex)

0 E W Zeros IL Zeros

0 1 2 13 15 31

4 Zeros

8 Bits 33-63 of Second-Operand Address of TRAP4

C Access Register 15

0 1 31

If z/Architecture PSW Stored

10 0 U 0 0 0 U U U U U U U 0 U W P AS CC Program Mask 0 0 0 0 0 0 0 E

A

14 BA Zeros

18 Bits 0-31 of Instruction Address

1C Bits 32-63 of Instruction Address

0 1 2 5 12 14 16 18 20 24 31

Trap Flags

PSW Values


Trace-Entry Formats

Identification of Trace Entries

If ESA/390 PSW Stored

10 0 U 0 0 0 U U U U U U U 1 U W P AS CC Program Mask 0 0 0 0 0 0 0 0

14 A Bits 33-63 of Instruction Address

18 Zeros

1C Zeros

0 1 2 5 12 14 16 18 20 24 31

209C

General Registers 0-15

A0 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

A4 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

A8FC

Unchanged

0 31

Byte.Bit Meaning0.0 (E) TRAP was target of EXECUTE0.1 (W) TRAP is TRAP4 (not TRAP2)0.13-14 (IL) Instruction-length code10-1F PSW values (see PSW on page 56)U Unpredictable/// Available for programming

Trace-Entry Bits Trace Entry

0-7 8-11 12-15 Type Format

00000000 Branch 1

00010000 000N Set Secondary ASN 1

00100001 Program Call 11

00100010 Program Call 21

00100001 0 Program Call 31

00100010 0 Program Call 41

00100010 100E Program Call 51



00110001 000N Program Transfer 1


00110010 0000 Program Return 1









67

Branch

F1 (Branch, RP, or TRAP2/4 to 24-Bit Mode)

F2 (Branch, RP, or TRAP2/4 to 31/64-Bit Mode)

F3 (Branch, RP, or TRAP2/4 to 64-Bit Mode)

Branch in Subspace Group (if ASN Tracing on)

F1 (in 24/31-Bit Mode)

F2 (in 64-Bit Mode)


01000001 Branch in Subspace Group 1

01000010 Branch in Subspace Group 2

01010001 0010 Mode Switch 2

01010001 0011 Mode Switch 1

01010001 1010 Mode-Switching Branch 1


01010010 0110 Mode Switch 3

01010010 1100 Branch 3


0111 0 Trace 1

0111 1 Trace 2

1 Branch

1 Format-1 and -2 entries are made when the ASN-and-LX-reuse facility (ALRF) is not enabled. Entries of formats 3-7 are made when the facility is enabled.

E Indicates, when one, that the extended-addressing-mode bit, PSW bit 31, was set to one.

N Indicates, when one, that an entry was made because of PTI or SSAIR.

0 0000 000 Bits 40-63 of Branch Address

0 8 31

1 Bits 33-63 of Branch Address

0 31

0 1010 0101 100 All Zeros Bits 0-31 of Branch Address

0 8 12 32 63

Bits 32-63 of Branch Address

64 95

Note: “Branch” is BAKR, BALR, BASR, BASSM, BSA, or BSG.

0 1000 001P Bits 9-31 of ALET A Bits 33-63 of Branch Address

0 8 32 63

0 1000 010P Bits 9-31 of ALET Bits 33-63 of Branch Address

0 8 32 63


64 95

Trace-Entry Bits Trace Entry

0-7 8-11 12-15 Type Format


Mode Switch

F1 (BASSM, BSM, PC, PR, RP, or SAM64 from 24/31-Bit to 64-Bit Mode)

F2 (BASSM, BSM, PC, PR, RP, SAM24/31 from 64-Bit to 24/31-Bit Mode)

F3 (BASSM, BSM, PC, PR, RP, SAM24/31 from 64-Bit to 24/31-Bit Mode)

Mode-Switching Branch

F1 (BASSM or RP from 64-Bit to 24/31-Bit Mode)

F2 (BASSM or RP from 24/31-Bit to 64-Bit Mode)

F3 (BASSM or RP from 24/31-Bit to 64-Bit Mode)

Program Call

F1 (in 24/31-Bit Mode, ALRF Not Enabled)

F2 (in 64-Bit Mode, ALRF Not Enabled)

F3 (in 24/31-Bit Mode, ALRF Enabled, 20-Bit PC Number)

0 1010 0010 011 All Zeros A Updated Instruction Address

0 8 12 32 63

0 1010 0010 010 All Zeros Bits 32-63 of Updated Inst. Address

0 8 12 32 63

0 1010 0100 110 All Zeros Bits 0-31 of Updated Inst. Address

0 8 12 32 63

Bits 32-63 of Updated Inst. Address

64 95

0 1010 0011 010 All Zeros A Branch Address

0 8 12 32 63


0 8 12 32 63


0 8 12 32 63


64 95

0 0100 001PSW Key

All Zeros A Bits 33-62 of Return Address P

0 8 12 32 63

0 0100 010PSW Key

All Zeros Bits 0-31 of Return Address

0 8 12 32 63

Bits 32-62 of Return Address P

64 95

0 0100 001PSW Key

0Bits 1-19 of 20-Bit PC Num-

berA Bits 33-62 of Return Address P

0 8 12 32 63

69

F4 (in 64-Bit Mode, ALRF Enabled, 20-Bit PC Number)

F5 (in 24/31-Bit Mode, ALRF Enabled, 32-Bit PC Number)

F6 (in 64-Bit Mode, ALRF Enabled, 32-Bit PC Number, Bits 0-31 of Return Address All Zeros)

F7 (in 64-Bit Mode, ALRF Enabled, 32-Bit PC Number, Bits 0-31 of Return Address Not All Zeros)

Program Return

F1 (in 24/31-Bit to 24/31-Bit Mode)

F2 (in 64-Bit to 24/31-Bit Mode)

0 0100 010PSW Key

0Bits 1-19 of 20-Bit PC

NumberBits 0-31 of Return Address

0 8 12 32 63

Bits 32-62 of Return Address P

64 95

0 0100 010PSW Key

1 00E All Zeros A Bits 33-62 of Return Address P

0 8 12 16 32 63

32-Bit PC Number

64 95

0 0100 010PSW Key

1 01E All Zeros Bits 32-62 of Return Address P

0 8 12 16 32 63

32-Bit PC Number

64 95

0 0100 011PSW Key

1 11E All Zeros Bits 0-31 of Return Address

0 8 12 16 32 63

Bits 32-62 of Return Address P 32-Bit PC Number

64 96 127

0 0110 010PSW Key

0 000 New PASN A Bits 33-62 of Return Address P

0 8 12 16 32 63

A Bits 33-63 of Updated Inst. Address

64 95

0 0110 010PSW Key


0 8 12 16 32 63


64 95


F3 (in 64-Bit to 24/31-Bit Mode)

F4 (in 24/31-Bit to 64-Bit Mode)

F5 (in 64-Bit to 64-Bit Mode)


F7 (in 24/31-Bit to 64-Bit Mode)


0 0110 011PSW Key


0 8 12 16 32 63

Updated Instruction Address

64 127

0 0110 010PSW Key

1 000 New PASN Bits 32-62 of Return Address P

0 8 12 16 32 63

A Bits 33-63 of Updated Inst. Address

64 95

0 0110 010PSW Key


0 8 12 16 32 63


64 95

0 0110 011PSW Key


0 8 12 16 32 63

Updated Instruction Address

64 127

0 0110 011PSW Key

1 100 New PASN Bits 0-31 of Return Address

0 8 12 16 32 63

Bits 32-62 of Return Address PA Updated Instruction Address

64 96 127

0 0110 011PSW Key


0 8 12 16 32 63

Bits 32-62 of Return Address P Bits 32-63 of Updated Inst. Address

64 96 127

71


Program Transfer

F1 (in 24/31-Bit Mode)

F2 (in 64-Bit Mode, Bits 0-31 of R2 All Zeros)

F3 (in 64-Bit Mode, Bits 0-31 of R2 Not All Zeros)

Set Secondary ASN

F1

Trace

F1 (TRACE)

0 0110 100PSW Key


0 8 12 16 32 63

Bits 32-62 of Return Address P Bits 0-31 of Updated Inst. Address

64 96 127


128 159

0 0110 001PSW Key

0 00N New PASN Bits 32-63 of R2 Before

0 8 12 16 32 63

0 0110 001PSW Key


0 8 12 16 32 63

0 0110 001PSW Key


0 8 12 16 32 63

Bits 32-63 of R2 Before

64 95

0 0010 0000 0000 00N New SASN

0 8 16 31

0 111 N 0 0000 000 TOD-Clock Bits 16-63

0 4 8 16 63

TRACE Operand (when CR0 bit 32 is zero)

(R1) - (R3)Model-Dependent Value(when CR0 bit 32 is one)

TRACE Operand bits 16-31 (when CR0 bit 32

is one)

64 80 96 4N+16


F2 (TRACG)

Operand of Store Clock and Store Clock Fast

Note: Bit 51 of the TOD clock corresponds to one microsecond.

Operand of Store Clock Extended

Note: Bit 51 of the TOD clock (bit 59 of the operand) corresponds to one microsec-ond.

0 111 N 1Epoch Ix. (bits 1-7)

TOD-Clock Bits 0-47

0 4 89 16 63

TOD-Clock Bits 48-79

TRACG Operand (when CR0 bit 32 is zero)

Model-Dependent Value(when CR0 bit 32 is one)

TRACG Operand bits 16-31 (when CR0 bit 32

is one)

64 96 127

(R1) - (R3)

128 8N+24

Bit Meaning

4-7 (N) One less than the number of registers in the trace entry.

Bits 0-63 ofTime-of-Day (TOD) Clock

0 63

Epoch Index Time-of-Day (TOD) Clock Programmable

Field

0 8 112 127

73

Transaction Diagnostic Block (TDB) TBEGIN-specified TDB is the operand of the TBEGIN instruction when B1 0;Program-interruption TDB is at real locations 6,144 - 6,399.

Byte

0 Format Flags TND

8 Transaction Abort Code1

16 Conflict Token

24 Aborted Transaction Instruction Address

32 EAID2 DXC2 Program Interruption Identification2

40 Translation-Exception Identification2

48 Breaking-Event Address2

56Reserved

128

248

General Registers at Abort

0 8 16 32 48 63

Explanation:1 Transaction abort codes:

2 – External interruption4 – Non-filtered program interruption5 – Machine-check interruption6 – I/O interruption7 – Fetch overflow8 – Store overflow9 – Fetch conflict

10 – Store conflict

11 – Restricted instruction12 – Filtered program interruption13 – Nesting depth exceeded14 – Cache fetch-related condition15 – Cache store-related condition16 – Cache other condition

255 – Miscellaneous condition>255 – TABORT instruction

2 Field is stored only in the TBEGIN-specified TDB; otherwise, the field is reserved. The program interruption identification is only stored for program-interruption conditions. The EAID and translation-exception identification are stored only for access-list-controlled or DAT protection, ASCE-type, page translation, region-first translation, region-second translation, region-third translation, and segment translation program-interruption conditions. The DXC is stored only for data program-exception conditions.

TND Transaction nesting depth


Guarded-Storage Facility Registers and Parameters

Guarded-Storage-Designation (GSD) Register

Guarded-Storage Control Block

Guarded-Storage-Event Parameter List

Guarded-Storage Origin (GSO)

0 31

GSO (continued) / / / / / / / / / / / / / / GLS / / GSC

32 53 56 58 63

Bit Meaning0-J Guarded-storage origin (GSO), where J is 64-GSC53-55 Guarded-load shift (GLS); valid values are 0-458-63 Guarded-storage characteristic (GSC); valid values are 25-56

Reserved

0 63

Guarded-Storage-Designation (GSD) Register (see above)

64 127

Guarded-Storage-Section-Mask (GSSM) Register

128 191

Guarded-Storage-Event-Parameter-List-Address (GSEPLA) Register (see below)

192 255

Reserved

GSEAM GSECI GSEAI

0 0 0 0 0 0 E BTX

CX

0 0 0 0 0IN

0 T AS AR

Reserved

Guarded-Storage-Event Handler Address (GSEHA)

Guarded-Storage-Event Instruction Address (GSEIA)

Guarded-Storage-Event Operand Address (GSEOA)

Guarded-Storage-Event Intermediate Result (GSEIR)

Guarded-Storage-Event Return Address (GSERA)

Bits Meaning0-7 Reserved8-15 Guarded-storage-event addressing mode (GSEAM)

14 - Extended-addressing mode (E)15 - Basic Addressing mode (B)

16-23 Guarded-storage-event cause indication (GSECI)16 - CPU was in the transactional-execution mode (TX)17 - CPU was in the constrained transactional-execution mode (CX)

23 - Instruction causing the event; 0-LGG, 1=LLGFSG24-31 Guarded-storage-event access information (GSEAI)

25 - DAT mode (copy of PSW bit 5)26-27 - Address-space indication (copy of PSW bits 16-17)28-31 - AR number (when in the AR mode; otherwise unpredictable

32-63 Reserved64-127 Guarded-storage-event handler address (GSEHA)128-191 Guarded-storage-event instruction address (GSEIA)192-255 Guarded-storage-event operand address (GSEOA)256-319 Guarded-storage-event intermediate result (GSEIR)320-383 Guarded-storage-event return address (GSERA)

75

Operation-Request Block (ORB)

Command-Mode ORB

Transport-Mode ORB

Word

0 Interruption Parameter

1 Key S C M Y F P I A U B H T LPM L D 0 0 0 0 0 X

2 0 Channel-Program Address

3 CSS Priority Reserved CU Priority Reserved

4 Reserved

5 Reserved

6 Reserved

7 Reserved

0 8 16 24 31

Word


1 Key 0 0 0 0 0 0 0 0 0 B 0 0 LPM 0 0 0 0 0 0 0 X

2 0 Channel-Program Address

3 CSS Priority Reserved Reserved for Pgm. Reserved

4 Reserved

5 Reserved

6 Reserved

7 Reserved

0 8 16 24 31

Word.Bit Meaning1.0-3 (Key) Subchannel key1.4 (S) Suspend control1.5 (C) Streaming-mode control1.6 (M) Modification control1.7 (Y) Synchronization control1.8 (F) CCW-format control1.9 (P) Prefetch control1.10 (I) Initial-status-interruption control1.11 (A) Address-limit-checking control1.12 (U) Suppress-suspended-interruption control1.13 (B) Channel-Program Type1.14 (H) Format-2-IDAW control1.15 (T) 2K-IDAW control1.16-23 (LPM) Logical-path mask1.24 (L) Incorrect-length-suppression mode1.25 (D) Modified-CCW-indirect-data-addressing control1.31 (X) ORB-extension control3.0-7 Channel-subsystem priority3.16-23 Control-unit priority


Channel-Command Word (CCW)

Format-0 CCW

Format-1 CCW

Indirect-Data-Address Word (IDAW)

Format-1 IDAW

Format-2 IDAW

Command Code Data Address

0 8 31

Flags Byte Count

32 40 48 63

Bit Meaning32 (CD) Causes use of data-address portion of next CCW33 (CC) Causes use of command code and data address of next CCW34 (SLI) Causes suppression of possible incorrect-length indication35 (Skip) Suppresses transfer of information to main storage36 (PCI) Causes an intermediate-interruption condition to occur37 (IDA) Causes bits 8-31 of CCW to specify location of first IDAW38 (Suspend) Causes suspension before execution of this CCW39 (MIDA) Causes bits 8-31 of CCW to specify location of first MIDAW

Command Code Flags Byte Count

0 8 16 31

0 Data Address

32 63

Bit Meaning8 (CD) Causes use of data-address portion of next CCW9 (CC) Causes use of command code and data address of next CCW10 (SLI) Causes suppression of possible incorrect-length indication11 (Skip) Suppresses transfer of information to main storage12 (PCI) Causes an intermediate-interruption condition to occur13 (IDA) Causes bits 33-63 of CCW to specify location of first IDAW14 (Suspend) Causes suspension before execution of this CCW15 (MIDA) Causes bits 33-63 of CCW to specify location of first MIDAW

0 Data Address

0 1 31

Bits 0-31 of Data Address

0 31


32 63

77

Modified-CCW-Indirect-Data-Address Word (MIDAW)

Transport Control Word (TCW)

Reserved

0 31

Reserved Flags Count

32 40 48 63


64 95


96 127

Bit Meaning40 Last MIDAW41 Skip42 Data-transfer-interruption control43-47 Reserved

Word

0 F 0 0 0 0 0 0 Flags

1 Reserved TCCBL R W Reserved

2Output-Data Address

3

4Input-Data Address

5

6Transport-Status-Block Address

7

8Transport-Command-Control-Block Address

9

10 Output Count

11 Input Count

12

Reserved

14

15 Interrogate-TCW Address

0 2 8 14 1516 24 31

Word.Bit Meaning0.0-1 Format0.13 Input transport-indirect-data addressing (TIDA)0.14 Transport-command-control-block TIDA0.15 Output TIDA0.16-17 TIDAW Format1.8-13 (TCCBL) Transport-Command-Control-Block Length1.14 (R) Read Operations1.15 (W) Write Operations


Transport-Indirect-Data-Address Word (TIDAW)

Transport Command Control Block (TCCB)

Transport Command Area Header (TCAH)

Flags Reserved

0 8 31

Count

32 48 63


64 95


96 127

Bit Meaning0 Last TIDA1 Skip2 Data-transfer-interruption control3 (TTIC) TIDAW Transfer In Channel4 Insert CBC Control5-7 Reserved

Word

0 Transport-Command-Area Header(TCAH)3

4

Transport-Command Area(TCA)

N

N+1Transport-Command-Area Trailer

(TCAT)N+(2 or 3)

0 31

Word

0 Format Reserved

1 Reserved TCAL

2 Service-Action Code Reserved Priority

3 Reserved

0 8 16 24 31

Word.Bit Meaning1.24-31 (TCAL) Transport-Command-Area Length

79

Transport-Command Area (TCA) and Transport-Command-Area Extension (TCAX)

Device-Command Word (DCW)

Interrogate TCA

Word

0DCW

1

2 DCWor

Control Data for Previous DCW

DCWor

Control Data for Previous DCWN

Y Reserved (TCAX only; not present in TCA)

0 31

Command Code Flags Reserved Control-Data Count

0 8 16 24 31

Count

32 63

Bit Meaning9 (CC) Causes use of next DCW10 (SLI) Suppresses incorrect-length indication

Word

0Interrogate DCW

1

2

Interrogate Data

N

0 31


Interrogate Data

Transport Command Area Trailer (TCAT)

CBC-Offset Block (COB)

Word

0 Format RC RCQ LPM

1 PAM PIM Timeout

2 Flags Reserved

3 Reserved

4Time

5

6Program Identifier

7

8

Program-Dependent Data

N

0 8 16 24 31

Word.Bit Meaning0.8-15 (RC) Reason code

0 Interrogate reason not specified1 Timeout

0.16-23 (RCQ) Reason-code qualifier0 Interrogate reason qualifier not specified1 Primary2 Secondary

0.24-31 (LPM) Logical-path mask1.0-7 (PAM) Path-available mask1.8-15 (PIM) Path-installed mask2.0-7 Flags

0 Multipath mode1 Program path recovery2 Critical

Word

0 Reserved

1 Write Count or Transport Count

2 Read Count (or not present)

0 31

Word

0 CBC Offset 0

1 CBC Offset 1

2 ...

N CBC Offset N

Y Reserved

0 31

81

Transport Status Block (TSB)

Transport Status Header (TSH)

I/O-Status TSA

Word

0Transport-Status Header

2

3

Transport-Status Area

15

0 31

Word

0 Length Flags DCW Offset

1 Count

2 Reserved

0 8 16 31

Word.Bit Meaning0.8 DCW-offset field valid0.9 Count field valid0.10 Cache miss0.11 Time fields valid0.13-15 Transport-Status Area (TSA) Format

0 TSA contents have no meaning1 I/O-status TSA2 Device-detected-program-check TSA3 Interrogate TSA

Word

0 Device Time

1 Defer Time

2 Queue Time

3 Device-Busy Time

4 Device-Active-Only Time

5

Additional Data(if present)

12

0 31


Device-Detected-Program-Check TSA Word

0 Reserved Reason Code

1

Reason-Code Qualifier

4

5

Sense Data(if present)

12

0 24 31

Word.Bit Meaning0.24-31 (RC) Reason Code

0 No information1 TCCB transport failure

(RCQ) Reason-code-qualifier byte 0 (1.0-7)0 No additional information1 TCCB transport size error2 TCCB CBC error

2 Invalid CBC detected on output dataRCQ word 0: Offset of first output-data byte for which error was detectedRCQ word 1: Offset of last output-data byte for which error was detected

3 Incorrect TCCB length specificationRCQ byte 0

0 No additional information1 TCAL value not 8 greater than TCW TCCBL value2 TCAL value is less than 20 or greater than 252

4 TCAH specification errorRCQ byte 0

0 No additional information1 Format field specification error2 Reserved field specification error3 Service-action-code field specification error

5 DCW specification errorRCQ byte 0

0 No additional information1 Reserved field specification error2 Flags field command-chaining specification error3 Control-data-count field specification error4 TCOB location error5 TCOB duplication error6 TCOB multiple-count error7 TCOB direction error8 TCOB chaining error9 TCOB count-specification error10 TTE location error11 TTE duplication error12 TTE CD-count specification error13 TTE count specification error14 TTE direction error:15 TTE chaining error16 TCAX specification error

6 Transfer-direction specification errorRCQ byte 0

0 No additional information1 Read-direction specification error2 Write-direction field specification error3 Read-write-conflict specification error

83

Interrogate TSA

7 Transport-count specification errorRCQ byte 0

0 No additional information1 Read-count specification error2 Write-count specification error

8 Two I/O operations activeRCQ: No additional information

9 CBC-offset specification errorRCQ word 0: Byte offset of COB CBC-offset entry

Word

0 Format Flags Control-Unit Status Device Status

1 Operation State Reserved

2

State-Dependent Information

4

5 Device-Level Identifier

6

Device-Dependent Information

12

0 8 16 24 31

Word.Bit Meaning0.8 Control-unit state valid0.9 Device-state valid0.10 Operation-state valid0.16-23 (CS) Control-unit state

0 Busy1 Recovery2 Interrogate maximum

0.24-31 (DS) Device-unit state0 Path-Group identification (in state-dependent-information field)1 Long busy2 Recovery

1.0-7 (OS) Operation state0 No I/O operation present.1 An I/O operation is present and executing.2 An I/O operation is present and awaiting completion of another operation ini-

tiated by another configuration.3 An I/O operation is present and awaiting completion of another operation ini-

tiated for the same device extent.4 An I/O operation is present and waiting to perform a device-dependent oper-

ation.


Subchannel-Information Block (SCHIB)

Path-Management-Control Word (PMCW)

Word

0

Path-Management-Control Word

1

2

3

4

5

6

7

Subchannel-Status Word(See “Command-Mode Subchannel-Status Word (SCSW)” on page 86.)8

9

10 Model-Dependent Area /Measurement-Block Address11

12 Model-Dependent Area

0 31

Word


1 0 0 ISC 0 0 0 E LM MM D T V Device Number

2 LPM PNOM LPUM PIM

3 MBI POM PAM

4 CHPID-0 CHPID-1 CHPID-2 CHPID-3

5 CHPID-4 CHPID-5 CHPID-6 CHPID-7

6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F X S

0 8 16 24 31

Word.Bit Meaning1.2-4 (ISC) Interruption-subclass code1.8 (E) Subchannel enabled1.9-10 (LM) limit mode

00 No Checking01 Data address must be limit10 Data address must be < limit11 Reserved

1.11-12 (MM) Measurement-mode enable00 Neither mode enabled01 Device-connect-time-measurement enabled10 Measurement-block-update enabled11 Both modes enabled

85

Interruption-Response Block (IRB)

Command-Mode Subchannel-Status Word (SCSW)

1.13 (D) Multipath mode1.14 (T) Timing facility available1.15 (V) Device number valid2.0-7 (LPM) Logical-path mask2.8-15 (PNOM) Path-not-operational mask2.16-23 (LPUM) Last-path-used mask2.24-31 (PIM) Path-installed mask3.0-15 (MBI) Measurement-block index3.16-23 (POM) Path-operational mask3.24-31 (PAM) Path-available mask4.0-7 (CHPID-0) Channel-path ID for logical path 0 (typical)6.29 (F) Measurement-block-format control6.30 (X) Extended-measurement-word-mode enable6.31 (S) Concurrent sense

Word

0

Subchannel-Status Word1

2

3

Extended-Status Word

4

5

6

7

815

Extended-Control Word

1623

Extended-Measurement Word

0 31

Word

0 Key S L CC F P I X U Z E N 0 FC AC SC

0 4 5 6 8 13 17 20 27 31

1 CCW Address

2 Device Status Subchannel Status Byte Count

0 8 16 31

Word.Bit Meaning0.0-3 (Key) Subchannel key0.4 (S) Suspend control0.5 (L) Extended-status-word format (logout stored)0.6-7 (CC) Deferred condition code

00 Normal I/O interruption01 Status in SCSW10 Reserved11 Path not operational

0.8 (F) CCW-format control0.9 (P) Prefetch control

Subchannel Control


Transport-Mode Subchannel-Status Word (SCSW)

0.10 (I) Initial-status-interruption control0.11 (X) IRB-format control0.12 (U) Suppress-suspended-interruption control0.13 (Z) Zero condition code0.14 (E) Extended control (information stored in ECW of IRB)0.15 (N) Path not operational (PNOM nonzero)0.17-19 (FC) Function control

17 (40) Start, 18 (20) Halt, 19 (10) Clear0.20-26 (AC) Activity control

20 (08) Resume pending 24 (80) Subchannel active21 (04) Start pending 25 (40) Device active22 (02) Halt pending 26 (20) Suspended23 (01) Clear pending

0.27-31 (SC) Status control27 (10) Alert 30 (02) Secondary28 (08) Intermediate 31 (01) Status pending29 (04) Primary

2.0-15 Device status (0-7) Subchannel status (8-15)0 (80) Attention 8 (80) Program-controlled interruption1 (40) Status modifier 9 (40) Incorrect length2 (20) Control-unit end 10 (20) Program check3 (10) Busy 11 (10) Protection check4 (08) Channel end 12 (08) Channel-data check5 (04) Device end 13 (04) Channel-control check6 (02) Unit check 14 (02) Interface-control check7 (01) Unit exception 15 (01) Chaining check

Word

0 Key 0 L CC FMT X Q 0 E N 0 FC AC SC

0 4 5 6 8 11 13 17 20 27 31

1 TCW Address

2 Device Status Subchannel Status FCX Status SCHXS

0 8 16 24 31

Word.Bit Meaning0.0-3 (Key) Subchannel key0.5 (L) Extended-status-word format (logout stored)0.6-7 (CC) Deferred condition code

00 Normal I/O interruption01 Status in SCSW10 Reserved11 Path not operational

0.8-10 (FMT) Format0.11 (X) IRB-format control0.12 (Q) Interrogate complete0.14 (E) Extended control (information stored in ECW of IRB)0.15 (N) Path not operational (PNOM nonzero)0.17-19 (FC) Function control

17 (40) Start, 18 (20) Halt, 19 (10) Clear0.20-26 (AC) Activity control

21 (04) Start pending 23 (01) Clear pending22 (02) Halt pending 25 (40) Device active

0.27-31 (SC) Status control27 (10) Alert 30 (02) Secondary28 (08) Intermediate 31 (01) Status pending29 (04) Primary

Subchannel Control

87

Extended-Status Word (ESW)See chart on page 90 to determine the appropriate ESW format.

Format-0 ESW

2.0-15 Device status (0-7) Subchannel status (8-15)0 (80) Attention 8 (80) —1 (40) — 9 (40) Incorrect length2 (20) Control-unit end 10 (20) Program check3 (10) Busy 11 (10) Protection check4 (08) Channel end 12 (08) Channel-data check5 (04) Device end 13 (04) Channel-control check6 (02) Unit check 14 (02) Interface-control check7 (01) Unit exception 15 (01) Channel-subsystem retry failed

2.16-23 FCX status (16-23)23 (01) TSB valid

2.24-31 (SCHXS) Subchannel-extended status24 (80) (F) Interrogate failed25-31 (SESQ) SCHSX qualifier

0 No status available.1 Storage-request limit exceeded.2 Program check when not an interrogate operation, TCW read/write

data count not zero, and CE only or CE+DE only status received.3 Transport mode not supported by the I/O device.4 Transport mode not supported by the selected channel path.6 Program check on TCW.7 Device-detected program check condition due to indeterminate

cause.8 Device-detected program check.9 Program check on TIDAW - failing-storage-address (FSA) valid in

ESW (see below) and contains TIDAW address.32 TCW access exception - FSA field valid and contains TCW

address.33 TSB access exception - FSA field valid and contains TSB address.34 TCCB access exception - FSA field valid and contains TCCB

address.35 TIDAW access exception - FSA field valid and contains TIDAW

address.36 Data access exception - FSA field valid and contains address of

data.64 Invalid CBC error on read data.66 Link protocol error condition.67 Device-level recovery operation failed.68 IFCC due to failed device-level recovery operation - program, pro-

tection, or data check may also be set in subchannel status.70 Invalid CBC on status portion of transport response from device.71 Invalid CBC on TSB transported from device.Note: If FSA field valid for cases other than noted above, FSA field con-

tains address of current TCW.

Word

0 Subchannel Logout

1 Extended-Report Word

2Failing-Storage Address

3

4 Secondary-CCW Address

0 31


Format-0 ESW Word 0 (Subchannel Logout)

Format-0 ESW Word 1 (Extended-Report Word)

Format-1 ESW Word 01



0 ESF LPUM R FVF SA TC D E A SC

0 1 8 16 22 24 26 28 31

Bit Meaning1-7 (ESF) Extended-status flags (1 key check, 2 measurement-block program check, 3

measurement-block data check, 4 measurement-block protection check, 5 CCW check, 6 IDAW check, 7:0)

8-15 (LPUM) Last-path-used mask16 (R) Ancillary Report17-21 (FVF) Field-validity flags (17 LPUM, 18 TC, 19 SC, 20 device status, 21 CCW address)22-23 (SA) Storage-access code (00 access type unknown, 01 read, 10 write, 11 read back-

ward)24-25 (TC) Termination code (00 halt signal issued, 01 stop, stack, or normal termination, 10

clear signal issued)26 (D) Device status check27 (E) Secondary error28 (A) I/O-error alert29-31 (SC) Sequence code

0 L E A P T F S C R SCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 3 8 10 16 31

Bit Meaning1 (L) Request logging only2 (E) Extended-subchannel-logout pending3 (A) Authorization check4 (P) Path-verification-required5 (T) Channel-path timeout6 (F) Failing-storage-address validity7 (S) Concurrent sense8 (C) Secondary-CCW-address validity9 (R) Failing-storage-address format (zero: 1-31 of word 2; one: words 2 and 3)10-15 (SCNT) Concurrent-sense count

0 0 0 0 0 0 0 0 LPUM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 8 16 31

Bit Meaning8-15 (LPUM) Last-path-used mask

1. Word 1 is the same as word 1 of a format-0 ESW. Words 2, 3, and 4 arezeros.

0 0 0 0 0 0 0 0 LPUM DCTI

0 8 16 31

Bit Meaning8-15 (LPUM) Last-path-used mask16-31 (DCTI) Device-connect-time interval

0 0 0 0 0 0 0 0 LPUM Unpredictable

0 8 16 31

Bit Meaning8-15 (LPUM) Last-path-used mask

89

Information Stored in ESW

Extended-Control Word (ECW)

Subchannel Conditions under which ESW Is Stored by Test Subchan-nel Instruction

Extended-Status Word (ESW)Subchannel-Status Word

Path-Management-Con-trol Word

Device-Connect-

Time Mea-surement-

Mode Active

Status-Control Field

L Bit

Sus-pended

BitTiming-

Facility Bit

Device-Connect-

Time Mea-surement-

Mode Enable Bit Format

Contents Word 0 Byte

A I P S X 0 1 2 3- - - - 0 - * * * No / Yes U * * * *

* * 0 0 1 1 * * * No / Yes 0 R R R R* * 1 * 1 1 * * * No / Yes 0 R R R R1 0 0 1 1 1 * * * No / Yes 0 R R R R

0 0 0 0 1 0 * * * No / Yes U * * * *0 0 0 1 1 0 * * * No / Yes 3 Z M * *1 0 0 * 1 0 * * * No / Yes 3 Z M * *

* * 1 * 1 0 * 0 * No / Yes 1 Z M Z Z* * 1 * 1 0 * 1 0 No / Yes 1 Z M Z Z* * 1 * 1 0 * 1 1 No 1 Z M Z Z* * 1 * 1 0 * 1 1 Yes 2 Z M D D

0 1 0 0 1 0 0 * * No / Yes U * * * *0 1 0 0 1 0 1 0 * No / Yes 1 Z M Z Z0 1 0 0 1 0 1 1 0 No / Yes 1 Z M Z Z0 1 0 0 1 0 1 1 1 No 1 Z M Z Z0 1 0 0 1 0 1 1 1 Yes 2 Z M D D

0 0 0 1 1 1These combinations do not occur.1 1 0 0 1 0

* 1 0 1 1 *Bit Meaning- Not meaningful.* Bits may be zeros or ones.A Alert status.D Accumulated device-connect-time-interval (DCTI) value stored in bytes 2 and 3.I Intermediate status.L Extended-status-word format.M Last-path-used mask (LPUM) stored in byte 1.P Primary status.R Subchannel-logout information stored in bytes 0-3.S Secondary status.U No format defined.X Status pending.Z Bits are stored as zeros.

SCSW Bits ERW Bit 7 ERW Bits 10-15 ECW Words 0-75 14

0 0 0 Zeros Unpredictable0 1 1 Number of concurrent-

sense bytesa

a. The contents of the ECW are specified by bits 5 and 14 of word 0 of the SCSW. The combinationof SCSW bit 5 zero, SCSW bit 14 one, and ERW bit 7 zero does not occur.

Concurrent-sense informationa

1 0 0 Zeros Unpredictable1 1 0 Zeros Model-dependent information1 1 1 Number of concurrent-

sense bytesConcurrent-sense information


Extended-Measurement Word

Format 0 Measurement Block

Word

0 Device-Connect Time

1 Function-Pending Time

2 Device-Disconnect Time

3 Control-Unit-Queuing Time


5 Device-Busy Time

6 Initial-Command-Response Time

7 Reserved

0 31

Word

0 SSCH + RSCH Count Sample Count






6 Device-Busy Time


0 16 31

91

Format 1 Measurement Block

Channel-Report Word (CRW)

Error-Recovery Codes

Word

0 SSCH + RSCH Count

1 Sample Count






7 Device-Busy Time


9 Interrupt Delay Time

10 I/O Priority Delay Time

11

15

Reserved

0 31

0 S R C RSC A 0 ERC Reporting-Source ID

0 4 8 10 16 31

Bit Meaning1 (S) Solicited CRW2 (R) Overflow (one or more CRWs lost)3 (C) Chaining (meaningless if bit 2 is one)4-7 (RSC) Reporting-source code (see Reporting-Source table)8 (A) Ancillary report10-15 (ERC) Error-recovery code (see Error-Recovery-Code table)16-31 Reporting-source ID (see Reporting-Source table)

ERC Condition

0 0 0 0 0 1 Available

0 0 0 0 1 0 Initialized

0 0 0 0 1 1 Temporary error

0 0 0 1 0 0 Installed parameters initialized

0 0 0 1 0 1 Terminal

0 0 0 1 1 0 Permanent error with facility not initialized

0 0 0 1 1 1 Permanent error with facility initialized

0 0 1 0 0 0 Installed parameters modified


Reporting Source

The reporting-source-ID format depends on the RSC field of the channel-report word, as follows:

I/O Command Codes

Standard Command-Code Assignments (CCW and DCW Bits 0-7)

Standard Meanings of Bits of First Sense Byte

RSC Reporting Source Reporting-Source ID

0 0 1 0 Monitoring facility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 Subchannel (first or only CRW) X X X X X X X X X X X X X X X X0 0 1 1 Subchannel (chained CRW) 0 0 0 0 0 0 0 0 0 0 S S 0 0 0 00 1 0 0 Channel path 0 0 0 0 0 0 0 0 Y Y Y Y Y Y Y Y1 0 0 1 Configuration-alert facility 0 0 0 0 0 0 0 0 Y Y Y Y Y Y Y Y1 0 1 1 Channel subsystem 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

S = Subchannel-set identifier (SSID) when the MSS facility is installed and the CRW is chained immediately following a CRW for a subchannel.

X = Subchannel numberY = Channel-path ID (CHPID)

x x x x 0 0 0 0 Invalid Command mmmm 0 1 0 0 Sensemmmm mm0 1 Write (a) 0 0 0 0 0 1 0 0 — Basic Sensemmmm mm1 0 Read (a) 1 1 1 0 0 1 0 0 — Sense ID0 0 0 0 0 0 1 0 — Read IPL x x x x 1 0 0 0 Transfer in channel (c)mmmm mm1 1 Control 0 0 0 0 1 0 0 0 Transfer in channel (d)0 0 0 0 0 0 1 1 — Control no operation mmmm 1 0 0 0 Invalid command (e)0 1 mm 0 0 0 0 Transport (b) mmmm 1 1 0 0 Read backwards (f)

x – Bit Ignored a May designate control data in a DCWm – Modifier bit for specific type of I/O b DCW only

device c Format-0 CCWd Format-1 CCWe Format-1 CCW and nonzero m bitf CCW only

Bit Designation Bit Designation

0 Command reject 4 Data check

1 Intervention required 5 Overrun

2 Bus-out check 6 (Device dependent)

3 Equipment check 7 (Device dependent)

93

Hexadecimal and Decimal ConversionUse the following figure to preform hexadecimal and decimal conversions.

From hex: locate each hex digit in its corresponding column position and note the dec-imal equivalents. Add these to obtain the decimal value.

From decimal: (1) locate the largest decimal value in the table that will fit into the dec-imal number to be converted, and (2) note its hex equivalent and hex column position. (3) Find the decimal remainder. Repeat the process on this and subsequent remain-ders.

Note: Hexadecimal equivalents of all numbers from 0 to 255 are listed in “Character Assignments” on page 98.


W

ord

Halfw

ord

Hal

fwor

d

Byte

Byte

Byte

Byte

Bits

:01

2345

6701

2345

6701

2345

6701

2345

67

Hex

Dec

Hex

Dec

Hex

Dec

Hex

Dec

Hex

Dec

Hex

Dec

Hex

Dec

Hex

Dec

00

00

00

00

00

00

00

00

126

8,43

5,45

61

16,7

77,2

161

1,04

8,57

61

65,5

361

4,09

61

256

116

11

253

6,87

0,91

22

33,5

54,4

322

2,09

7,15

22

131,

072

28,

192

251

22

322

23

805,

306,

368

350

,331

,648

33,

145,

728

319

6,60

83

12,2

883

768

348

33

41,

073,

741,

824

467

,108

,864

44,

194,

304

426

2,14

44

16,3

844

1,02

44

644

45

1,34

2,17

7,28

05

83,8

86,0

805

5,24

2,88

05

327,

680

520

,480

51,

280

580

55

61,

610,

612,

736

610

0,66

3,29

66

6,29

1,45

66

393,

216

624

,576

61,

536

696

66

71,

879,

048,

192

711

7,44

0,51

27

7,34

0,03

27

458,

752

728

,672

71,

792

711

27

78

2,14

7,48

3,64

88

134,

217,

728

88,

388,

608

852

4,28

88

32,7

688

2,04

88

128

88

92,

415,

919,

104

915

0,99

4,94

49

9,43

7,18

49

589,

824

936

,864

92,

304

914

49

9A

2,68

4,35

4,56

0A

167,

772,

160

A10

,485

,760

A65

5,36

0A

40,9

60A

2,56

0A

160

A10

B2,

952,

790,

016

B18

4,54

9,37

6B

11,5

34,3

36B

720,

896

B45

,056

B2,

816

B17

6B

11C

3,22

1,22

5,47

2C

201,

326,

592

C12

,582

,912

C78

6,43

2C

49,1

52C

3,07

2C

192

C12

D3,

489,

660,

928

D21

8,10

3,80

8D

13,6

31,4

88D

851,

968

D53

,248

D3,

328

D20

8D

13E

3,75

8,09

6,38

4E

234,

881,

024

E14

,680

,064

E91

7,50

4E

57,3

44E

3,58

4E

224

E14

F4,

026,

531,

840

F25

1,65

8,24

0F

15,7

28,6

40F

983,

040

F61

,440

F3,

840

F24

0F

158

76

54

32

1

95

Powers of 2 and 16 m n 2m and 16n Symbol0 0 11 22 43 84 1 165 326 647 1288 2 2569 512

10 1 024 K (kilo)11 2 04812 3 4 09613 8 19214 16 38415 32 76816 4 65 53617 131 07218 262 14419 524 28820 5 1 048 576 M (mega)21 2 097 15222 4 194 30423 8 388 60824 6 16 777 21625 33 554 43226 67 108 86427 134 217 72828 7 268 435 45629 536 870 91230 1 073 741 824 G (giga)31 2 147 483 64832 8 4 294 967 29633 8 589 934 59234 17 179 869 18435 34 359 738 36836 9 68 719 476 73637 137 438 953 47238 274 877 906 94439 549 755 813 88840 10 1 099 511 627 776 T (tera)41 2 199 023 255 55242 4 398 046 511 10443 8 796 093 022 20844 11 17 592 186 044 41645 35 184 372 088 83246 70 368 744 177 66447 140 737 488 355 32848 12 281 474 976 710 65649 562 949 953 421 31250 1 125 899 906 842 624 P (peta)51 2 251 799 813 685 24852 13 4 503 599 627 370 49653 9 007 199 254 740 99254 18 014 398 509 481 98455 36 028 797 018 963 96856 14 72 057 594 037 927 93657 144 115 188 075 855 87258 288 230 376 151 711 74459 576 460 752 303 423 48860 15 1 152 921 504 606 846 976 E (exa)61 2 305 843 009 213 693 95262 4 611 686 018 427 387 90463 9 223 372 036 854 775 808


Note: No Système international d'unités (SI) symbols greater than Y (yotta) are defined.

64 16 18 446 744 073 709 551 61665 36 893 488 147 419 103 23266 73 786 976 294 838 206 46467 147 573 952 589 676 412 92868 17 295 147 905 179 352 825 85669 590 295 810 358 705 651 71270 1 180 591 620 717 411 303 424 Z (zetta)71 2 361 183 241 434 822 606 84872 18 4 722 366 482 869 645 213 69673 9 444 732 965 739 290 427 39274 18 889 465 931 478 580 854 78475 37 778 931 862 957 161 709 56876 19 75 557 863 725 914 323 419 13677 151 115 727 451 828 646 838 27278 302 231 454 903 657 293 676 54479 604 462 909 807 314 587 353 08880 20 1 208 925 819 614 629 174 706 176 Y (yotta)81 2 417 851 639 229 258 349 412 35282 4 835 703 278 458 516 698 824 70483 9 671 406 556 917 033 397 649 40884 21 19 342 813 113 834 066 795 298 81685 38 685 626 227 668 133 590 597 63286 77 371 252 455 336 267 181 195 26487 154 742 504 910 672 534 362 390 52888 22 309 485 009 821 345 068 724 781 05689 618 970 019 642 690 137 449 562 11290 1 237 940 039 285 380 274 899 124 224 (see note)91 2 475 880 078 570 760 549 798 248 44892 23 4 951 760 157 141 521 099 596 496 89693 9 903 520 314 283 042 199 192 993 79294 19 807 040 628 566 084 398 385 987 58495 39 614 081 257 132 168 796 771 975 16896 24 79 228 162 514 264 337 593 543 950 33697 158 456 325 028 528 675 187 087 900 67298 316 912 650 057 057 350 374 175 801 34499 633 825 300 114 114 700 748 351 602 688100 25 1 267 650 600 228 229 401 496 703 205 376 (see note)101 2 535 301 200 456 458 802 993 406 410 752102 5 070 602 400 912 917 605 986 812 821 504103 10 141 204 801 825 835 211 973 625 643 008104 26 20 282 409 603 651 670 423 947 251 286 016105 40 564 819 207 303 340 847 894 502 572 032106 81 129 638 414 606 681 695 789 005 144 064107 162 259 276 829 213 363 391 578 010 288 128108 27 324 518 553 658 426 726 783 156 020 576 256109 649 037 107 316 853 453 566 312 041 152 512110 1 298 074 214 633 706 907 132 624 082 305 024 (see note)111 2 596 148 429 267 413 814 265 248 164 610 048112 28 5 192 296 858 534 827 628 530 496 329 220 096113 10 384 593 717 069 655 257 060 992 658 440 192114 20 769 187 434 139 310 514 121 985 316 880 384115 41 538 374 868 278 621 028 243 970 633 760 768116 29 83 076 749 736 557 242 056 487 941 267 521 536117 166 153 499 473 114 484 112 975 882 535 043 072118 332 306 998 946 228 968 225 951 765 070 086 144119 664 613 997 892 457 936 451 903 530 140 172 288120 30 1 329 227 995 784 915 872 903 807 060 280 344 576 (see note)121 2 658 455 991 569 831 745 807 614 120 560 689 152122 5 316 911 983 139 663 491 615 228 241 121 378 304123 10 633 823 966 279 326 983 230 456 482 242 756 608124 31 21 267 647 932 558 653 966 460 912 964 485 513 216125 42 535 295 865 117 307 932 921 825 928 971 026 432126 85 070 591 730 234 615 865 843 651 857 942 052 864127 170 141 183 460 469 231 731 687 303 715 884 105 728128 32 340 282 366 920 938 463 463 374 607 431 768 211 456

m n 2m and 16n Symbol

97

Character Assignments Dec Hex EBCDIC1 ISO-82

0 00 NUL NUL1 01 SOH SOH2 02 STX STX3 03 ETX ETX4 04 SEL EOT5 05 HT ENQ6 06 RNL ACK7 07 DEL BEL8 08 GE BS9 09 SPS HT

10 0A RPT LF11 0B VT VT12 0C FF FF13 0D CR CR14 0E SO SO15 0F SI SI16 10 DLE DLE17 11 DC1 DC118 12 DC2 DC219 13 DC3 DC320 14 RES/ENP DC421 15 NL NAK22 16 BS SYN23 17 POC ETB24 18 CAN CAN25 19 EM EM26 1A UBS SUB27 1B CU1 ESC28 1C IFS IFS29 1D IGS IGS30 1E IRS IRS31 1F ITB/IUS IUS32 20 DS SP33 21 SOS !34 22 FS "35 23 WUS #36 24 BYP/INP $37 25 LF %38 26 ETB &39 27 ESC '40 28 SA (41 29 SFE )42 2A SM/SW *43 2B CSP +44 2C MFA ,45 2D ENQ -46 2E ACK .47 2F BEL /48 30 049 31 150 32 SYN 251 33 IR 352 24 PP 453 35 TRN 554 36 NBS 655 37 EOT 756 38 SBS 857 39 IT 958 3A RFF :59 3B CU3 ;60 3C DC4 <61 3D NAK =62 3E >63 3F SUB ?

Dec Hex EBCDIC1 ISO-82

64 40 SP @65 41 RSP A66 42 â B67 43 ä C68 44 à D69 45 á E70 46 ã F71 47 å G72 48 ç H73 49 ñ I74 4A ¢ J75 4B . K76 4C < L77 4D ( M78 4E + N79 4F | O80 50 & P81 51 é Q82 52 ê R83 53 ë S84 54 è T85 55 í U86 56 î V87 57 ï W88 58 ì X89 59 ß Y90 5A ! Z91 5B $ [92 5C * \93 5D ) ]94 5E ; ^95 5F ¬ _96 60 - `97 61 / a98 62 Â b99 63 Ä c

100 64 À d101 65 Á e102 66 Ã f103 67 Å g104 68 Ç h105 69 Ñ i106 6A ¦ j107 6B , k108 6C % l109 6D _ m110 6E > n111 6F ? o112 70 ø p113 71 É q114 72 Ê r115 73 Ë s116 74 È t117 75 Í u118 76 Î v119 77 Ï w120 78 Ì x121 79 ` y122 7A : z123 7B # {124 7C @ |125 7D ' }126 7E = ~127 7F " •



128 80 Ø129 81 a130 82 b BPH131 83 c NBH132 84 d IND133 85 e NEL134 86 f SSA135 87 g ESA136 88 h HTS137 89 i HTJ138 8A « VTS139 8B » PLD140 8C ð PLU141 8D ý RI142 8E þ SS2143 8F ± SS3144 90 ° DCS145 91 j PU1146 92 k PU2147 93 l STS148 94 m CCH149 95 n MW150 96 o SPA151 97 p EPA152 98 q SOS153 99 r154 9A ª SCI155 9B º CSI156 9C æ ST157 9D ¸ OSC158 9E Æ PM159 9F ¤ APC160 A0 µ RSP161 A1 ~ ¡162 A2 s ¢163 A3 t £164 A4 u ¤165 A5 v ¥166 A6 w ¦167 A7 x §168 A8 y ¨169 A9 z ©170 AA ¡ ª171 AB ¿ «172 AC Ð ¬173 AD Ý SHY174 AE þ ®175 AF ® ¯176 B0 ^ °177 B1 £ ±178 B2 ¥ ²179 B3 · ³180 B4 © ´181 B5 § µ182 B6 ¶ ¶183 B7 ¼ ·184 B8 ½ ¸185 B9 ¾ ¹186 BA [ º187 BB ] »188 BC ä ¼189 BD ¨ ½190 BE ´ ¾191 BF × ¿


192 C0 { À193 C1 A Á194 C2 B Â195 C3 C Ã196 C4 D Ä197 C5 E Å198 C6 F Æ199 C7 G Ç200 C8 H È201 C9 I É202 CA SHY Ê203 CB ô Ë204 CC ö Ì205 CD ò Í206 CE ó Î207 CF õ Ï208 D0 } Ð209 D1 J Ñ210 D2 K Ò211 D3 L Ó212 D4 M Ô213 D5 N Õ214 D6 O Ö215 D7 P ×216 D8 Q Ø217 D9 R Ù218 DA ¹ Ú219 DB û Û220 DC ü Ü221 DD ù Ý222 DE ú Þ223 DF ÿ ß224 E0 \ à225 E1 ÷ á226 E2 S â227 E3 T ã228 E4 U ä229 E5 V å230 E6 W æ231 E7 X ç232 E8 Y è233 E9 Z é234 EA ² ê235 EB Ô ë236 EC Ö ì237 ED Ò í238 EE Ó î239 EF Õ ï240 F0 0 ð241 F1 1 ñ242 F2 2 ò243 F3 3 ó244 F4 4 ô245 F5 5 õ246 F6 6 ö247 F7 7 ÷248 F8 8 ø249 F9 9 ù250 FA ³ ú251 FB Û û252 FC Ü ü253 FD Ù ý254 FE Ú þ255 FF EO ÿ

99

Notes: 1 The EBCDIC characters are based on code page 037.2 The ISO-8 controls are from ISO 6429, and the graphics are from ISO 8859-1. The ISO-8

graphics are code page 00819, named ISO/ANSI Multilingual.

Control Character Representations

Additional ISO-8 Control Character Representations

Formatting Character Representations

Two-Character BSC Data Link Controls

Commonly Used Editing Pattern Characters

ACK Acknowledge IT Indent TabBEL Bell ITB Intermediate Transmission BlockBS Backspace IUS International Unit SeparatorBYP Bypass LF Line FeedCAN Cancel MFA Modify Field AttributeCR Carriage Return NAK Negative AcknowledgeCSP Control Sequence Prefix NBS Numeric BackspaceCU1 Customer Use 1 NL New LineCU3 Customer Use 3 NUL NullDC1 Device Control 1 POC Program-Operator CommunicationDC2 Device Control 2 PP Presentation PositionDC3 Device Control 3 RES RestoreDC4 Device Control 4 RFF Required Form FeedDEL Delete RNL Required New LineDLE Data Link Escape RPT RepeatDS Digit Select SA Set AttributeEM End of Medium SBS SubscriptENP Enable Presentation SEL SelectENQ Enquiry SFE Start Field ExtendedEO Eight Ones SI Shift InEOT End of Transmission SM Set ModeESC Escape SO Shift OutETB End of Transmission Block SOH Start of HeadingETX End of Text SOS Start of SignificanceFF Form Feed SPS SuperscriptFS Field Separator STX Start of TextGE Graphic Escape SUB SubstituteHT Horizontal Tab SW SwitchIFS Interchange File Separator SYN Synchronous IdleIGS Interchange Group Separator TRN TransparentINP Inhibit Presentation UBS Unit BackspaceIR Index Return VT Vertical TabIRS Interchange Record Separator WUS Word Underscore

APC Application Program Command PLD Partial Line DownBPH Break Permitted Here PLU Partial Line UpCCH Cancel Character PM Privacy MessageCSI Control Sequence Introducer PU1 Private Use OneDCS Device Control String PU2 Private Use TwoESA End of Selected Area SCI Single Character IntroducerHTJ Character Tabulation w/ Justification SOS Start of StringHTS Character Tabulation Set SPA Start of Guarded AreaIFS Information Separator Four SSA Start of Selected AreaIGS Information Separator Three SS2 Single Shift TwoIND Index SS3 Single Shift ThreeIRS Information Separator Two ST String TerminatorMW Message Waiting STS Set Transmit StateNBH No Break Here US Information Separator OneNEL Next Line VTS Line Tabulation SetOSC Operating System Command

NSP Numeric Space SP SpaceRSP Required Space SHY Syllable Hyphen

Function EBCDIC ASCIIACK-0 DLE,X'70' DLE,0ACK-1 DLE,X'61' DLE,1WACK DLE,X'68' DLE,;RVI DLE,X'7C' DLE,<

Code(Hex) Meaning

Code(Hex) Meaning

20 Digit selector 5B Dollar sign21 Start of significance 5C Asterisk22 Field separator 6B Comma40 Blank C3D9 CR (credit)4B Period C4C2 DB (debit)


ANSI-Defined Printer Control Characters(A in RECFM field of DCB)

Code Action before Printing Recordblank Space 1 line0 Space 2 lines- Space 3 lines+ Suppress space1 Skip to line 1 on new page

101


.

File Number: S-390-00

SA22-7871-10

*07SA22787110*

IBMr

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IBM z/Architecture Reference Summary