HTR

80 MHz

40 ps

100 ppm

RJ-45(pinning std RG568B)

2.5V-CMOS

HEX-SLB

40 MHz

100 ps

0

VME P2 con.

Dif. LVPECL

HTR

40 MHz

-

0

RJ-45(pinning std RG568B)

TTCrx output

Clock requirements

Board

Freq.

Jitter (p-p)

Freq. tolerance

Connector

Level

HTR clock scheme

CK_LEMO

L1A_LEMO

TTC LVDS

3.3V-PECL80 MHz CLK

RX_BC0 LVDS

RJ-45Cat5 AMP558342-1

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

..

To other devices

DS90LV001

SpareOut

MC100LVEL37

8 clocks to TLKs

1 ck to Xilinx

80 MHzDifferential3.3V-PECL Xtal

Ck/2

CkCk

PCK953LVPECL-to-LVTTLp-p~3 ps

PCK953LVPECL-LVTTLp-p~3 ps

RX_CLK 3.3V PECL 40 MHz

(On final design path separate from Xtal)

..

..

..

..

DS90LV001TTCrx chip (VDD=3.3V

VCC=5V)

ININ_b

8 clocks to TLKs

1 ck to Xilinx

VME J2

p-p~2 ps

TTC_CLK40