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Imagination Technologies 2020 RVfpga-SoC How to go from a RISC-V Core to a RISC-V SoC? 1 Zubair Kakakhel (AZKY Tech Labs) Imagination Worldwide University Programme | September 2021 [email protected]

How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

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Page 1: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

Imagination Technologies 2020

RVfpga-SoCHow to go from a RISC-V Coreto a RISC-V SoC?

1

Zubair Kakakhel (AZKY Tech Labs)Imagination Worldwide University Programme | September [email protected]

Page 2: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

What is a System on Chip (SoC)?

An SoC is an integrated circuit or an IC that integrates an entire electronic or computer system onto it.

2© Copyright Imagination Technologies 2021Zubair Kakakhel

Page 3: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

The challenge

3

Very little material about how to make an SoC

Page 4: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

What is RVfpga-SoC?

A set of teaching materials explaining how to design and build an SoC

4© Copyright Imagination Technologies 2021Zubair Kakakhel

➢ CPU○ SweRV EH1

➢ SoC○ SwerVolfX

➢ Board○ Nexys A7

➢ Simulator○ Verilator

Page 5: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

What does RVfpga-SoC include?

1. Introduction to RVfpga-SoC2. Running Software on the RVfpga-SoC3. Introduction to SweRVolf and FuseSoC4. Building and Running Zephyr on

SweRVolf5. Running Tensorflow Lite on SweRVolf

55

RVfpga-SoC Course includes following five extensive labs:

© Copyright Imagination Technologies 2021Zubair Kakakhel

Page 6: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Lab 1: Building an SoC (Visual approach)

Wire CPU, Interconnect, Peripherals, Clock, Memory, Reset etc.

6© Copyright Imagination Technologies 2021Zubair Kakakhel

Page 7: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Lab 2: Running Software on RVfpga-SoCRun C programs on the SoC created in Lab 1

7© Copyright Imagination Technologies 2021Zubair Kakakhel

RVfpga SimRVfpga Nexys

Simulation

Nexys A7Implementation

Page 8: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Lab 3: FuseSoC approach to SoC design

FuseSoC does all of this tedious work that we manually did in Labs 1 and 2

8© Copyright Imagination Technologies 2021Zubair Kakakhel

SweRVolf SimSweRVolf Nexys

Simulation

Nexys A7Implementation

Page 9: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Lab 4: Running Zephyr on SweRVolfBuilding and Running Zephyr (an RTOS: Real Time Operating System) on SweRVolf.

9© Copyright Imagination Technologies 2021Zubair Kakakhel

Page 10: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Lab 5: Run Tensorflow Hello WorldThe Hello World example is designed to demonstrate the absolute basics of using TensorFlow Lite for Microcontrollers. This program trains and runs a model that replicates a sine function.

10© Copyright Imagination Technologies 2021Zubair Kakakhel

Page 11: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Two Courses: RVfpga vs. RVfpga-SoC (1)

RVfpga and RVfpga SoC are two courses. RVfpga focuses more on aspects inside the CPU core. RVfpga-SoC focuses more on aspects outside the CPU core.

11© Copyright Imagination Technologies 2021Zubair Kakakhel

Lab 0: RVfpga Experiment OverviewLab 1: Creating a Vivado ProjectLab 2: Programming in CLab 3: RISC-V assembly languageLab 4: Function callsLab 5: Image processing: C and assembly

Lab 6: Introduction to 1/OLab 7: 7-segment displayLab 8: TimersLab 9: Interrupt driven I/OLab 10: Serial Bus

I/O systems

Programming

Lab 11: SweRV EH1 Configuration and Organization. Performance MonitoringLab 12: Arithmetic/Logical Instructions: the add instructionLab 13: Memory Instructions: the lw and sw instructionsLab 14: Structural HazardsLab 15: Data HazardsLab 16: Control Hazards. Branch Instructions: the beq Instruction. The Branch.Lab 17: Superscalar ExecutionLab 18: Adding New Features (Instructions, Hardware Counters) to the CoreLab 19: Memory Hierarchy. The Instruction Cache.Lab 20: ICCM and DCCM

Investigate, analyze, and modify the RISC-Vcore and memory system.

RVfpga

Page 12: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Two Courses: RVfpga vs. RVfpga-SoC (2)

RVfpga and RVfpga SoC are two courses. RVfpga focuses more on aspects inside the CPU core. RVfpga-SoC focuses more on aspects outside the CPU core.

12© Copyright Imagination Technologies 2021Zubair Kakakhel

Lab 1: Introduction to RVfpga-SoCLab 2: Running Software on the RVfpga-SoCLab 3: Introduction to SweRVolf and FuseSoCLab 4: Building and Running Zephyr on SweRVolfLab 5: Running Tensorflow Lite on SweRVolf

SoC

RVfpga-SoC

Page 13: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Closing Remarks

From Verilog, to SoC, to RTOS, to Tensorflow- All source code visible

A set of 5 labs that walk through students on how to set things up

13© Copyright Imagination Technologies 2021Zubair Kakakhel

Page 14: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

Acknowledgements

AUTHORSProf. Sarah L. HarrisProf. Daniel ChaverM. Hamza LiaqatZubair L. KakakhelOlof KindgrenRobert Owen

CONTRIBUTORSRobert OwenIvan KravetsValerii KovalTed MarenaProf. Roy KravitzProf. Luis PiñuelProf. J.I. Gomez

ADVISERProf. David Patterson

ASSOCIATESProf. Daniel LeónProf. José Ignacio GómezProf. Katzalin OlcozProf. Alberto del BarrioProf. Fernando CastroProf. Manuel PrietoProf Ataur Patwary

Sponsors and Supporters

Prof. Christian TenlladoProf. Francisco TiradoProf. Román HermidaCathal McCabeDan HugoBraden HarwoodProf. David Burnett

Gage ElerdingProf. Brian CruickshankDeepen ParmarThong DoanOliver RewNiko NikolayGuanyang He

Page 15: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel

15

Join the IUP today，and you can download free teaching materials!→ university.imgtec.comOur support hub:• Brochures, info sheets• Teaching materials, guides, software • Tutorial video gallery • Support forums• References: books, platforms, photosSupported languages: Chinese, EnglishSocial media:✔ Robert Owen @UniPgm✔ Imagination Technologies @ImaginationTech✔ WeChat & Weibo: ImaginationTech

© Copyright Imagination Technologies 2021Zubair Kakakhel

Please feel free to join the group on WeChat

Page 16: How to go from a RISC-V Core RVfpga-SoC to a RISC-V SoC?

© Copyright Imagination Technologies 2021Zubair Kakakhel 16Imagination Technologies 2021Zubair Kakakhel 2021

https://docs.google.com/file/d/1TY6apEXpcbMm_Nly9M0T_PUGwAJW4PWm/preview

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