How to Debug a PLL Frequency Synthesizer

50 www.rfdesign.com February 2004

Next Generation Wireless

How to debug a PLL frequency synthesizer

adio systems incorporate frequencyR synthesizers based on phase lock loop(PLL) technology for various reasons. Thebenefits of PLLs include:

1) The ease of integration into integratedcircuits.

2) The flexibility in the channel spacing forthe radio.

3) The high performance available.4) The small size of the frequency synthe-

sizer.Many textbooks on the theory, design and

optimization of PLLs exist, but there is littleliterature to guide a novice in properlydebugging the PLL in an engineering labenvironment.

PLL overviewThe simple PLL consists of a frequency

reference, a phase detector, a charge pump, aloop filter and a voltage-controlled oscillator(VCO). (Figure 1.) This simple PLL imple-mentation is a fine starting point for creatingbasic loop equations and understanding thedynamic response. A frequency synthesizerbased on PLL technology will add twofrequency dividers: one that reduces thereference frequency and one that divides theVCO’s frequency. It is also handy to com-bine the phase detector and charge pump intoone block for ease of analysis and a clean

tector produces an error voltage that is ap-proximately linear over the range of phaseerrors of 62*p, and is constant for errorsgreater in magnitude than 62*p. (Figure 3.)This dual-mode operation of the phase-fre-quency comparator produces faster PLL locktimes for large frequency errors, such as whenthe PLL starts at power up, and avoids lock-ing on harmonics.

The VCO creates a frequency based onthe control or tuning voltage applied to it.VCOs are available in module form, IC formor can be created from discrete components.Figure 4 depicts a VCO created using activecomponents inside a MAX2361 transmitterIC. The resonant tank and varactors areexternal, allowing the IF LO to be uniquelydefined by the design engineer in support ofa particular radio’s frequency plan.

The loop filter (Figure 5) integrates thecurrent pulses produced by the phase-frequency detector’s charge pump to createthe tuning voltage applied to the VCO. Tra-ditionally, the tuning voltage from the loopfilter moves higher (more positive) toadvance the VCO’s phase and to move theVCO to a higher frequency. The loop filtermay be implemented with passive compo-nents such as resistors and capacitors, or itmay employ an operational amplifier. Theloop filter time constants, along with the gainof the VCO, phase detector and dividers, setsthe PLL bandwidth. The PLL bandwidth thendetermines the PLL’s transient response,reference spurious levels and noise filteringcharacteristics. At frequencies within the PLL

While there are many excellent textbooks on the theory, design and optimizationof PLLs, little literature exists to guide a novice in properly debugging the PLL inan engineering lab environment. This article provides some valuable techniquesand guidelines in quickly debugging individual portions of a PLL employed in afrequency synthesizer.

By Bob Kelly

diagram. (Figure 2.) These digital dividercircuits added to the simple PLL allow easysetting and changing of the operatingfrequency. A processor will simply “write”a new divider value to a register in the PLLto change the VCO’s operating frequency,thereby changing the radio’s operatingchannel.

Description of PLL operationThe operation of the PLL is a closed-loop

control system, which compares the phase ofa reference signal to the phase of the VCO. Afrequency synthesizer, with the added refer-ence and feedback dividers compares the twophases scaled by the divider’s setting. Thisphase comparison is done in the phase detec-tor, which in most systems is a phase andfrequency detector. The phase-frequency de-

Figure 1. The simple PLL shown in this block diagram produces an output frequency“locked” to the reference.

The operation of the PLL is a closed-loopcontrol system, which compares the phase of a

reference signal to the phase of the VCO. Afrequency synthesizer, with the added reference

and feedback dividers, actually compares thetwo phases scaled by the divider’s setting.


bandwidth, the phase noise at a synthesizeroutput is dominated by the phase detector’sphase noise. Meanwhile, at frequenciesoutside of the PLL bandwidth, the outputphase noise is due to VCO phase noise.

The frequency synthesizer PLL referenceinput is a stable, clean constant-frequencysignal. In most radios, some form of a crystaloscillator is employed since its phase noise isvery low and its frequency is stable and welldefined. The PLL will divide this reference toprovide a lower frequency for the phase-frequency detector. This lower frequency setsthe comparison rate for the detector andestablishes the smallest frequency step pos-sible by incrementing the feedback divider by“1.” This becomes the frequency resolutionof the synthesizer, or frequency step size,which should be equal to or smaller than thechannel spacing of the radio system beingdesigned. The phase detector and loop filtercreate a tuning voltage based on the VCO’soutput scaled down by the feedback divider.Based on this description, the VCO operat-ing frequency is:

(1)

For example, if the reference frequency(FREF) is 20 MHz, and the reference divider(R) is 2000, a feedback divider setting (N) of88,103 will produce a VCO frequency (FVCO)as follows:

(20 MHz/2,000) x 88,103 = 881.03 MHz

Changing the feedback divider by 1 to88,104 produces a VCO frequency of 881.04MHz, since the comparison frequency is10 kHz.

This frequency synthesizer multiplies thereference frequency to the UHF band. Onebyproduct of this PLL multiplication methodis the increase in phase noise within the loop’sbandwidth. The noise floor of the PLL isincreased by 20*log (N) within the loop band-width. In the case noted above, the phasenoise increased 20*log (88,103) = 98.89 dB.This is why the reference oscillator must beextremely clean. The loop’s action will in-crease the noise floor by ~100 dB, so a clean,high-Q crystal oscillator is mandatory if theoutput is to be of sufficient quality for mod-ern radio communications.

Please consult existing references fordetailed analysis equations.

Bring PLL to lifeAt this point in your product development

cycle, you have read the texts, poured overspreadsheets and simulations, and theoreti-cally obtained every dB of performance pos-sible from your design. Your design isreduced to copper traces on a circuit board.

The parts have been installed on the boardand the temptation is to rush into the lab,apply power and quickly verify that all yourdiligent efforts are correct. In a perfect world,this engineering project is on schedule andunder budget. Theory and reality are aboutto meet again, with your design being theconduit between those two disparate domains.

Invest some time to study the PLL’soperation before exhaustive performancemeasurements are begun. Not only must the

frequency synthesizer function; it must func-tion properly before data is recorded. Rapidprogress is ensured by following a methodi-cal procedure to verify each section of thePLL during your early debugging sessions.

The VCO sectionThe VCO produces the signal output from

a PLL frequency synthesizer, so it deter-mines much of the PLL’s performance. If theVCO is not operating properly, many perfor-

Figure 2. A frequency synthesizer adds digital dividers to a PLL, allowing the output frequencyto be programmed.

Figure 3. The phase-frequency detector produces a control voltage over a 666662ppppp phase range.

Figure 4. The MAX2361 transmit IC’s IF VCO uses external components to set the gain andfrequency.


mance parameters will be affected. Early inthe debug phase, the VCO should be testedto ensure it is providing the intended fre-quency range, gain and output level. To testthe VCO, modify the PLL so that there is noclosed-loop control. A common way to“break” the loop is to disconnect R3 (Figure4) and apply a lab power supply across C4,which allows the VCO tuning voltage to bevaried over the desired range. Monitor theVCO’s frequency of operation on a frequency

correct this condition, verify that all resonantcomponents in the VCO tank are the desiredvalues. For example, if the tank inductorL1 (Figure 4) is too small, the resonantfrequency will be shifted up in frequency.

Always keep in mind the equation describ-ing a simple LC tank circuit’s resonantfrequency:

(2)

Fres is the resonant frequency in Hertz.L is the inductance in Henries.C is the capacitance in Farads.

Are the correct parts installed?Modern reactive components have become

so small that visible labels are not possible.This means that components in the VCO aremost easily tested by substitution with aknown value. Because assembly of the firstcircuit board may have been completed byhand, it is likely that incorrect values havebeen soldered on the PCB. Replace tankcomponents as needed to bring the VCOfrequency close to the desired operating point(Table 1).

It is possible to correct the VCO’s opera-tion as described in Table 1 and the PLL willstill exhibit problems. The loop might oscil-late if the VCO’s tuning gain is not close tothe value used when the loop filter compo-nents were calculated. In Figure 6, note theslope of the curve described by the lab datafrom your prototype. The stability of thefeedback loop requires the gain of the loop tobe in a certain range. If the VCO is on thecorrect frequency but has a large gain error,the loop itself will oscillate and cause theVCO to be modulated over a broad range offrequencies.

Use your data on the VCO in the openloop condition to verify the loop gain is closeto your design-target value. If the VCO tun-ing gain is too high, the varactors are coupledtoo tightly to the resonant tank. Confirm thatthe correct varactors have been installed. Thecapacitors (C2 and C3 in Figure 4) that couplethe varactors to the tank may be too large invalue. Conversely, if VCO tuning gain is low,C2 and C3 may need to be increased in value.

The dividersCan the divider work at the desiredfrequency?

A PLL design often overlooks the digitalfrequency divider’s specifications. The divid-ers usually work fine, but a lack of thorough-ness on the designer’s part will produce aPLL that does not perform as expected. Alldividers have a specification for the maxi-mum input frequency (FMAX) and the mini-mum input level.

In a design that ignores the FMAX specifica-tion, the divider will “drop pulses.” The closedloop will then detect (in error) that the VCO

counter (or a spectrum analyzer) as the tun-ing voltage changes. Record the operatingfrequency at several tuning voltage settings.Is the VCO at the correct frequency?

Using data from this simple test will quicklyassess if the VCO is able to operate at thedesired frequency. If the VCO is to producean IF LO (intermediate frequency local oscil-lator) at 183 MHz, and the lowest frequencynoted in the test is 187 MHz, it will beimpossible for the PLL to lock properly. To

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is too low in frequency and command thetuning voltage to go still higher. The dividerwill miss more pulses and the loop willattempt to further push the VCO to a higherfrequency. The loop will then enter a “latched”condition where the VCO tuning voltage isheld at the positive supply voltage.

The deceptive issue at work is that thefeedback divider must not only divide theVCO’s expected output, but it must correctlydivide the highest frequency that the VCOcan produce under locked and unlocked

conditions. For the loop to function reliably,transient conditions encountered at start-upor changing channels must not cause feedbackpolarity reversal. Is the VCO amplitude sufficient to drivethe divider?

The feedback dividers also require a mini-mum signal amplitude to operate. Ensure thatthe VCO signal level reaching the divideris well above the data sheet minimum overthe entire frequency range of the VCO.Dividers will commonly drop pulses when

the signal level is too low, making it impos-sible for the PLL to obtain stable steady-stateoperation.Is the divider programmed with the correctvalue?

The PLL will not produce the correctfrequency if the divider control registers areloaded with the wrong values. It is common tooverlook a fixed divide-by-two foundin many receiver embedded PLLs, especiallyin applications with quadrature generationcircuits. Last, the PLL control registersmay be loaded with the wrong data dueto faulty data transmission on the serialbus. Improper data transfer may resultfrom RC networks placed on the serial buslines to help control noise and interference.Confirm with an oscilloscope that bus timingrequirements are met and that valid data arebeing presented to the pins of the PLL IC.

The loop filterThe loop filter sets the PLL’s bandwidth

and transient response, and it shapes the PLL’snoise spectrum. You can consult textbooksfor the relations between loop-filter timeconstants and these performance behaviors.Are the correct components installed in theloop filter?

With the wrong parts installed, the band-width may be too wide, causing reference fre-quency spurious sidebands on the PLL output.Or, the bandwidth may be too narrow, causingVCO phase noise to dominate the output spec-trum and produce a long settling time. If thedamping factor is too low, the loop will oscil-late. Polarized filter capacitors have high leak-age currents, causing a loop to constantly becorrecting with large charge pump pulses. Thisconstant correction causes the reference fre-quency spurious sidebands to be larger thanexpected. Install low-leakage capacitors (ce-ramic, mica or polyester film) to improve thisperformance.Is the op-amp in the active filter staying outof saturation?

PLLs with no on-chip charge pump willhave phase detector outputs that command a“pump up, pump down” condition. ThesePLLs will often employ an active loop filter.In the case of an active loop filter, the op-amp’s input stages may saturate on each cor-rection pulse from the phase-frequency de-tector. Recovery from this saturationcondition is not well defined or controlled, sothe loop dynamics will not be as designed.

The solution is to “split” the op-amp inputresistors and place a pole in the filter’sresponse. This will prevent the fast edges fromhitting the op-amp input, thereby avoidingpulse-wise saturation. The extra pole must beexamined for its impact on loop stability, sinceit will degrade the design’s phase margin.

Also, some op-amp input stages can “changepolarity” during power-up conditions, causing the



Figure 5. The passive loop filter integrates charge-pump current pulsesto produce the VCO tuning voltage (a). Some PLLs use an op-amp in anactive loop filter (b).

loop to saturate due to excess positive feedback. The solution is to select anop-amp that is not upset by power-on transient conditions.

The phase-frequency detector and charge pumpThe phase-frequency detector and charge pump are usually

Table 1. VCO troubleshooting guide suggests common solutions.

Symptom Cause Remedy

VCO frequency too high. Incorrect tank components. Replace tank’s L & C components with knownvalue parts.

VCO frequency too low. Incorrect tank components. Replace tank’s L & C components with knownvalue parts.

VCO frequency too low even Too much stray capacitance. New PCB layout in area of VCO, or recalculatewith correct tank components. tank components with increased stray

capacitance values.

No VCO output. VCO not oscillating. Confirm varactors are installed with correctpolarity. Check solder connections in tank area.Confirm that R1 and R2 are high enough values.

VCO frequency very unsteady. Marginal design to support Increase VCO’s loop gain if possible.oscillation. Try high Q inductor. Confirm varactor polarity

is correct.

VCO frequency very unsteady. Multiple VCO modes; tuning Try lower Q inductor, or decrease R1 and R2.curve not continuous. Decrease varactor coupling to tank by

lowering C2 and C3. Pick inductor with higherself-resonant frequency.

Figure 6. The VCO tuning-curve data allows the VCO’s gain to becomputed.

integrated with other PLL circuits, so if they have been properlydesigned, there is little room for difficulty. Nevertheless, Mr. Murphywas not copied on the memo that ruled out trouble, so we mustexpect some room for error.

Phase frequency detectors in most ICs have some aspects of theiroperation programmed by register values. The polarity of the detectorcan be set under software control, and the magnitude of the charge pumpcurrent may have several user-defined values.Is the phase detector set for the correct polarity?

Phase detector polarity control allows a PLL IC to function withpositive or negative VCO gain, or to account for a signal inversion inan active loop filter. Confirm that the phase detector’s polarity iscorrect to operate with the intended VCO and loop filter. If the loopis latched with the control voltage against the ground or supply rail, asimple bit inversion may be all that is needed to bring life to the PLL.Is the charge pump current the desired value?

The charge pump is also (often) under user control. This is handy,as it allows a frequency synthesizer to operate over a wide tuningrange and correct for the PLL’s gain change over the band of interest.This leads to similar loop dynamics and noise character at low,medium and high VCO frequencies. If the charge pump current is not


changed as the synthesizer tunes over its band,the noise sidebands change and the tuningtime will vary. If either of these symptomsappear in an otherwise well-behaved PLL, thec h a r g epump current may be set too low, too high, oris being changed inappropriately for theapplication.

The printed circuit boardThe last aspect of the PLL often con-

sidered is the impact of the printed circuitboard (PCB). As many RF engineers un-derstand, the PCB is a vital part of thesystem, and proper design must be observed.Is the circuit board clean?

The loop filter has already been identified as an area of the PLLthat is adversely affected by leakage currents. The leakage dueto filter capacitors is improved by using low-leakage capacitors.Another source of leakage is dirt and flux in the area of the filter.Often, a PLL can be improved by using proper cleaning techniquesin the area of the filter to remove contamination. Study the PCBunder the microscope and confirm that your filter area is free of dirtand flux residue.Is the VCO tuning line shielded?

A high-gain VCO produces large frequency deviations forsmall changes in the tuning voltage. The VCO tuning line hashigh impedance, and noise can easily couple onto the line andmodulate the VCO. Digital signals must not be routed near the

ABOUT THE AUTHORBob Kelly, Sr., corporate RF engineer,Maxim Integrated Products Inc., hasdefined seven low-noise amplifier prod-ucts. He earned a B.S.E. (EE) and M.S.E.(EE) from the University of Michigan.He has held design and applicationsengineer positions with Motorola, Philips,Loral, Proxima and Hitachi during his24-year career. He has consulted onanalog, radio and video systems andwritten software for the PC. He can bereached at 760-633-4158, or by e-mailat [email protected].

VCO tuning line. Veteran engineers willavoid routing any signals near the VCOtuning just to avoid any impact on thesynthesizer’s performance. The PLL actiondoes help a bit with this type of noise cou-pling; low-frequency noise within the loop’sbandwidth, is corrected by the loop’s excessgain. Is the VCO shielded?

A VCO acts like a narrow bandpass filterwith gain. Any noise with frequency contentnear the VCO’s resonance point will readilycouple into the VCO and modulate it. Ifthe VCO tunes over a harmonic of a “strong”

crystal oscillator, expect to see spurious outputs if the harmonicenergy couples into the VCO tank.

ConclusionBy understanding and evaluating the individual portions of

a PLL, the design engineer rapidly brings the frequencysynthesizer into operation. Armed with the techniques andinformation presented here a frequency synthesizer is quicklydebugged and the radio system is ready for detailed performanceevaluation. RFD

References:1. Ulrich L. Rohde, Digital PLL Frequency Synthesizers: Theory

and Design. Prentice-Hall, Englewood Cliff, NJ, 1983.


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How to Debug a PLL Frequency Synthesizer