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How Computers Work Lecture 6 Page 1
How Computers WorkLecture 6
Finite State Machines
How Computers Work Lecture 6 Page 2
WD Memory
WDRegister File
RA2Memory
RD2
WA RC
WERF WEMEM
WA
WEWE
A B
A op B
Register FileRA1
RD1
RA2
RD2
RA RB RC
BSELASEL
ALUFN
WDSEL0
0 1
010 1 2
1
ALU
Register FileSEXT
C
4:0 9:5 20:5 25:2131:26
OPCODE
RA1Memory
RD1
PCQ
+1
DPC
Z
0 1
JMP(R31,XADDR,XP)
XADDR
0 1
2
ISEL
PCSEL
OPCODE
One FSM: The Beta
How Computers Work Lecture 6 Page 3
A generic form of exemplified by the Beta:The (Synchronous) Finite State Machine
(FSM)
Logic(describable by
truth table)
NEXTSTATE
IN OUT
CURRENTSTATE
Memory
CLOCK
How Computers Work Lecture 6 Page 4
Another FSM: A (Primitive) Coke Machine
COKE
1. Coke Costs $0.152. Only Nickels + Dimes Accepted3. FSM Inputs:
5: Nickel10: DimeCoke: Give-me-a-cokeReturn: Give-me-my-money-back
4. FSM Outputs:Drop-a-coke (Drop)Return $.05 (Ret5)Return $.10 (Ret10)Return $.15 (Ret15)
How Computers Work Lecture 6 Page 5
State Diagramfor a primitive Coke Machine
How Computers Work Lecture 6 Page 6
Rules for DesigningFSM State Diagrams
• Arcs out of a state must be mutually exclusive
• Arcs out of a state must be exhaustive (use * to make this job easier)
• The starting state should be defined• All possible states should be defined, with
transitions to starting state• S states requires 2 ^ S state variables
How Computers Work Lecture 6 Page 7
The Synchronous FSM
Comb.Logic
NEXTSTATE
IN OUT
CURRENTSTATE
Synch.Delay
CLOCK
How Computers Work Lecture 6 Page 8
Mealy vs. Moore
in out
Q D
clk
nextstate
currentstate
in out
Q D
clk
nextstate
currentstate
MEALY MOORE
i11 s1,o1 s2,o2
i12
i21
i22i11,o11 s1 s2
i12,o12
i21,o21i22,o22
How Computers Work Lecture 6 Page 9
Mealy vs. Moorefrom a Truth Table
CURRENT NEXT STATE IN STATE OUT
0 0 0 0 0 0 1 1 00 0 0 1 0 0 0 1 00 0 1 0 1 0 0 0 10 0 1 1 0 1 0 0 10 1 0 0 0 0 1 1 10 1 0 1 0 1 0 1 1 ... ...
This is a Mealy machine
How Computers Work Lecture 6 Page 10
Another Way of DrawingMoore FSMs
in out
Q D
clk
nextstate
currentstate
in outQD
clk
Next StateC.L.
OutputC.L.
current state
How Computers Work Lecture 6 Page 11
Why do we need the synchronizing element?
Logic
IN OUT
STATE
How Computers Work Lecture 6 Page 12
A Human Experiment
Make a power-of-2 sequence generator from 2 adders:
How Computers Work Lecture 6 Page 13
• Experiment 1– Wait your turn
– Immediately Look at the two numbers on the board
– Immediately Erase the number in front of you
– Immediately Add them in your head
– Immediately Write the result in front of you
– Walk away
• Experiment 2– Follow the instructions of your sergeant / lecturer
How Computers Work Lecture 6 Page 14
PossibleSynchronizing Elements
The Register, a.k.a. the Edge Triggered Flip-Flop
in outC.L.
Q D
clk
nextstate
currentstate
clk
D (next state)
Q (current state)
How Computers Work Lecture 6 Page 15
Edge-Triggered F-F Input Timing
D
CLK
Ts = Setup Time
Th = Hold Time
How Computers Work Lecture 6 Page 16
PossibleSynchronizing Elements
• The Transparent Latch
in outC.L.
Q D
G
clk
nextstate
currentstate
G
D (next state)
Q (current state)
How Computers Work Lecture 6 Page 17
D
G
Q0
1
MUX Implementationof the Transparent Latch
G
D
Q
How Computers Work Lecture 6 Page 18
Input Specifications for the Transparent Latch
D
G
Ts = Setup Time
Th = Hold Time
How Computers Work Lecture 6 Page 19
The Globally Synchronous Discipline
• NO LOGIC CYCLES - All Cycles Are Broken by at least 1 Synchronizing Delay
• All Synchronizer Inputs obey timing requirements ( Tsetup, Thold )
How Computers Work Lecture 6 Page 20
Timing Constraints
• Transparent Latch
in outLogic
Q D
G
clk
nextstate
currentstate
1
3
5
4
6
2G
next state
current state
Tpd minG-Q < t13
Tpd maxG-Q > t14
Tpd min Logic < t35
Tpd max Logic > t46
t12 < Tpd min G-Q + Tpd min Logic - TholdTpd min G-Q + Tpd min Logic - Thold
How Computers Work Lecture 6 Page 21
Timing Constraints
Edge Triggered Flip-Flop
in outC.L.
Q D
clk
nextstate
currentstate
1
3
5
4
6
clk
next state
current state
Thold < Tpd minC-Q + Tpd minC.L.
Tpd minG-Q < t13
Tpd maxG-Q > t14
Tpd min Logic < t35
Tpd max Logic > t46
How Computers Work Lecture 6 Page 22
Maximum Frequency
in outC.L.
nextstate
currentstate
clk
next state
current state
Clock Period > ___________
Q D
clk
T pd max c-q + T pd max cl + T setupT pd max c-q + T pd max cl + T setup
How Computers Work Lecture 6 Page 23
Skew
QD
clk1
QD
clk2
C.L.
Tskew < _______________________________T cd c-q + T cd cl - T holdT cd c-q + T cd cl - T hold
How Computers Work Lecture 6 Page 24
A Few Details
• What Happens if the Logic has Glitchy Outputs?
in out
Q D
clk
nextstate
currentstate
How Computers Work Lecture 6 Page 25
De-Glitching FSM Outputs
• Assumption: Registers Glitch Free if output doesn’t change from cycle to cycle.
• Consequence: Output Delayed
in
nextstate
currentstate
Q D
clk
QD
clk
out
How Computers Work Lecture 6 Page 26
Summary
• Today’s Lecture– Every modern computer is a finite state machine
– There is a straightforward art to designing FSMs
– Timing is important, but there is a discipline for insuring correct operation.
• Recitation– Practical Practice designing and implementing FSMs