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HiM 2014CMOS digital, analog & mixed microelectronics ICs 1

CMOS scaling down for digital, analog & mixed signals in microelectronics circuits & systems

Highlights in Microtechnology HiM‘2014,EPFL IMT-NE, June 18th, 2014

EPFL STI IMT-NE ESPLABPierre-André Farine


Content

• MOSFET Basics, CMOS, Memories

• CMOS Technology scaling

• Changes in CMOS and implications on digital and analog circuits

• Conclusions


MOSFET Perspective view

[Sze]


MOS diode - Energy band diagram at V = 0

E0

Eg

2

[Sze]


Ideal MOS diode - Energy Band diagrams and charge distributions – 3 cases

(a) accumulation (b) depletion (c) inversion

[Sze]

qqS

BSB 2c2) Strong inversion:c1) Weak inversion:

BS 2


n-MOS FET Energy Band ProfileTwo-dimensional band diagram of an n-channel MOSFET:

(a) Device configuration.

(b) Flat-band zero-bias equilibrium condition.

(c) Equilibrium condition (VDS = 0) under a positive gate bias.

(d) Nonequilibrium condition under both gate and drain biases.

[Sze]


MOSFET - ID = f(VD) & ID = f(VG)Transfer characteristics in linear region ID = f(VG)Idealized drain characteristics ID = f(VD)

[Sze]


2.1

MOSFET operated in linear and saturation

(a) in the linear region (low V,)

(b) at onset of saturation, and

(c) beyond saturation(effective channel length is reduced).

[Sze]


DTGonD VVVCL

ZI

MOSFET - The Main Equations

I. Linear Region: Drain Current:

for VD << (VD – VT)

II. Triode region: Threshold Voltage:B

O

BAsT C

qNV

2

)2(2

2

2D

DTGonD

VVVVC

L

ZI V-I Characteristics:

III. Saturation Region: Saturation Voltage: TGD VVVsat

Drain Current: 22 TG

onD VV

L

CZI

sat

Transconductance: )(.

TGoxn

cstVG

Dm VV

dL

Z

V

Ig

D


MOSFET Parameters [Baker]


Layout of a conventional MOS transistor


Determining Threshold Voltage VT

• Graph showing the root of saturated drain current as a function of drain-source voltage

• Body Biasing


Id(Vds, Vgs) characteristicsSub-threshold operation (Weak inversion)Conventional operation (Strong inversion)

When the gate voltage is below the threshold voltage and the semi-conductor surface is only weakly inverted, the corresponding drain current is called the sub-threshold current. The sub-threshold region is particularly important when the MOSFET is used as a low-voltage, low-power device such as a switch in digital logic and memory applications, because the sub-threshold region describes how the switch turns on and off. To reduce the sub-threshold current to a negligible value, we must bias the MOSFET a half-volt or more below VT. In the sub-threshold region, the Id(Vds, Vgs) characteristics of a MOSFET are similar to that of a BJT with high transconductance, low saturation voltage and high temperature sensitivity.


Subthreshold characteristics of a MOSFET

[Sze]

Inverse slope issubthreshold swing,S [mV/dec] (S~ 80 mV/dec)


MOSFET Operation: Gate Control

2.1

[King Liu]


DIGITAL CMOS IC INVERTER:

CIRCUIT LAYOUT

Complementary MOS inverter. (a) Circuit diagram(b) Circuit layout. (c) Cross section along dotted A-A’line of (b). [Sze]


DIGITAL CMOS INVERTER TRANSFER CURVE

[Baker]


7.18

CMOS Logic Gates

[R. Jacob Baker ]


Digital Model of MOSFET

[Baker ]

LL

V

L

VV

C

gf Dsat

nTG

nG

mT 2

1

2...

2 2

0m n G T

Wg C V V

L


Basic Common Source Amplifier: Analog Voltage Gain

VDD

Circuit Schematic

R

Equivalent Circuit[Baker]

R


CMOS n-MOS Input Analog Differential Amplifier

[Baker]

CMOS p-MOS Input Analog Differential Amplifier

Eliminatesthe body effect


Noise - CMOS differential amplifier

(a) Noise sources added into the basic diff. (b) Modeling the amplifier noise at the input

(c) Total output noise over a 1-Hz bandwidth


SRAM Memory Cell Structure

VDD

Six-transistor full CMOS

WORD

BIT BIT

WORD

VDDVDD

VDD

I I-I

I

HL

High Speed

High Cost

Low Density


Impact of Variability on SRAM

2.1


Impact of VDD & size on SRAMRDF and VT DF fluctuations cause the SRAM’s static noise margin to vanish!

Impact of Vdd scaling

Impact of bit cell scaling

03/22/2012


DRAM Memory Cell Structure

Row

Column

StorageCapacitor

WORD LINE

PASS TRANSISTOR

CAPACITOR

WORD LINE

CAPACITOR

PASS TRANSISTOR

PASS TRANSISTOR

WORD LINE

CAPACITOR

STACK

TRENCH

PLANAR


DRAM Memory Architecture

Sense Amplifier

Column Decoder

InputBuffer

OutputBuffer

Memory Array

RowAddressBuffer

Word-line D

river

Row

Decoder

ColumnAddressBuffer

I/Oline

RAS

CAS

Din

Dout

Row andColumnAddresses

addressmultiplexing

word linedelay

Sense delaybandwidth

Refreshcircuit


DRAM Trench Cell

Deep of >7 m

Surface areais then large


SRAM Layout size (140F2) vs. DRAM (8F2)


EPROM, EEPROM & Flash MemoryBasic Operation Principle

Sensevoltage

ProgrammedErased

Gate Voltage, VGS

Dar

in C

urre

nt

n+ n+

P -sub

-- -- -- --

Gate

DrainSourceQT

Storage of charges


Types of EEPROM (NVM)

Floating Gate Charge-Trapping

Poly-gate

Blocking OxideSi3N4

Tunnel oxide

Control gate

Floating gateONO

EPROMEEPROMFlash

SONOS


EEPROM(Electrically Erasable Programmable Read Only Memory)

Control gate

n+ n+

p-substrate

Source

Floating gate

Tunnel oxide

Bit line

Select- Line

Word Line

Byte-Alterable


EEPROM Charge Transfer Mechanisms

• Hot-Electron Injection– Avalanche Injection

– Channel Hot-Electron Injection

– Source-Side Electron Injection

– Substrate Injection

• Fowler-Nordheim Tunneling

• Ultraviolet Light Erase


Comparison EEPROM vs. Flash


Flash - Cell Architecture


CMOS Technology• Complementary Metal-Oxide-Semiconductor – CMOS

• First proposed in the 1960s. Was not seriously considered (except by watchmakers!) until the severe limitations in power density and dissipation occurred in n-MOS circuits

• Now the dominant technology in IC manufacturing

• Employs both p-MOS and n-MOS transistors to form logic elements

• The advantage of CMOS is that its logic elements draw significant current only during the transition from one state to another and very little current between transitions -hence power is conserved.


CMOS Technology Scaling

03/22/2012

[Bergemont, 2012]

1. CMOS scaling driven by digital applications• Memories: high density and low power constraints• Microprocessors: high performance and speed

2. Analog use a digital process as bare bones baseline

3. Huge implications on analog design , creating new challenges as silicon continues to scale down, including headroom, gain, leakage, variations, mismatches and automated CAD


CMOS Technology Scaling – The Dilemma

[Bergemont, 2012]


MOSFET - Scaling Relations


MOSFET - Scaling Relations


MOSFET - Miniaturization RulesThe consequences of applying the Constant-Field scaling rules

K

x

K

V

qKNx dSB

BB

sd

maxmax 2

2'

K

V

K

VqKN

KCK

V

KC

QV TSB

BBsox

Bs

ox

fmsT ~'22

1'2''

K

I

K

V

K

V

K

V

K

V

KdL

ZI DDDTG

ox

oxD

2'

1. Depleted Region

2. Threshold Voltage

3. Drain Current


International Technology Roadmap for SemiconductorsITRS for Deep Submicron CMOS Technologies

Technology node (nm)

Gate length LG (nm)

Voltage supply (V)

Dielectric equivalent thickness (nm)

Threshold voltage VTH(V)

Leakage current (µA/µm)

On state current (µA/µm)

NMOS delay – CV/I (ps)


MOSFET - Miniaturization ProblemsStandard Size

L decreased

(Holding all other parameters constant)


Depleted Region

LDD: depleted region of drain

L’=L-LDD

B

ddsDD qN

VL

2

Vdd ≈ VD-VD,sat

VD,sat ≈ VG-VTo

Influence of the drain depletion region


Reduced Early voltage

A. B. Miniaturized gate

Standard gate

Reduced breakdown voltage

• Punch-through

Consequences of an excessively large drain depletion region


Reduction of threshold voltage VT

Review: (std. channel lengths)

)2(2'

12 BBBs

GBFBT VqN

CVV

Qd= q Xdmax W Na L

• At miniaturized scales, the depletion regions of S and D substitute an important part of Qd

•This reduced the threshold voltage (VT) compared with standard channel lengths


MOSFET - Miniaturization ProblemsEffects of High Electric Fields:

1. Breakdown

• Breakdown of gate oxide (Emax ~ 5x106 V/cm)

• Breakdown of the drain-substrate junction

2. Generation of Hot Electrons

• EKinetic > EG

• i.e. Avalanche effects


Electrical field along the channel


Energy-band diagram at the semiconductor surface from source to drain - DIBL

DIBL - Drain-Induced BarrierLowering effect in the latter

Short-Channel Effect (SCE)

(a) Long channel MOSFETs (b) Short-channel MOSFETs

Dashed lines VD = 0, solid lines VD > 0.

DIBL


MOSFET: Hot Electrons


MOSFET: Hot Electron Effects

1. Injection and trapping Instability

2. Avalanche multiplication Holes

3. Substrate Current Polarization of substrate

4. Injection of electrons Current leakage and breakdown

5. Bipolar transistor effects Current leakage and breakdown


MOSFET: Lightly Doped Drain (LDD)

DRAINSUB Conventional

LDDP N

N+

Goal: Avoid problems due to hot electrons


The CMOS Power Crisis


Sources of Variability


Improving ION/IOFF

[King Liu]


MOSFET in ON State (VGS > VTH)

2.1

[King Liu]


Optimizing MOSFET Performance


Reduced SCE with Body Biasing


CMOS Technology Scaling

[King Liu]


MOSFET Performance Boosters

[King Liu]


Analog Scaling Parameters

1. Headroom (VDD & VT Scaling)2. Transconductance & output

impedance3. Mismatch (random & systematic)4. Leakage5. Modeling methodology/EDA tools


Headroom: VDD / Vt Scaling

1) VDD cuts down active power consumption for digital circuitry quadratically: P = C V2

2) But VDD/Vt don’t decrease anymore with scaling : flatting out ~ 1V @ 65nm due to substantial static power consumption (dramatic increase in BOTH Off state LATERAL and VERTICAL leakage)

3) Headroom reduction a problem for analog designs

4) Minimum theoretical VGS value:

kT/q = 26 mV at room temp and n = 1 + CD/Cox, in which CD is the bulk Depletion layer capacitance under the channel and Cox the gate oxide capacitance. Note that this value is about 80 mV and does not depend on channel length (n 1.6).

[Bergemont]


Off State lateral leakage & Temperature

Weak inversion mode (below VT) : Id exponentially dependent on the value of Vgs–Vt.

• S does not scale with technology scaling (~ 1.4)• S~ 80mV/decade @ room temp and 100mV/dec @ 85C • Reducing Vt by 100mV increases off‐current by an order of magnitude.•Sharper subthreshold slope is obtained by reducing either T or n, with expensive technologies such as FD‐SOI , FinFet (S~ 60mV/dec)

Exacerbated with Temperature (~ 1.25 mV/C) : For specifications ranging from ‐40C to 85C, shift due to temp alone is ~ 170mV

With S = 65mV/dec & assuming sub-threshold occupies 4-5 decade (resulting in an Ion to Ioff ratio approaching 105, 300mV = Vt would ensure an acceptable Ion/Ioff ratio for digital logic.

[Bergemont]


VT variations issues

Vt variations -> Huge impact on both speed and standby power dissipation.

Example : - speed performance impact due to +/-100mV VT variation is about +/-2.5% in a 5V process with VT of 800mV & rises to +/- 12% in a 1V process with Vt = 200mV !- Standby current : assuming Ids = 1uA at Vgs = Vt, S=100mV/dec, the highest off current in above example would be 100fA for 5V-high Vt and 10nA for 1V-low Vt.

Such a large impact on speed and standby power intolerable• circuit techniques are often required to address this issue• multiple Vt processes offers circuit design flexibility at the expense of cost (Low-Vt for circuit speed and high- Vt to reduce the Ileak)

[Bergemont]


Physics of VT variations

VT variability tied to process variations (random dopant fluctuations RDF & channel length variations)

Standard deviation due to random dopant fluctuations RDF concentration variation is:

AVT improves with scaling (ox) but decrease less than predicted oxide thickness scaling as MOS scaling forces the doping level under the gate to increase

[Bergemont]


Effects of Random Dopant Fluctuations RDF

RDF Random Dopant Fluctuations gettingworse as less dopants in the channel

5000 dopants within (100nm)3 cubeAverage 40 dopants within its 125 sub‐cubes of (20nm)3

Discrete dopants randomly distributed in (Xnm)3

cubes with average conc of 5X10 18 cm3

At minimum L, control and variations are exacerbated, mainly through Vt

‐ Vt dependence on Vds getting worse (SCE)‐ Better control with large W

NMOS VT & Ioff [L down to 20nm for (a) width=200nmand (b) width=20nm at Vd=1.0V (Source TSMC)]

[Bergemont]


Differential amplifier gain analog FOM

R R

Commonly used as good analog FOM

Lambda known also as 1/VAVA called Early Voltage

Mobility on the wish list

General practice : use longer W

Gain limited to < gm/gds

[Bergemont]


Gate Leakage

• For digital circuits, power associated with gate leakage is acceptable until oxide thickness reduces less than 2nm (~1A/cm2) • When high-κ materials are used as the gate insulator in later generation devices, gate leakage currents are greatly reduced.

• Mechanism is tunneling through thin gate oxide.• Gate leakage extremely sensitive to the oxide thickness.• 65nm node shifted the leakage by more than six ordersof magnitude as compared to 0.18 um node

[Bergemont][Bergemont]


Latest changes in CMOS and the implication on Analog design

RESOLUTIONS: (digital scaling)‐ Gate leakage by using High K dielectric‐ Vt variations by using undoped channels and Metal Gate

‐ Lateral leakage by using exotic structures : FinFet , UTSOI, FDSOI


Un‐doped channels

With undoped channels, Fermi potential and the depletion charge are approximatelyzero, and the expression for the threshold voltage becomes:

Thus the threshold voltage of the transistor is essentially set by the gate workfunction.

Two solutions for achieving a Vt ~ 0.35V‐band‐edge gate materials (N+/P+Poly gates) with high channel doping ~ 1X10 18 cm3‐or mid‐gap gate material with low channel doping 1X10 15 cm3

[Bergemont]


Structures to resolve lateral leakage

ISSUEdrain control competing with gate control

SOLUTIONSProvide gate control from more than one side of the channel (Multi‐gate FETs)

Vertical gates: FINFET

Channel consists of two vertical surfaces and the top surface of the fin

(Intel)

Lateral Gates : UTSOI

FDSOI with back planes

Fully Depleted Silicon On Insulator (ST 28nm)

[Bergemont]


Resulting… in good news for analog design

1. Better matching No Vt variation due to RDF Demonstrated with FDSOI (mainly LETI/ST and IBM) & FinFets (INTEL, IMEC)

2. Better gm/gds

0

1

2

3

4

5

6

0 50 100 150 200

STST IBM

Intel

IntelIMEC FINFET

IBM

IBM FDSOILETI FDSOI

BULK

FDSOI (Fully Depleted SOI) betterFINFET sensitive to fin height control

AVT

[Bergemont]


Unknown & Concerns (1)

1. Battle for mainstream technology still not resolved (FDSOI vs. FINFET)

•INTEL : FinFet•ST/IBM: FDSOI•Foundries: ?

IBM

INTEL

2. Expensive: - Resources commitment & IP: INTEL, ST/IBM alliance, TSMC- At least 300mm tools

[Bergemont]


Unknown & Concerns (2)

3. EDA: FDSOI FET similar to a bulk FET ‐> extendapplicability of existing design and EDA tools.FinFET: part of the width of the transistor is inthe vertical direction ‐> traditional EDA toolcannot be used

4.Specific‐ New materials, new difficulties‐ Dual gate diel, embedded NVM


FINFET, FDSOIFINFET Significantly more complex than either strained Si (90nm) or HKMG (<45nm)

4 years in pathfinding phase, 4 years in full‐scale development Thousand of wafers run , large development team (2000+) Compatibility with SoC environment unclear

• Multiple VTs and oxide thickness, body bias power mode• Next issues ?• Highly restrictive design rules ‐> favors adoption by IDM, not foundry• Restrictive design rules ‐> footprint penalty• Incompatibility with existing IP blocks ‐> no IP reuse

EDA availability ? Foundry strategy ?

FDSOI Cost increase ~ $500 EDA on line with current planarCompatibility with SoC environment unclear

• Multiple VTs and oxide thickness, body bias power mode (doped channel or multiple work‐functions ?)

• Rext issues ? [Bergemont]


Foundries benchmark

28nm first note with Metal gate New structure expected 14nm


Conclusions - MOSFET Evolution

[King Liu]


Conclusions

Analog design main issue is headroom

Good news is that matching and Gain improves while scaling digital CMOS

Innovations required to design at lower Vcc


Chip Scale Cs Atomic Clock


Some References• S. M. Sze, Kwok K. Ng, “Semiconductor Devices”, 3rd

Edition, John Wiley and Sons Inc., 2007

• H. Mathieu, H. Fanet, “Physique des Semiconducteurset des composants électroniques”, Dunod, Paris, 2009

• R. Jacob Baker, “CMOS Circuit Design, Layout and Simulation”, 3rd edition, 2010

• A. Bergemont, “Lessons from 15 years of fabdevelopment for deep sub-micron mixed signal ICs”, IEEE Swiss Chapter, March 2012

• T. J. King Liu, “Bulk CMOS Scaling to the End of the Roadmap”, Symposium on VLSI Circuits Short Course, UC Berkeley, June 2012

Documents

HiM 2014 CMOS scaling down for digital, analog and mixed ...phd.epfl.ch/files/content/sites/phd/files/shared/Zarchives/mt... · HiM 2014 CMOS digital, analog & mixed microelectronics